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Initial working code

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commit 072026766df704125e1fa69c7c18c67bd44dd6ca 0 parents
@pksunkara authored
1  .gitignore
@@ -0,0 +1 @@
+*.pyc
62 Automata.py
@@ -0,0 +1,62 @@
+class Automata:
+ def __init__(self):
+ pass;
+
+ def get(self, state, signal):
+ if(state == 'M'):
+ return self._getModified(signal);
+ elif(state == 'E'):
+ return self._getInvalid(signal);
+ elif(state == 'S'):
+ return self._getShared(signal);
+ elif(state == 'I'):
+ return self._getInvalid(signal);
+ return [];
+
+ def _getModified(self, signal):
+ # if signal is BusRdX or BusRd
+ if(signal == 'BX' or signal == 'BR'):
+ return ['M','F'];
+ # if signal is ProcessorRead or ProccesorWrite
+ elif(signal == 'PR' or signal == 'PW'):
+ return ['M'];
+ return [];
+
+ def _getInvalid(self, signal):
+ # if signal is ProcessorRead.
+ if(signal == 'PR'):
+ return ['D','BR'];
+ # if signal is ProcessorWrite.
+ elif(signal == 'PW'):
+ return ['M','BX'];
+ return [];
+
+ def _getExclusive(self, signal):
+ # if signal is ProcessorRead.
+ if(signal == 'PR'):
+ return ['E'];
+ # if signal is ProcessorWrite
+ elif(signal == 'PW'):
+ return ['M'];
+ # if signal is BusRd.
+ elif(signal == 'BR'):
+ return ['S','F'];
+ # if signal is BusRdX.
+ elif(signal == 'BX'):
+ return ['I','F'];
+ return [];
+
+ def _getShared(self, signal):
+ # if signal is ProcessorRead.
+ if(signal == 'PR'):
+ return ['S'];
+ # if signal is ProcessorWrite.
+ elif(signal == 'PW'):
+ return ['M','BX'];
+ # if signal is BusRdX.
+ elif(signal == 'BX'):
+ return ['I','F'];
+ # if signal is BusRd.
+ elif(signal == 'BR'):
+ return ['S','F'];
+ return [];
209 Core.py
@@ -0,0 +1,209 @@
+from Automata import *
+
+"""
+ Physical address generated by processor is as:
+ --------------------------------------------------
+ |20-bit Tag| 6-bit Set | 4-bit Word | 2-bit Byte |
+ --------------------------------------------------
+
+ 16KB capacity, 64B block size, 4B word size & 4 associativity.
+"""
+
+class Block:
+ def __init__(self, state):
+ self._state = state;
+ self._lfu = 1000;
+
+ def setState(self, state):
+ self._state = state;
+
+ def getState(self):
+ return self._state;
+
+ def getLFU(self):
+ return self._lfu;
+
+ def decrLFU(self):
+ self._lfu =- 1;
+
+class SetBlock:
+ def __init__(self):
+ self._tagMem = {};
+ self._dataMem = {};
+
+ def set(self, s, t, state):
+ if(self._tagMem.has_key(s)):
+ self._tagMem[s] = t;
+ del self._dataMem[s];
+ self._dataMem[s] = Block(state);
+ return True;
+ elif(len(self._tagMem.keys()) < 64):
+ self._tagMem[s] = t;
+ self._dataMem[s] = Block(state);
+ return True;
+ return False;
+
+ def setState(self, s, t, state):
+ if(self._tagMem.has_key(s) and self._tagMem[s]==t):
+ print "<%s, %s> %s -> %s"%(s, t, self._dataMem[s].getState(), state);
+ self._dataMem[s].setState(state);
+
+ def get(self, s, t):
+ if(self._tagMem.has_key(s) and self._tagMem[s]==t):
+ return [self._dataMem[s].getState()];
+ return [];
+
+ def getLFU(self, s):
+ if(self._tagMem.has_key(s)):
+ return self._dataMem[s].getLFU();
+ return -1;
+
+ def decrLFU(self, s, t):
+ if(self._tagMem.has_key(s) and self._tagMem[s]==t):
+ self._dataMem[s].decrLFU();
+
+class Cache:
+ def __init__(self):
+ self._block0 = SetBlock();
+ self._block1 = SetBlock();
+ self._block2 = SetBlock();
+ self._block3 = SetBlock();
+
+ def getState(self, s, t):
+ state = self._block0.get(s, t);
+ if(len(state)==1):
+ self._block0.decrLFU(s, t);
+ return state;
+ state = self._block1.get(s, t);
+ if(len(state)==1):
+ self._block1.decrLFU(s, t);
+ return state;
+ state = self._block2.get(s, t);
+ if(len(state)==1):
+ self._block2.decrLFU(s, t);
+ return state;
+ state = self._block3.get(s, t);
+ if(len(state)==1):
+ self._block3.decrLFU(s, t);
+ return state;
+ return [];
+
+ def setState(self, s, t, nState):
+ state = self._block0.get(s, t);
+ if(len(state)==1):
+ self._block0.set(s, t, nState);
+ return;
+ state = self._block1.get(s, t);
+ if(len(state)==1):
+ self._block1.set(s, t, nState);
+ return;
+ state = self._block2.get(s, t);
+ if(len(state)==1):
+ self._block2.set(s, t, nState);
+ return;
+ state = self._block3.get(s, t);
+ if(len(state)==1):
+ self._block3.set(s, t, nState);
+ return;
+ idLFU = self.__idLFU(s);
+ if(idLFU==0):
+ self._block0.set(s, t, nState);
+ elif(idLFU==1):
+ self._block1.set(s, t, nState);
+ elif(idLFU==2):
+ self._block2.set(s, t, nState);
+ else:
+ self._block3.set(s, t, nState);
+
+ def changeState(self, s, t, nState):
+ state = self._block0.get(s, t);
+ if(len(state)==1):
+ self._block0.setState(s, t, nState);
+ return;
+ state = self._block1.get(s, t);
+ if(len(state)==1):
+ self._block1.setState(s, t, nState);
+ return;
+ state = self._block2.get(s, t);
+ if(len(state)==1):
+ self._block2.setState(s, t, nState);
+ return;
+ state = self._block3.get(s, t);
+ if(len(state)==1):
+ self._block3.setState(s, t, nState);
+
+ def __idLFU(self, s):
+ countLFU = [self._block0.getLFU(s)];
+ if(countLFU[0]==-1):
+ return 0;
+ countLFU.append(self._block1.getLFU(s));
+ if(countLFU[1]==-1):
+ return 1;
+ countLFU.append(self._block2.getLFU(s));
+ if(countLFU[2]==-1):
+ return 2;
+ countLFU.append(self._block3.getLFU(s));
+ if(countLFU[3]==-1):
+ return 3;
+ idLFU = 0;
+ for i in range(1,4):
+ if(countLFU[idLFU] > countLFU[i]):
+ idLFU = i;
+ return idLFU;
+
+class Core:
+ def __init__(self):
+ self._cache = Cache();
+ self._automata = Automata();
+
+ self._coherenceMisses = 0;
+ self._cacheMisses = 0;
+
+ def printStats(self, name):
+ print "Core %s:"%name
+ print "\tCache Misses:", self._cacheMisses
+ print "\tCoherence Misses:", self._coherenceMisses
+
+ def read(self, s, t):
+ state = self._cache.getState(s, t);
+ # cache hit
+ if(len(state)==1 and state[0]!='I'):
+ return [];
+ # cacheBlock in Invalid state
+ elif(len(state)==1 and state[0]=='I'):
+ self._coherenceMisses = self._coherenceMisses + 1;
+ return ['BR','I'];
+ # cache miss
+ else:
+ self._cacheMisses = self._cacheMisses + 1;
+ return ['BR'];
+
+ def write(self, s, t):
+ state = self._cache.getState(s, t);
+ if(len(state)==0):
+ self._cacheMisses = self._cacheMisses + 1
+ self._cache.setState(s, t, 'M');
+ else:
+ if state[0]=='I':
+ self._coherenceMisses = self._coherenceMisses + 1
+ self._cache.changeState(s, t, 'M');
+ return ['BX'];
+
+ def request(self, s, t, request):
+ state = self._cache.getState(s, t);
+ if(len(state)==0):
+ return []
+ mesiTxn = self._automata.get(state[0],request);
+ if request=='BR' and len(mesiTxn) !=0 :
+ self._cache.changeState(s, t, mesiTxn[0]);
+ return state;
+ elif request=='BX' and len(mesiTxn)!=0:
+ self._cache.changeState(s, t, mesiTxn[0]);
+ return [];
+ return [];
+
+ def new(self, s, t, state):
+ self._cache.setState(s, t, state);
+
+ def change(self, s, t,state):
+ self._cache.changeState(s, t, state);
110 __main__.py
@@ -0,0 +1,110 @@
+import sys, Core
+from math import *
+
+if(len(sys.argv)!=2):
+ print "Usage: python . <case>"
+ sys.exit(1);
+
+try:
+ inputlines = open(sys.argv[1],'r').readlines()[1:]
+except IOError:
+ print "%s: no such file or directory"%sys.argv[1]
+ sys.exit(1);
+
+def getSetTag(hexa):
+ bina = bin(int(hexa,16))[2:].zfill(32)
+ s,t = 0,0
+ for bit in bina[0:20]:
+ t = t*2 + int(bit);
+ for bit in bina[20:26]:
+ s = s*2 + int(bit);
+ return [s,t]
+
+def handler(result, trace, c0, c1, c2, c3):
+ addr = getSetTag(trace[2])
+ blockFound = 0
+ response = c1.request(addr[0], addr[1], 'BR')
+ if response:
+ if len(result) == 2:
+ c0.change(addr[0], addr[1], 'S')
+ elif len(result) == 1:
+ c0.new(addr[0], addr[1], 'S')
+ blockFound = 1
+ response = c2.request(addr[0], addr[1], 'BR')
+ if response:
+ if len(result) == 2 :
+ c0.change(addr[0], addr[1], 'S')
+ elif len(result) == 1:
+ c0.new(addr[0], addr[1], 'S')
+ blockFound = 1
+ response = c3.request(addr[0], addr[1], 'BR')
+ if response:
+ if len(result) == 2:
+ c0.change(addr[0], addr[1], 'S')
+ elif len(result) == 1:
+ c0.new(addr[0], addr[1], 'S')
+ blockFound = 1
+ if blockFound == 0:
+ if len(result) == 2:
+ c0.change(addr[0], addr[1], 'E')
+ elif len(result) == 1:
+ c0.new(addr[0], addr[1], 'E')
+ return (c0, c1, c2, c3)
+
+def execute(trace):
+ buf = trace[0]
+ rw = trace[1]
+ addr = getSetTag(trace[2])
+
+ if buf == '0':
+ if rw == '0':
+ result = core[1].read(addr[0], addr[1])
+ if len(result) != 0:
+ (core[1], core[2], core[3], core[4]) = handler(result, trace, core[1], core[2], core[3], core[4])
+ elif rw == '1':
+ result = core[1].write(addr[0], addr[1])
+ core[2].change(addr[0], addr[1], 'I')
+ core[3].change(addr[0], addr[1], 'I')
+ core[4].change(addr[0], addr[1], 'I')
+ if buf == '1':
+ if rw == '0':
+ result = core[2].read(addr[0], addr[1])
+ if len(result) != 0:
+ (core[2], core[1], core[3], core[4]) = handler(result, trace, core[2], core[1], core[3], core[4])
+ elif rw == '1':
+ result = core[2].write(addr[0], addr[1])
+ core[1].change(addr[0], addr[1], 'I')
+ core[3].change(addr[0], addr[1], 'I')
+ core[4].change(addr[0], addr[1], 'I')
+ if buf == '2':
+ if rw == '0':
+ result = core[3].read(addr[0], addr[1])
+ if len(result) != 0:
+ (core[3], core[2], core[1], core[4]) = handler(result, trace, core[3], core[2], core[1], core[4])
+ elif rw == '1':
+ result = core[3].write(addr[0], addr[1])
+ core[2].change(addr[0], addr[1], 'I')
+ core[1].change(addr[0], addr[1], 'I')
+ core[4].change(addr[0], addr[1], 'I')
+ if buf == '3':
+ if rw == '0':
+ result = core[4].read(addr[0], addr[1])
+ if len(result) != 0:
+ (core[4], core[2], core[3], core[1]) = handler(result, trace, core[4], core[2], core[3], core[1])
+ elif rw == '1':
+ result = core[4].write(addr[0], addr[1])
+ core[2].change(addr[0], addr[1], 'I')
+ core[3].change(addr[0], addr[1], 'I')
+ core[1].change(addr[0], addr[1], 'I')
+
+def printStats():
+ core[1].printStats("One")
+ core[2].printStats("Two")
+ core[3].printStats("Three")
+ core[4].printStats("Four")
+
+core = [0, Core.Core(), Core.Core(), Core.Core(), Core.Core()]
+for i in inputlines:
+ execute(i.strip().split()[1:])
+print ""
+printStats()
31 cases/a.txt
@@ -0,0 +1,31 @@
+time core r/w address
+4427213 0 0 b236e0
+4427214 3 0 b14278
+4427215 1 0 b20278
+4427216 0 0 a236e8
+4427216 3 0 b24660
+4427216 3 0 b24660
+4427217 1 1 b24660
+4427217 0 0 1236f0
+4427217 2 1 b20278
+4427219 3 0 b24668
+4427220 1 1 b236e0
+4427222 1 1 b20268
+4427223 1 1 b20270
+4427223 0 0 2236f8
+4427224 0 0 6236e7
+4427224 1 1 b20278
+4427226 3 0 b24678
+4427226 2 0 b14280
+4427227 2 0 b24288
+4427228 3 1 b24288
+4427228 0 1 b236e0
+4427228 2 0 b14280
+4427229 2 0 b24288
+4427230 0 1 d236e8
+4427231 2 0 b1fa80
+4427231 3 1 b24660
+4427231 0 1 b236f0
+4427232 0 1 b236f8
+4427233 1 0 b204c0
+4427233 3 1 b24668
30 cases/b.txt
@@ -0,0 +1,30 @@
+time core r/w address
+4427213 0 0 b236e0
+4427214 3 0 b14278
+4427215 1 0 b20278
+4427216 0 0 a236e8
+4427216 3 0 b24660
+4427217 1 1 b24660
+4427217 0 0 1236f0
+4427217 2 1 b20278
+4427219 3 0 b24668
+4427220 3 0 b24670
+4427220 1 1 b236e0
+4427222 1 1 b20268
+4427223 1 1 b20270
+4427223 0 0 a236e8
+4427224 1 1 b20278
+4427226 3 0 b24678
+4427226 2 0 b14280
+4427227 2 0 b24288
+4427228 3 1 b24288
+4427228 0 1 b236e0
+4427228 2 0 b14280
+4427229 2 0 b24288
+4427230 0 1 d236e8
+4427231 2 0 b1fa80
+4427231 3 1 b24660
+4427231 0 1 b236f0
+4427232 0 1 b236f8
+4427233 1 0 b204c0
+4427233 3 1 b24668
20 cases/c.txt
@@ -0,0 +1,20 @@
+clk core r/w address
+210 0 0 b236e0
+211 3 1 b14278
+212 1 0 b00278
+212 2 0 b236e0
+213 0 0 b236e0
+214 3 0 b14278
+215 1 0 b20278
+216 0 1 b236e8
+217 3 0 b236f0
+218 2 0 b236e0
+219 3 0 b24668
+220 1 1 b20260
+220 2 0 b24670
+220 3 1 b24676
+223 1 0 b236e0
+223 3 0 b236e0
+227 0 1 b236e0
+228 1 0 b236e0
+229 3 0 b236e0
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