diff --git a/.travis.yml b/.travis.yml index 9abc526..259a35d 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,6 +1,7 @@ language: python python: - "2.7" + - "3.6" env: - PLATFORMIO_PROJECT_DIR=examples/counter diff --git a/appveyor.yml b/appveyor.yml index b31b906..caafaeb 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -7,8 +7,8 @@ environment: install: - cmd: git submodule update --init --recursive - - cmd: SET PATH=%PATH%;C:\Python27\Scripts - - cmd: pip install -U https://github.com/platformio/platformio/archive/develop.zip + - cmd: SET PATH=C:\Python36\Scripts;%PATH% + - cmd: pip3 install -U https://github.com/platformio/platformio/archive/develop.zip - cmd: platformio platform install file://. test_script: diff --git a/platform.json b/platform.json index bcdcae9..0d6c207 100644 --- a/platform.json +++ b/platform.json @@ -2,17 +2,22 @@ "name": "lattice_ice40", "title": "Lattice iCE40", "description": "The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680 Look-Up Tables (LUTs). In addition to LUT-based,low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features allow the devices to be used in low-cost, high-volume consumer and system applications.", - "url": "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40.aspx", - "homepage": "http://platformio.org/platforms/lattice_ice40", + "homepage": "http://www.latticesemi.com/Products/FPGAandCPLD/iCE40.aspx", "license": "Apache-2.0", + "keywords": [ + "dev-platform", + "Lattice", + "iCE40", + "FPGA" + ], "engines": { - "platformio": "^3.0.0" + "platformio": "<5" }, "repository": { "type": "git", "url": "https://github.com/platformio/platform-lattice_ice40.git" }, - "version": "1.2.2", + "version": "1.2.3", "packageRepositories": [ "https://dl.bintray.com/platformio/dl-packages/manifest.json", "http://dl.platformio.org/packages/manifest.json"