From ebfa04de5aa90428e774bd029777e0e882e980d4 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 23 Mar 2021 15:52:26 +0100 Subject: [PATCH 1/6] Add native-blink example Adds a native blink example using only one C file and the device header file for comfort from https://github.com/gicking/STM8_headers The MIT license is FOSS and a copy of the license is included per license requirements. --- examples/native-blink/.gitignore | 1 + examples/native-blink/LICENSE_STM8_HEADERS | 21 + examples/native-blink/README.rst | 54 + examples/native-blink/include/README | 39 + examples/native-blink/lib/README | 46 + examples/native-blink/platformio.ini | 22 + examples/native-blink/src/STM8S103F3.h | 4526 ++++++++++++++ examples/native-blink/src/STM8S207K8.h | 4648 ++++++++++++++ examples/native-blink/src/STM8S208RB.h | 6376 ++++++++++++++++++++ examples/native-blink/src/main.c | 115 + examples/native-blink/test/README | 11 + 11 files changed, 15859 insertions(+) create mode 100644 examples/native-blink/.gitignore create mode 100644 examples/native-blink/LICENSE_STM8_HEADERS create mode 100644 examples/native-blink/README.rst create mode 100644 examples/native-blink/include/README create mode 100644 examples/native-blink/lib/README create mode 100644 examples/native-blink/platformio.ini create mode 100644 examples/native-blink/src/STM8S103F3.h create mode 100644 examples/native-blink/src/STM8S207K8.h create mode 100644 examples/native-blink/src/STM8S208RB.h create mode 100644 examples/native-blink/src/main.c create mode 100644 examples/native-blink/test/README diff --git a/examples/native-blink/.gitignore b/examples/native-blink/.gitignore new file mode 100644 index 0000000..03f4a3c --- /dev/null +++ b/examples/native-blink/.gitignore @@ -0,0 +1 @@ +.pio diff --git a/examples/native-blink/LICENSE_STM8_HEADERS b/examples/native-blink/LICENSE_STM8_HEADERS new file mode 100644 index 0000000..41ef1a0 --- /dev/null +++ b/examples/native-blink/LICENSE_STM8_HEADERS @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2020 Georg Icking-Konert + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/examples/native-blink/README.rst b/examples/native-blink/README.rst new file mode 100644 index 0000000..3632d76 --- /dev/null +++ b/examples/native-blink/README.rst @@ -0,0 +1,54 @@ +.. Copyright 2021-present PlatformIO + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +How to build PlatformIO based project +===================================== + +1. `Install PlatformIO Core `_ +2. Download `development platform with examples `_ +3. Extract ZIP archive +4. Run these commands: + +.. code-block:: bash + + # Change directory to example + > cd platform-ststm8/examples/spl-blink + + # Build project + > platformio run + + # Upload firmware + > platformio run --target upload + + # Build specific environment + > platformio run -e stm8sdisco + + # Upload firmware for the specific environment + > platformio run -e stm8sdisco --target upload + + # Clean build files + > platformio run --target clean + +Project description +=================== + +This is a baremetal project targeting three STM8S example chips / boards : +* STM8S103F3 breakout board +* Nucleo-8S207K8 +* Nucleo-8S208RB + +The pinmapping is such that the built-in LED of those boards is automatically used. + +The project does not any framework like Arduino or SPL for compilation, hence no `framework = ..` line in the `platformio.ini`. Only one `.c` file and the right `.h` device header file is used. + +The project uses a copy of the FOSS header files for the three devices from https://github.com/gicking/STM8_headers, which are placed under the MIT license. A copy of the license is included. + +If you wish to adapt this example for more chips and boards, add the appropriate header file from the referenced repository and include that header. \ No newline at end of file diff --git a/examples/native-blink/include/README b/examples/native-blink/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/examples/native-blink/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/native-blink/lib/README b/examples/native-blink/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/examples/native-blink/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/native-blink/platformio.ini b/examples/native-blink/platformio.ini new file mode 100644 index 0000000..c19fae3 --- /dev/null +++ b/examples/native-blink/platformio.ini @@ -0,0 +1,22 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[env:stm8sblue] +platform = https://github.com/platformio/platform-ststm8.git +board = stm8sblue +upload_protocol = stlinkv2 + +[env:nucleo_8s207k8] +platform = https://github.com/platformio/platform-ststm8.git +board = nucleo_8s207k8 + +[env:nucleo_8s208rb] +platform = https://github.com/platformio/platform-ststm8.git +board = nucleo_8s208rb diff --git a/examples/native-blink/src/STM8S103F3.h b/examples/native-blink/src/STM8S103F3.h new file mode 100644 index 0000000..c03f385 --- /dev/null +++ b/examples/native-blink/src/STM8S103F3.h @@ -0,0 +1,4526 @@ +/*------------------------------------------------------------------------- + + STM8S103F3.h - Device Declarations + + STM8S/STM8AF, low density without ROM bootloader + + Copyright (C) 2020, Georg Icking-Konert + + Mainstream Access line 8-bit MCU with 8 Kbytes Flash, 16 MHz CPU, integrated EEPROM + + datasheet: https://www.st.com/resource/en/datasheet/stm8s103f3.pdf + reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf + + MIT License + + Copyright (c) 2020 Georg Icking-Konert + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. + +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- + MODULE DEFINITION FOR MULTIPLE INCLUSION +-------------------------------------------------------------------------*/ +#ifndef STM8S103F3_H +#define STM8S103F3_H + +// DEVICE NAME +#define DEVICE_STM8S103F3 + +// DEVICE FAMILY +#define FAMILY_STM8S + +// required for C++ +#ifdef __cplusplus + extern "C" { +#endif + + +/*------------------------------------------------------------------------- + INCLUDE FILES +-------------------------------------------------------------------------*/ +#include + + +/*------------------------------------------------------------------------- + COMPILER SPECIFIC SETTINGS +-------------------------------------------------------------------------*/ + +// Cosmic compiler +#if defined(__CSMC__) + + // macros to unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine + #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine + + // definition of inline functions + #define INLINE @inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling + #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode + #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + + +// IAR Compiler +#elif defined(__ICCSTM8__) + + // include intrinsic functions + #include + + // macros to unify ISR declaration and implementation + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define ISR_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define ISR_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling + #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt + #define ENTER_HALT() __halt() ///< put controller to HALT mode + #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) + + +// SDCC compiler +#elif defined(__SDCC) + + // store SDCC version in preprocessor friendly way + #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ + + __SDCC_VERSION_MINOR * 100 \ + + __SDCC_VERSION_PATCH) + + // unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine + #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 + #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine + #else + #error traps require SDCC >=3.4.3. Please update! + #endif + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling + #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode + #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + +// unsupported compiler -> stop +#else + #error: compiler not supported +#endif + + +/*------------------------------------------------------------------------- + FOR CONVENIENT PIN ACCESS +-------------------------------------------------------------------------*/ + +#define PIN0 0x01 +#define PIN1 0x02 +#define PIN2 0x04 +#define PIN3 0x08 +#define PIN4 0x10 +#define PIN5 0x20 +#define PIN6 0x40 +#define PIN7 0x80 + + +/*------------------------------------------------------------------------- + DEVICE MEMORY (size in bytes) +-------------------------------------------------------------------------*/ + +// RAM +#define RAM_ADDR_START 0x000000 +#define RAM_ADDR_END 0x0003FF +#define RAM_SIZE 1024 + + +// FLASH +#define FLASH_ADDR_START 0x008000 +#define FLASH_ADDR_END 0x009FFF +#define FLASH_SIZE 8192 + + +// SFR1 +#define SFR1_ADDR_START 0x005000 +#define SFR1_ADDR_END 0x0057FF +#define SFR1_SIZE 2048 + + +// SFR2 +#define SFR2_ADDR_START 0x007F00 +#define SFR2_ADDR_END 0x007FFF +#define SFR2_SIZE 256 + + +// EEPROM +#define EEPROM_ADDR_START 0x004000 +#define EEPROM_ADDR_END 0x00427F +#define EEPROM_SIZE 640 + + +// OPTION +#define OPTION_ADDR_START 0x004800 +#define OPTION_ADDR_END 0x00480A +#define OPTION_SIZE 11 + + +// ID +#define ID_ADDR_START 0x004865 +#define ID_ADDR_END 0x004870 +#define ID_SIZE 12 + + +// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) +#define FLASH_ADDR_WIDTH 16 ///< width of address space +#define FLASH_POINTER_T uint16_t ///< address variable type + + +/*------------------------------------------------------------------------- + UNIQUE IDENTIFIER (size in bytes) +-------------------------------------------------------------------------*/ + +#define UID_ADDR_START 0x4865 ///< start address of unique identifier +#define UID_SIZE 12 ///< size of unique identifier [B] +#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N + + +/*------------------------------------------------------------------------- + MISC OPTIONS +-------------------------------------------------------------------------*/ + +/// LSI frequency measurement channel +#define LSI_MEASURE_TIM1_IC1 + + +/*------------------------------------------------------------------------- + ISR Vector Table (SDCC, IAR) + Notes: + - IAR has an IRQ offset of +2 compared to datasheet and below numbers + - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' + - different interrupt sources may share the same IRQ +-------------------------------------------------------------------------*/ + +// interrupt IRQ +#define _TLI_VECTOR_ 0 +#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR +#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR +#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR +#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR +#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR +#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR +#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR +#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR +#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR +#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR +#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR +#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR +#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR +#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR +#define _TIM1_CAPCOM_BIF_VECTOR_ 11 ///< TIM1_CAPCOM_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_TIF_VECTOR_ 11 ///< TIM1_CAPCOM_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR +#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR +#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR +#define _UART1_T_TC_VECTOR_ 17 ///< UART1_T_TC interrupt vector: enable: UART1_CR2.TCIEN, pending: UART1_SR.TC, priority: ITC_SPR5.VECT17SPR +#define _UART1_T_TXE_VECTOR_ 17 ///< UART1_T_TXE interrupt vector: enable: UART1_CR2.TIEN, pending: UART1_SR.TXE, priority: ITC_SPR5.VECT17SPR +#define _UART1_R_IDLE_VECTOR_ 18 ///< UART1_R_IDLE interrupt vector: enable: UART1_CR2.ILIEN, pending: UART1_SR.IDLE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_LBDF_VECTOR_ 18 ///< UART1_R_LBDF interrupt vector: enable: UART1_CR4.LBDIEN, pending: UART1_CR4.LBDF, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_OR_VECTOR_ 18 ///< UART1_R_OR interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.OR_LHE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_PE_VECTOR_ 18 ///< UART1_R_PE interrupt vector: enable: UART1_CR1.PIEN, pending: UART1_SR.PE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_RXNE_VECTOR_ 18 ///< UART1_R_RXNE interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.RXNE, priority: ITC_SPR5.VECT18SPR +#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR +#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR +#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR +#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR +#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR +#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR +#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR +#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR +#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR +#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR +#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR +#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR +#define _ADC1_AWDG_VECTOR_ 22 ///< ADC1_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS0_VECTOR_ 22 ///< ADC1_AWS0 interrupt vector: enable: ADC_AWCRL.AWEN0, pending: ADC_AWSRL.AWS0, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS1_VECTOR_ 22 ///< ADC1_AWS1 interrupt vector: enable: ADC_AWCRL.AWEN1, pending: ADC_AWSRL.AWS1, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS2_VECTOR_ 22 ///< ADC1_AWS2 interrupt vector: enable: ADC_AWCRL.AWEN2, pending: ADC_AWSRL.AWS2, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS3_VECTOR_ 22 ///< ADC1_AWS3 interrupt vector: enable: ADC_AWCRL.AWEN3, pending: ADC_AWSRL.AWS3, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS4_VECTOR_ 22 ///< ADC1_AWS4 interrupt vector: enable: ADC_AWCRL.AWEN4, pending: ADC_AWSRL.AWS4, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS5_VECTOR_ 22 ///< ADC1_AWS5 interrupt vector: enable: ADC_AWCRL.AWEN5, pending: ADC_AWSRL.AWS5, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS6_VECTOR_ 22 ///< ADC1_AWS6 interrupt vector: enable: ADC_AWCRL.AWEN6, pending: ADC_AWSRL.AWS6, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS7_VECTOR_ 22 ///< ADC1_AWS7 interrupt vector: enable: ADC_AWCRL.AWEN7, pending: ADC_AWSRL.AWS7, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS8_VECTOR_ 22 ///< ADC1_AWS8 interrupt vector: enable: ADC_AWCRH.AWEN8, pending: ADC_AWSRH.AWS8, priority: ITC_SPR6.VECT22SPR +#define _ADC1_AWS9_VECTOR_ 22 ///< ADC1_AWS9 interrupt vector: enable: ADC_AWCRH.AWEN9, pending: ADC_AWSRH.AWS9, priority: ITC_SPR6.VECT22SPR +#define _ADC1_EOC_VECTOR_ 22 ///< ADC1_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR +#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR +#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR +#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR + + +/*------------------------------------------------------------------------- + DEFINITION OF STM8 PERIPHERAL REGISTERS +-------------------------------------------------------------------------*/ + +//------------------------ +// Module ADC1 +//------------------------ + +/** struct containing ADC1 module registers */ +typedef struct { + + /** ADC data buffer registers (DB0RH at 0x53e0) */ + union { + + /// bytewise access to DB0RH + uint8_t byte; + + /// bitwise access to register DB0RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB0RH bitfield + + /// register _ADC1_DB0RH reset value + #define sfr_ADC1_DB0RH_RESET_VALUE ((uint8_t) 0x00) + + } DB0RH; + + + /** ADC data buffer registers (DB0RL at 0x53e1) */ + union { + + /// bytewise access to DB0RL + uint8_t byte; + + /// bitwise access to register DB0RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB0RL bitfield + + /// register _ADC1_DB0RL reset value + #define sfr_ADC1_DB0RL_RESET_VALUE ((uint8_t) 0x00) + + } DB0RL; + + + /** ADC data buffer registers (DB1RH at 0x53e2) */ + union { + + /// bytewise access to DB1RH + uint8_t byte; + + /// bitwise access to register DB1RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB1RH bitfield + + /// register _ADC1_DB1RH reset value + #define sfr_ADC1_DB1RH_RESET_VALUE ((uint8_t) 0x00) + + } DB1RH; + + + /** ADC data buffer registers (DB1RL at 0x53e3) */ + union { + + /// bytewise access to DB1RL + uint8_t byte; + + /// bitwise access to register DB1RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB1RL bitfield + + /// register _ADC1_DB1RL reset value + #define sfr_ADC1_DB1RL_RESET_VALUE ((uint8_t) 0x00) + + } DB1RL; + + + /** ADC data buffer registers (DB2RH at 0x53e4) */ + union { + + /// bytewise access to DB2RH + uint8_t byte; + + /// bitwise access to register DB2RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB2RH bitfield + + /// register _ADC1_DB2RH reset value + #define sfr_ADC1_DB2RH_RESET_VALUE ((uint8_t) 0x00) + + } DB2RH; + + + /** ADC data buffer registers (DB2RL at 0x53e5) */ + union { + + /// bytewise access to DB2RL + uint8_t byte; + + /// bitwise access to register DB2RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB2RL bitfield + + /// register _ADC1_DB2RL reset value + #define sfr_ADC1_DB2RL_RESET_VALUE ((uint8_t) 0x00) + + } DB2RL; + + + /** ADC data buffer registers (DB3RH at 0x53e6) */ + union { + + /// bytewise access to DB3RH + uint8_t byte; + + /// bitwise access to register DB3RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB3RH bitfield + + /// register _ADC1_DB3RH reset value + #define sfr_ADC1_DB3RH_RESET_VALUE ((uint8_t) 0x00) + + } DB3RH; + + + /** ADC data buffer registers (DB3RL at 0x53e7) */ + union { + + /// bytewise access to DB3RL + uint8_t byte; + + /// bitwise access to register DB3RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB3RL bitfield + + /// register _ADC1_DB3RL reset value + #define sfr_ADC1_DB3RL_RESET_VALUE ((uint8_t) 0x00) + + } DB3RL; + + + /** ADC data buffer registers (DB4RH at 0x53e8) */ + union { + + /// bytewise access to DB4RH + uint8_t byte; + + /// bitwise access to register DB4RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB4RH bitfield + + /// register _ADC1_DB4RH reset value + #define sfr_ADC1_DB4RH_RESET_VALUE ((uint8_t) 0x00) + + } DB4RH; + + + /** ADC data buffer registers (DB4RL at 0x53e9) */ + union { + + /// bytewise access to DB4RL + uint8_t byte; + + /// bitwise access to register DB4RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB4RL bitfield + + /// register _ADC1_DB4RL reset value + #define sfr_ADC1_DB4RL_RESET_VALUE ((uint8_t) 0x00) + + } DB4RL; + + + /** ADC data buffer registers (DB5RH at 0x53ea) */ + union { + + /// bytewise access to DB5RH + uint8_t byte; + + /// bitwise access to register DB5RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB5RH bitfield + + /// register _ADC1_DB5RH reset value + #define sfr_ADC1_DB5RH_RESET_VALUE ((uint8_t) 0x00) + + } DB5RH; + + + /** ADC data buffer registers (DB5RL at 0x53eb) */ + union { + + /// bytewise access to DB5RL + uint8_t byte; + + /// bitwise access to register DB5RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB5RL bitfield + + /// register _ADC1_DB5RL reset value + #define sfr_ADC1_DB5RL_RESET_VALUE ((uint8_t) 0x00) + + } DB5RL; + + + /** ADC data buffer registers (DB6RH at 0x53ec) */ + union { + + /// bytewise access to DB6RH + uint8_t byte; + + /// bitwise access to register DB6RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB6RH bitfield + + /// register _ADC1_DB6RH reset value + #define sfr_ADC1_DB6RH_RESET_VALUE ((uint8_t) 0x00) + + } DB6RH; + + + /** ADC data buffer registers (DB6RL at 0x53ed) */ + union { + + /// bytewise access to DB6RL + uint8_t byte; + + /// bitwise access to register DB6RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB6RL bitfield + + /// register _ADC1_DB6RL reset value + #define sfr_ADC1_DB6RL_RESET_VALUE ((uint8_t) 0x00) + + } DB6RL; + + + /** ADC data buffer registers (DB7RH at 0x53ee) */ + union { + + /// bytewise access to DB7RH + uint8_t byte; + + /// bitwise access to register DB7RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB7RH bitfield + + /// register _ADC1_DB7RH reset value + #define sfr_ADC1_DB7RH_RESET_VALUE ((uint8_t) 0x00) + + } DB7RH; + + + /** ADC data buffer registers (DB7RL at 0x53ef) */ + union { + + /// bytewise access to DB7RL + uint8_t byte; + + /// bitwise access to register DB7RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB7RL bitfield + + /// register _ADC1_DB7RL reset value + #define sfr_ADC1_DB7RL_RESET_VALUE ((uint8_t) 0x00) + + } DB7RL; + + + /** ADC data buffer registers (DB8RH at 0x53f0) */ + union { + + /// bytewise access to DB8RH + uint8_t byte; + + /// bitwise access to register DB8RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB8RH bitfield + + /// register _ADC1_DB8RH reset value + #define sfr_ADC1_DB8RH_RESET_VALUE ((uint8_t) 0x00) + + } DB8RH; + + + /** ADC data buffer registers (DB8RL at 0x53f1) */ + union { + + /// bytewise access to DB8RL + uint8_t byte; + + /// bitwise access to register DB8RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB8RL bitfield + + /// register _ADC1_DB8RL reset value + #define sfr_ADC1_DB8RL_RESET_VALUE ((uint8_t) 0x00) + + } DB8RL; + + + /** ADC data buffer registers (DB9RH at 0x53f2) */ + union { + + /// bytewise access to DB9RH + uint8_t byte; + + /// bitwise access to register DB9RH + struct { + BITS DBH : 8; // bits 0-7 + }; // DB9RH bitfield + + /// register _ADC1_DB9RH reset value + #define sfr_ADC1_DB9RH_RESET_VALUE ((uint8_t) 0x00) + + } DB9RH; + + + /** ADC data buffer registers (DB9RL at 0x53f3) */ + union { + + /// bytewise access to DB9RL + uint8_t byte; + + /// bitwise access to register DB9RL + struct { + BITS DL : 8; // bits 0-7 + }; // DB9RL bitfield + + /// register _ADC1_DB9RL reset value + #define sfr_ADC1_DB9RL_RESET_VALUE ((uint8_t) 0x00) + + } DB9RL; + + + /// Reserved register (12B) + uint8_t Reserved_1[12]; + + + /** ADC control/status register (CSR at 0x5400) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS CH : 4; // bits 0-3 + BITS AWDIE : 1; // bit 4 + BITS EOCIE : 1; // bit 5 + BITS AWD : 1; // bit 6 + BITS EOC : 1; // bit 7 + }; // CSR bitfield + + /// register _ADC1_CSR reset value + #define sfr_ADC1_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + + + /** ADC configuration register 1 (CR1 at 0x5401) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS ADON : 1; // bit 0 + BITS CONT : 1; // bit 1 + BITS : 2; // 2 bits + BITS SPSEL : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR1 bitfield + + /// register _ADC1_CR1 reset value + #define sfr_ADC1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** ADC configuration register 2 (CR2 at 0x5402) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 1; // 1 bit + BITS SCAN : 1; // bit 1 + BITS : 1; // 1 bit + BITS ALIGN : 1; // bit 3 + BITS EXTSEL : 2; // bits 4-5 + BITS EXTTRIG : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _ADC1_CR2 reset value + #define sfr_ADC1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** ADC configuration register 3 (CR3 at 0x5403) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 6; // 6 bits + BITS OVR : 1; // bit 6 + BITS DBUF : 1; // bit 7 + }; // CR3 bitfield + + /// register _ADC1_CR3 reset value + #define sfr_ADC1_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** ADC data register high (DRH at 0x5404) */ + union { + + /// bytewise access to DRH + uint8_t byte; + + /// bitwise access to register DRH + struct { + BITS DH : 8; // bits 0-7 + }; // DRH bitfield + + /// register _ADC1_DRH reset value + #define sfr_ADC1_DRH_RESET_VALUE ((uint8_t) 0x00) + + } DRH; + + + /** ADC data register low (DRL at 0x5405) */ + union { + + /// bytewise access to DRL + uint8_t byte; + + /// bitwise access to register DRL + struct { + BITS DL : 8; // bits 0-7 + }; // DRL bitfield + + /// register _ADC1_DRL reset value + #define sfr_ADC1_DRL_RESET_VALUE ((uint8_t) 0x00) + + } DRL; + + + /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ + union { + + /// bytewise access to TDRH + uint8_t byte; + + /// bitwise access to register TDRH + struct { + BITS TD : 8; // bits 0-7 + }; // TDRH bitfield + + /// register _ADC1_TDRH reset value + #define sfr_ADC1_TDRH_RESET_VALUE ((uint8_t) 0x00) + + } TDRH; + + + /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ + union { + + /// bytewise access to TDRL + uint8_t byte; + + /// bitwise access to register TDRL + struct { + BITS TL : 8; // bits 0-7 + }; // TDRL bitfield + + /// register _ADC1_TDRL reset value + #define sfr_ADC1_TDRL_RESET_VALUE ((uint8_t) 0x00) + + } TDRL; + + + /** ADC high threshold register high (HTRH at 0x5408) */ + union { + + /// bytewise access to HTRH + uint8_t byte; + + /// bitwise access to register HTRH + struct { + BITS HT : 8; // bits 0-7 + }; // HTRH bitfield + + /// register _ADC1_HTRH reset value + #define sfr_ADC1_HTRH_RESET_VALUE ((uint8_t) 0x03) + + } HTRH; + + + /** ADC high threshold register low (HTRL at 0x5409) */ + union { + + /// bytewise access to HTRL + uint8_t byte; + + /// bitwise access to register HTRL + struct { + BITS HT : 2; // bits 0-1 + BITS : 6; // 6 bits + }; // HTRL bitfield + + /// register _ADC1_HTRL reset value + #define sfr_ADC1_HTRL_RESET_VALUE ((uint8_t) 0xFF) + + } HTRL; + + + /** ADC low threshold register high (LTRH at 0x540a) */ + union { + + /// bytewise access to LTRH + uint8_t byte; + + /// bitwise access to register LTRH + struct { + BITS LT : 8; // bits 0-7 + }; // LTRH bitfield + + /// register _ADC1_LTRH reset value + #define sfr_ADC1_LTRH_RESET_VALUE ((uint8_t) 0x00) + + } LTRH; + + + /** ADC low threshold register low (LTRL at 0x540b) */ + union { + + /// bytewise access to LTRL + uint8_t byte; + + /// bitwise access to register LTRL + struct { + BITS LT : 2; // bits 0-1 + BITS : 6; // 6 bits + }; // LTRL bitfield + + /// register _ADC1_LTRL reset value + #define sfr_ADC1_LTRL_RESET_VALUE ((uint8_t) 0x00) + + } LTRL; + + + /** ADC analog watchdog status register high (AWSRH at 0x540c) */ + union { + + /// bytewise access to AWSRH + uint8_t byte; + + /// bitwise access to register AWSRH + struct { + BITS AWS8 : 1; // bit 0 + BITS AWS9 : 1; // bit 1 + BITS : 6; // 6 bits + }; // AWSRH bitfield + + /// register _ADC1_AWSRH reset value + #define sfr_ADC1_AWSRH_RESET_VALUE ((uint8_t) 0x00) + + } AWSRH; + + + /** ADC analog watchdog status register low (AWSRL at 0x540d) */ + union { + + /// bytewise access to AWSRL + uint8_t byte; + + /// bitwise access to register AWSRL + struct { + BITS AWS0 : 1; // bit 0 + BITS AWS1 : 1; // bit 1 + BITS AWS2 : 1; // bit 2 + BITS AWS3 : 1; // bit 3 + BITS AWS4 : 1; // bit 4 + BITS AWS5 : 1; // bit 5 + BITS AWS6 : 1; // bit 6 + BITS AWS7 : 1; // bit 7 + }; // AWSRL bitfield + + /// register _ADC1_AWSRL reset value + #define sfr_ADC1_AWSRL_RESET_VALUE ((uint8_t) 0x00) + + } AWSRL; + + + /** ADC analog watchdog control register high (AWCRH at 0x540e) */ + union { + + /// bytewise access to AWCRH + uint8_t byte; + + /// bitwise access to register AWCRH + struct { + BITS AWEN8 : 1; // bit 0 + BITS AWEN9 : 1; // bit 1 + BITS : 6; // 6 bits + }; // AWCRH bitfield + + /// register _ADC1_AWCRH reset value + #define sfr_ADC1_AWCRH_RESET_VALUE ((uint8_t) 0x00) + + } AWCRH; + + + /** ADC analog watchdog control register low (AWCRL at 0x540f) */ + union { + + /// bytewise access to AWCRL + uint8_t byte; + + /// bitwise access to register AWCRL + struct { + BITS AWEN0 : 1; // bit 0 + BITS AWEN1 : 1; // bit 1 + BITS AWEN2 : 1; // bit 2 + BITS AWEN3 : 1; // bit 3 + BITS AWEN4 : 1; // bit 4 + BITS AWEN5 : 1; // bit 5 + BITS AWEN6 : 1; // bit 6 + BITS AWEN7 : 1; // bit 7 + }; // AWCRL bitfield + + /// register _ADC1_AWCRL reset value + #define sfr_ADC1_AWCRL_RESET_VALUE ((uint8_t) 0x00) + + } AWCRL; + +} ADC1_t; + +/// access to ADC1 SFR registers +#define sfr_ADC1 (*((ADC1_t*) 0x53e0)) + + +//------------------------ +// Module AWU +//------------------------ + +/** struct containing AWU module registers */ +typedef struct { + + /** AWU control/status register 1 (CSR1 at 0x50f0) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS MSR : 1; // bit 0 + BITS : 3; // 3 bits + BITS AWUEN : 1; // bit 4 + BITS AWUF : 1; // bit 5 + BITS : 2; // 2 bits + }; // CSR1 bitfield + + /// register _AWU_CSR1 reset value + #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ + union { + + /// bytewise access to APR + uint8_t byte; + + /// bitwise access to register APR + struct { + BITS APR : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // APR bitfield + + /// register _AWU_APR reset value + #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) + + } APR; + + + /** AWU timebase selection register (TBR at 0x50f2) */ + union { + + /// bytewise access to TBR + uint8_t byte; + + /// bitwise access to register TBR + struct { + BITS AWUTB : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // TBR bitfield + + /// register _AWU_TBR reset value + #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) + + } TBR; + +} AWU_t; + +/// access to AWU SFR registers +#define sfr_AWU (*((AWU_t*) 0x50f0)) + + +//------------------------ +// Module BEEP +//------------------------ + +/** struct containing BEEP module registers */ +typedef struct { + + /** BEEP control/status register (CSR at 0x50f3) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS BEEPDIV : 5; // bits 0-4 + BITS BEEPEN : 1; // bit 5 + BITS BEEPSEL : 2; // bits 6-7 + }; // CSR bitfield + + /// register _BEEP_CSR reset value + #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) + + } CSR; + +} BEEP_t; + +/// access to BEEP SFR registers +#define sfr_BEEP (*((BEEP_t*) 0x50f3)) + + +//------------------------ +// Module CLK +//------------------------ + +/** struct containing CLK module registers */ +typedef struct { + + /** Internal clock control register (ICKR at 0x50c0) */ + union { + + /// bytewise access to ICKR + uint8_t byte; + + /// bitwise access to register ICKR + struct { + BITS HSIEN : 1; // bit 0 + BITS HSIRDY : 1; // bit 1 + BITS FHW : 1; // bit 2 + BITS LSIEN : 1; // bit 3 + BITS LSIRDY : 1; // bit 4 + BITS REGAH : 1; // bit 5 + BITS : 2; // 2 bits + }; // ICKR bitfield + + /// register _CLK_ICKR reset value + #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) + + } ICKR; + + + /** External clock control register (ECKR at 0x50c1) */ + union { + + /// bytewise access to ECKR + uint8_t byte; + + /// bitwise access to register ECKR + struct { + BITS HSEEN : 1; // bit 0 + BITS HSERDY : 1; // bit 1 + BITS : 6; // 6 bits + }; // ECKR bitfield + + /// register _CLK_ECKR reset value + #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) + + } ECKR; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** Clock master status register (CMSR at 0x50c3) */ + union { + + /// bytewise access to CMSR + uint8_t byte; + + /// bitwise access to register CMSR + struct { + BITS CKM : 8; // bits 0-7 + }; // CMSR bitfield + + /// register _CLK_CMSR reset value + #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) + + } CMSR; + + + /** Clock master switch register (SWR at 0x50c4) */ + union { + + /// bytewise access to SWR + uint8_t byte; + + /// bitwise access to register SWR + struct { + BITS SWI : 8; // bits 0-7 + }; // SWR bitfield + + /// register _CLK_SWR reset value + #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) + + } SWR; + + + /** Clock switch control register (SWCR at 0x50c5) */ + union { + + /// bytewise access to SWCR + uint8_t byte; + + /// bitwise access to register SWCR + struct { + BITS SWBSY : 1; // bit 0 + BITS SWEN : 1; // bit 1 + BITS SWIEN : 1; // bit 2 + BITS SWIF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SWCR bitfield + + /// register _CLK_SWCR reset value + #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) + + } SWCR; + + + /** Clock divider register (CKDIVR at 0x50c6) */ + union { + + /// bytewise access to CKDIVR + uint8_t byte; + + /// bitwise access to register CKDIVR + struct { + BITS CPUDIV : 3; // bits 0-2 + BITS HSIDIV : 2; // bits 3-4 + BITS : 3; // 3 bits + }; // CKDIVR bitfield + + /// register _CLK_CKDIVR reset value + #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) + + } CKDIVR; + + + /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ + union { + + /// bytewise access to PCKENR1 + uint8_t byte; + + /// bitwise access to register PCKENR1 + struct { + BITS PCKEN : 8; // bits 0-7 + }; // PCKENR1 bitfield + + /// register _CLK_PCKENR1 reset value + #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR1; + + + /** Clock security system register (CSSR at 0x50c8) */ + union { + + /// bytewise access to CSSR + uint8_t byte; + + /// bitwise access to register CSSR + struct { + BITS CSSEN : 1; // bit 0 + BITS AUX : 1; // bit 1 + BITS CSSDIE : 1; // bit 2 + BITS CSSD : 1; // bit 3 + BITS : 4; // 4 bits + }; // CSSR bitfield + + /// register _CLK_CSSR reset value + #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) + + } CSSR; + + + /** Configurable clock control register (CCOR at 0x50c9) */ + union { + + /// bytewise access to CCOR + uint8_t byte; + + /// bitwise access to register CCOR + struct { + BITS CCOEN : 1; // bit 0 + BITS CCOSEL : 4; // bits 1-4 + BITS CCORDY : 1; // bit 5 + BITS CC0BSY : 1; // bit 6 + BITS : 1; // 1 bit + }; // CCOR bitfield + + /// register _CLK_CCOR reset value + #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) + + } CCOR; + + + /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ + union { + + /// bytewise access to PCKENR2 + uint8_t byte; + + /// bitwise access to register PCKENR2 + struct { + BITS PCKEN2 : 8; // bits 0-7 + }; // PCKENR2 bitfield + + /// register _CLK_PCKENR2 reset value + #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR2; + + + /** CAN clock control register (CANCCR at 0x50cb) */ + union { + + /// bytewise access to CANCCR + uint8_t byte; + + /// bitwise access to register CANCCR + struct { + BITS CANDIV : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // CANCCR bitfield + + /// register _CLK_CANCCR reset value + #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) + + } CANCCR; + + + /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ + union { + + /// bytewise access to HSITRIMR + uint8_t byte; + + /// bitwise access to register HSITRIMR + struct { + BITS HSITRIM : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // HSITRIMR bitfield + + /// register _CLK_HSITRIMR reset value + #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) + + } HSITRIMR; + + + /** SWIM clock control register (SWIMCCR at 0x50cd) */ + union { + + /// bytewise access to SWIMCCR + uint8_t byte; + + /// bitwise access to register SWIMCCR + struct { + BITS SWIMCLK : 1; // bit 0 + BITS : 7; // 7 bits + }; // SWIMCCR bitfield + + /// register _CLK_SWIMCCR reset value + #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) + + } SWIMCCR; + +} CLK_t; + +/// access to CLK SFR registers +#define sfr_CLK (*((CLK_t*) 0x50c0)) + + +//------------------------ +// Module CPU +//------------------------ + +/** struct containing CPU module registers */ +typedef struct { + + /** Accumulator (A at 0x7f00) */ + union { + + /// bytewise access to A + uint8_t byte; + + /// skip bitwise access to register A + + /// register _CPU_A reset value + #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) + + } A; + + + /** Program counter extended (PCE at 0x7f01) */ + union { + + /// bytewise access to PCE + uint8_t byte; + + /// skip bitwise access to register PCE + + /// register _CPU_PCE reset value + #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) + + } PCE; + + + /** Program counter high (PCH at 0x7f02) */ + union { + + /// bytewise access to PCH + uint8_t byte; + + /// skip bitwise access to register PCH + + /// register _CPU_PCH reset value + #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) + + } PCH; + + + /** Program counter low (PCL at 0x7f03) */ + union { + + /// bytewise access to PCL + uint8_t byte; + + /// skip bitwise access to register PCL + + /// register _CPU_PCL reset value + #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) + + } PCL; + + + /** X index register high (XH at 0x7f04) */ + union { + + /// bytewise access to XH + uint8_t byte; + + /// skip bitwise access to register XH + + /// register _CPU_XH reset value + #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) + + } XH; + + + /** X index register low (XL at 0x7f05) */ + union { + + /// bytewise access to XL + uint8_t byte; + + /// skip bitwise access to register XL + + /// register _CPU_XL reset value + #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) + + } XL; + + + /** Y index register high (YH at 0x7f06) */ + union { + + /// bytewise access to YH + uint8_t byte; + + /// skip bitwise access to register YH + + /// register _CPU_YH reset value + #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) + + } YH; + + + /** Y index register low (YL at 0x7f07) */ + union { + + /// bytewise access to YL + uint8_t byte; + + /// skip bitwise access to register YL + + /// register _CPU_YL reset value + #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) + + } YL; + + + /** Stack pointer high (SPH at 0x7f08) */ + union { + + /// bytewise access to SPH + uint8_t byte; + + /// skip bitwise access to register SPH + + /// register _CPU_SPH reset value + #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x03) + + } SPH; + + + /** Stack pointer low (SPL at 0x7f09) */ + union { + + /// bytewise access to SPL + uint8_t byte; + + /// skip bitwise access to register SPL + + /// register _CPU_SPL reset value + #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) + + } SPL; + + + /** Condition code register (CCR at 0x7f0a) */ + union { + + /// bytewise access to CCR + uint8_t byte; + + /// bitwise access to register CCR + struct { + BITS C : 1; // bit 0 + BITS Z : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS I0 : 1; // bit 3 + BITS H : 1; // bit 4 + BITS I1 : 1; // bit 5 + BITS : 1; // 1 bit + BITS V : 1; // bit 7 + }; // CCR bitfield + + /// register _CPU_CCR reset value + #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) + + } CCR; + + + /// Reserved register (85B) + uint8_t Reserved_1[85]; + + + /** Global configuration register (CFG_GCR at 0x7f60) */ + union { + + /// bytewise access to CFG_GCR + uint8_t byte; + + /// bitwise access to register CFG_GCR + struct { + BITS SWO : 1; // bit 0 + BITS AL : 1; // bit 1 + BITS : 6; // 6 bits + }; // CFG_GCR bitfield + + /// register _CPU_CFG_GCR reset value + #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) + + } CFG_GCR; + +} CPU_t; + +/// access to CPU SFR registers +#define sfr_CPU (*((CPU_t*) 0x7f00)) + + +//------------------------ +// Module DM +//------------------------ + +/** struct containing DM module registers */ +typedef struct { + + /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ + union { + + /// bytewise access to BK1RE + uint8_t byte; + + /// skip bitwise access to register BK1RE + + /// register _DM_BK1RE reset value + #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RE; + + + /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ + union { + + /// bytewise access to BK1RH + uint8_t byte; + + /// skip bitwise access to register BK1RH + + /// register _DM_BK1RH reset value + #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RH; + + + /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ + union { + + /// bytewise access to BK1RL + uint8_t byte; + + /// skip bitwise access to register BK1RL + + /// register _DM_BK1RL reset value + #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RL; + + + /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ + union { + + /// bytewise access to BK2RE + uint8_t byte; + + /// skip bitwise access to register BK2RE + + /// register _DM_BK2RE reset value + #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RE; + + + /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ + union { + + /// bytewise access to BK2RH + uint8_t byte; + + /// skip bitwise access to register BK2RH + + /// register _DM_BK2RH reset value + #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RH; + + + /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ + union { + + /// bytewise access to BK2RL + uint8_t byte; + + /// skip bitwise access to register BK2RL + + /// register _DM_BK2RL reset value + #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RL; + + + /** DM debug module control register 1 (CR1 at 0x7f96) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// skip bitwise access to register CR1 + + /// register _DM_CR1 reset value + #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** DM debug module control register 2 (CR2 at 0x7f97) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// skip bitwise access to register CR2 + + /// register _DM_CR2 reset value + #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// skip bitwise access to register CSR1 + + /// register _DM_CSR1 reset value + #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) + + } CSR1; + + + /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// skip bitwise access to register CSR2 + + /// register _DM_CSR2 reset value + #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + + + /** DM enable function register (ENFCTR at 0x7f9a) */ + union { + + /// bytewise access to ENFCTR + uint8_t byte; + + /// skip bitwise access to register ENFCTR + + /// register _DM_ENFCTR reset value + #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) + + } ENFCTR; + +} DM_t; + +/// access to DM SFR registers +#define sfr_DM (*((DM_t*) 0x7f90)) + + +//------------------------ +// Module FLASH +//------------------------ + +/** struct containing FLASH module registers */ +typedef struct { + + /** Flash control register 1 (CR1 at 0x505a) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS FIX : 1; // bit 0 + BITS IE : 1; // bit 1 + BITS AHALT : 1; // bit 2 + BITS HALT : 1; // bit 3 + BITS : 4; // 4 bits + }; // CR1 bitfield + + /// register _FLASH_CR1 reset value + #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Flash control register 2 (CR2 at 0x505b) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS FPRG : 1; // bit 4 + BITS ERASE : 1; // bit 5 + BITS WPRG : 1; // bit 6 + BITS OPT : 1; // bit 7 + }; // CR2 bitfield + + /// register _FLASH_CR2 reset value + #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** Flash complementary control register 2 (NCR2 at 0x505c) */ + union { + + /// bytewise access to NCR2 + uint8_t byte; + + /// bitwise access to register NCR2 + struct { + BITS NPRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS NFPRG : 1; // bit 4 + BITS NERASE : 1; // bit 5 + BITS NWPRG : 1; // bit 6 + BITS NOPT : 1; // bit 7 + }; // NCR2 bitfield + + /// register _FLASH_NCR2 reset value + #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) + + } NCR2; + + + /** Flash protection register (FPR at 0x505d) */ + union { + + /// bytewise access to FPR + uint8_t byte; + + /// bitwise access to register FPR + struct { + BITS WPB0 : 1; // bit 0 + BITS WPB1 : 1; // bit 1 + BITS WPB2 : 1; // bit 2 + BITS WPB3 : 1; // bit 3 + BITS WPB4 : 1; // bit 4 + BITS WPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // FPR bitfield + + /// register _FLASH_FPR reset value + #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) + + } FPR; + + + /** Flash complementary protection register (NFPR at 0x505e) */ + union { + + /// bytewise access to NFPR + uint8_t byte; + + /// bitwise access to register NFPR + struct { + BITS NWPB0 : 1; // bit 0 + BITS NWPB1 : 1; // bit 1 + BITS NWPB2 : 1; // bit 2 + BITS NWPB3 : 1; // bit 3 + BITS NWPB4 : 1; // bit 4 + BITS NWPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // NFPR bitfield + + /// register _FLASH_NFPR reset value + #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) + + } NFPR; + + + /** Flash in-application programming status register (IAPSR at 0x505f) */ + union { + + /// bytewise access to IAPSR + uint8_t byte; + + /// bitwise access to register IAPSR + struct { + BITS WR_PG_DIS : 1; // bit 0 + BITS PUL : 1; // bit 1 + BITS EOP : 1; // bit 2 + BITS DUL : 1; // bit 3 + BITS : 2; // 2 bits + BITS HVOFF : 1; // bit 6 + BITS : 1; // 1 bit + }; // IAPSR bitfield + + /// register _FLASH_IAPSR reset value + #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) + + } IAPSR; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash program memory unprotection register (PUKR at 0x5062) */ + union { + + /// bytewise access to PUKR + uint8_t byte; + + /// bitwise access to register PUKR + struct { + BITS MASS_PRG : 8; // bits 0-7 + }; // PUKR bitfield + + /// register _FLASH_PUKR reset value + #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) + + } PUKR; + + + /// Reserved register (1B) + uint8_t Reserved_2[1]; + + + /** Data EEPROM unprotection register (DUKR at 0x5064) */ + union { + + /// bytewise access to DUKR + uint8_t byte; + + /// bitwise access to register DUKR + struct { + BITS MASS_DATA : 8; // bits 0-7 + }; // DUKR bitfield + + /// register _FLASH_DUKR reset value + #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) + + } DUKR; + +} FLASH_t; + +/// access to FLASH SFR registers +#define sfr_FLASH (*((FLASH_t*) 0x505a)) + + +//------------------------ +// Module I2C +//------------------------ + +/** struct containing I2C module registers */ +typedef struct { + + /** I2C control register 1 (CR1 at 0x5210) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PE : 1; // bit 0 + BITS : 5; // 5 bits + BITS ENGC : 1; // bit 6 + BITS NOSTRETCH : 1; // bit 7 + }; // CR1 bitfield + + /// register _I2C_CR1 reset value + #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** I2C control register 2 (CR2 at 0x5211) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS START : 1; // bit 0 + BITS STOP : 1; // bit 1 + BITS ACK : 1; // bit 2 + BITS POS : 1; // bit 3 + BITS : 3; // 3 bits + BITS SWRST : 1; // bit 7 + }; // CR2 bitfield + + /// register _I2C_CR2 reset value + #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** I2C frequency register (FREQR at 0x5212) */ + union { + + /// bytewise access to FREQR + uint8_t byte; + + /// bitwise access to register FREQR + struct { + BITS FREQ : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // FREQR bitfield + + /// register _I2C_FREQR reset value + #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) + + } FREQR; + + + /** I2C Own address register low (OARL at 0x5213) */ + union { + + /// bytewise access to OARL + uint8_t byte; + + /// bitwise access to register OARL + struct { + BITS ADD0 : 1; // bit 0 + BITS ADD : 7; // bits 1-7 + }; // OARL bitfield + + /// register _I2C_OARL reset value + #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) + + } OARL; + + + /** I2C Own address register high (OARH at 0x5214) */ + union { + + /// bytewise access to OARH + uint8_t byte; + + /// bitwise access to register OARH + struct { + BITS : 1; // 1 bit + BITS ADD : 2; // bits 1-2 + BITS : 3; // 3 bits + BITS ADDCONF : 1; // bit 6 + BITS ADDMODE : 1; // bit 7 + }; // OARH bitfield + + /// register _I2C_OARH reset value + #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) + + } OARH; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** I2C data register (DR at 0x5216) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _I2C_DR reset value + #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** I2C status register 1 (SR1 at 0x5217) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS SB : 1; // bit 0 + BITS ADDR : 1; // bit 1 + BITS BTF : 1; // bit 2 + BITS ADD10 : 1; // bit 3 + BITS STOPF : 1; // bit 4 + BITS : 1; // 1 bit + BITS RXNE : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR1 bitfield + + /// register _I2C_SR1 reset value + #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** I2C status register 2 (SR2 at 0x5218) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS BERR : 1; // bit 0 + BITS ARLO : 1; // bit 1 + BITS AF : 1; // bit 2 + BITS OVR : 1; // bit 3 + BITS : 1; // 1 bit + BITS WUFH : 1; // bit 5 + BITS : 2; // 2 bits + }; // SR2 bitfield + + /// register _I2C_SR2 reset value + #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** I2C status register 3 (SR3 at 0x5219) */ + union { + + /// bytewise access to SR3 + uint8_t byte; + + /// bitwise access to register SR3 + struct { + BITS MSL : 1; // bit 0 + BITS BUSY : 1; // bit 1 + BITS TRA : 1; // bit 2 + BITS : 1; // 1 bit + BITS GENCALL : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR3 bitfield + + /// register _I2C_SR3 reset value + #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) + + } SR3; + + + /** I2C interrupt control register (ITR at 0x521a) */ + union { + + /// bytewise access to ITR + uint8_t byte; + + /// bitwise access to register ITR + struct { + BITS ITERREN : 1; // bit 0 + BITS ITEVTEN : 1; // bit 1 + BITS ITBUFEN : 1; // bit 2 + BITS : 5; // 5 bits + }; // ITR bitfield + + /// register _I2C_ITR reset value + #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) + + } ITR; + + + /** I2C Clock control register low (CCRL at 0x521b) */ + union { + + /// bytewise access to CCRL + uint8_t byte; + + /// bitwise access to register CCRL + struct { + BITS CCR : 8; // bits 0-7 + }; // CCRL bitfield + + /// register _I2C_CCRL reset value + #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) + + } CCRL; + + + /** I2C Clock control register high (CCRH at 0x521c) */ + union { + + /// bytewise access to CCRH + uint8_t byte; + + /// bitwise access to register CCRH + struct { + BITS CCR : 4; // bits 0-3 + BITS : 2; // 2 bits + BITS DUTY : 1; // bit 6 + BITS F_S : 1; // bit 7 + }; // CCRH bitfield + + /// register _I2C_CCRH reset value + #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) + + } CCRH; + + + /** I2C TRISE register (TRISER at 0x521d) */ + union { + + /// bytewise access to TRISER + uint8_t byte; + + /// bitwise access to register TRISER + struct { + BITS TRISE : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // TRISER bitfield + + /// register _I2C_TRISER reset value + #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) + + } TRISER; + + + /** I2C packet error checking register (PECR at 0x521e) */ + union { + + /// bytewise access to PECR + uint8_t byte; + + /// bitwise access to register PECR + struct { + BITS PEC : 8; // bits 0-7 + }; // PECR bitfield + + /// register _I2C_PECR reset value + #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) + + } PECR; + +} I2C_t; + +/// access to I2C SFR registers +#define sfr_I2C (*((I2C_t*) 0x5210)) + + +//------------------------ +// Module ITC +//------------------------ + +/** struct containing ITC module registers */ +typedef struct { + + /** External interrupt control register 1 (CR1 at 0x50a0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PAIS : 2; // bits 0-1 + BITS PBIS : 2; // bits 2-3 + BITS PCIS : 2; // bits 4-5 + BITS PDIS : 2; // bits 6-7 + }; // CR1 bitfield + + /// register _ITC_CR1 reset value + #define sfr_ITC_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** External interrupt control register 2 (CR2 at 0x50a1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PEIS : 2; // bits 0-1 + BITS TLIS : 1; // bit 2 + BITS : 5; // 5 bits + }; // CR2 bitfield + + /// register _ITC_CR2 reset value + #define sfr_ITC_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /// Reserved register (17B) + uint8_t Reserved_1[17]; + + + /** Reset status register (RST_SR at 0x50b3) */ + union { + + /// bytewise access to RST_SR + uint8_t byte; + + /// bitwise access to register RST_SR + struct { + BITS WWDGF : 1; // bit 0 + BITS IWDGF : 1; // bit 1 + BITS ILLOPF : 1; // bit 2 + BITS SWIMF : 1; // bit 3 + BITS EMCF : 1; // bit 4 + BITS : 3; // 3 bits + }; // RST_SR bitfield + + /// register _ITC_RST_SR reset value + #define sfr_ITC_RST_SR_RESET_VALUE ((uint8_t) 0x00) + + } RST_SR; + + + /// Reserved register (11964B) + uint8_t Reserved_2[11964]; + + + /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ + union { + + /// bytewise access to SPR1 + uint8_t byte; + + /// bitwise access to register SPR1 + struct { + BITS VECT0SPR : 2; // bits 0-1 + BITS VECT1SPR : 2; // bits 2-3 + BITS VECT2SPR : 2; // bits 4-5 + BITS VECT3SPR : 2; // bits 6-7 + }; // SPR1 bitfield + + /// register _ITC_SPR1 reset value + #define sfr_ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF) + + } SPR1; + + + /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ + union { + + /// bytewise access to SPR2 + uint8_t byte; + + /// bitwise access to register SPR2 + struct { + BITS VECT4SPR : 2; // bits 0-1 + BITS VECT5SPR : 2; // bits 2-3 + BITS VECT6SPR : 2; // bits 4-5 + BITS VECT7SPR : 2; // bits 6-7 + }; // SPR2 bitfield + + /// register _ITC_SPR2 reset value + #define sfr_ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF) + + } SPR2; + + + /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ + union { + + /// bytewise access to SPR3 + uint8_t byte; + + /// bitwise access to register SPR3 + struct { + BITS VECT8SPR : 2; // bits 0-1 + BITS VECT9SPR : 2; // bits 2-3 + BITS VECT10SPR : 2; // bits 4-5 + BITS VECT11SPR : 2; // bits 6-7 + }; // SPR3 bitfield + + /// register _ITC_SPR3 reset value + #define sfr_ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF) + + } SPR3; + + + /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ + union { + + /// bytewise access to SPR4 + uint8_t byte; + + /// bitwise access to register SPR4 + struct { + BITS VECT12SPR : 2; // bits 0-1 + BITS VECT13SPR : 2; // bits 2-3 + BITS VECT14SPR : 2; // bits 4-5 + BITS VECT15SPR : 2; // bits 6-7 + }; // SPR4 bitfield + + /// register _ITC_SPR4 reset value + #define sfr_ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF) + + } SPR4; + + + /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ + union { + + /// bytewise access to SPR5 + uint8_t byte; + + /// bitwise access to register SPR5 + struct { + BITS VECT16SPR : 2; // bits 0-1 + BITS VECT17SPR : 2; // bits 2-3 + BITS VECT18SPR : 2; // bits 4-5 + BITS VECT19SPR : 2; // bits 6-7 + }; // SPR5 bitfield + + /// register _ITC_SPR5 reset value + #define sfr_ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF) + + } SPR5; + + + /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ + union { + + /// bytewise access to SPR6 + uint8_t byte; + + /// bitwise access to register SPR6 + struct { + BITS VECT20SPR : 2; // bits 0-1 + BITS VECT21SPR : 2; // bits 2-3 + BITS VECT22SPR : 2; // bits 4-5 + BITS VECT23SPR : 2; // bits 6-7 + }; // SPR6 bitfield + + /// register _ITC_SPR6 reset value + #define sfr_ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF) + + } SPR6; + + + /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ + union { + + /// bytewise access to SPR7 + uint8_t byte; + + /// bitwise access to register SPR7 + struct { + BITS VECT24SPR : 2; // bits 0-1 + BITS VECT25SPR : 2; // bits 2-3 + BITS VECT26SPR : 2; // bits 4-5 + BITS VECT27SPR : 2; // bits 6-7 + }; // SPR7 bitfield + + /// register _ITC_SPR7 reset value + #define sfr_ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF) + + } SPR7; + + + /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ + union { + + /// bytewise access to SPR8 + uint8_t byte; + + /// bitwise access to register SPR8 + struct { + BITS VECT28SPR : 2; // bits 0-1 + BITS VECT29SPR : 2; // bits 2-3 + BITS : 4; // 4 bits + }; // SPR8 bitfield + + /// register _ITC_SPR8 reset value + #define sfr_ITC_SPR8_RESET_VALUE ((uint8_t) 0xFF) + + } SPR8; + +} ITC_t; + +/// access to ITC SFR registers +#define sfr_ITC (*((ITC_t*) 0x50a0)) + + +//------------------------ +// Module IWDG +//------------------------ + +/** struct containing IWDG module registers */ +typedef struct { + + /** IWDG key register (KR at 0x50e0) */ + union { + + /// bytewise access to KR + uint8_t byte; + + /// bitwise access to register KR + struct { + BITS KEY : 8; // bits 0-7 + }; // KR bitfield + + /// register _IWDG_KR reset value + #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) + + } KR; + + + /** IWDG prescaler register (PR at 0x50e1) */ + union { + + /// bytewise access to PR + uint8_t byte; + + /// bitwise access to register PR + struct { + BITS PR : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PR bitfield + + /// register _IWDG_PR reset value + #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) + + } PR; + + + /** IWDG reload register (RLR at 0x50e2) */ + union { + + /// bytewise access to RLR + uint8_t byte; + + /// bitwise access to register RLR + struct { + BITS RL : 8; // bits 0-7 + }; // RLR bitfield + + /// register _IWDG_RLR reset value + #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) + + } RLR; + +} IWDG_t; + +/// access to IWDG SFR registers +#define sfr_IWDG (*((IWDG_t*) 0x50e0)) + + +//------------------------ +// Module OPT +//------------------------ + +/** struct containing OPT module registers */ +typedef struct { + + /** Read-out protection (ROP) (OPT0 at 0x4800) */ + union { + + /// bytewise access to OPT0 + uint8_t byte; + + /// skip bitwise access to register OPT0 + + /// register _OPT_OPT0 reset value + #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) + + } OPT0; + + + /** User boot code (UBC) (OPT1 at 0x4801) */ + union { + + /// bytewise access to OPT1 + uint8_t byte; + + /// skip bitwise access to register OPT1 + + /// register _OPT_OPT1 reset value + #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) + + } OPT1; + + + /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ + union { + + /// bytewise access to NOPT1 + uint8_t byte; + + /// skip bitwise access to register NOPT1 + + /// register _OPT_NOPT1 reset value + #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT1; + + + /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ + union { + + /// bytewise access to OPT2 + uint8_t byte; + + /// skip bitwise access to register OPT2 + + /// register _OPT_OPT2 reset value + #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) + + } OPT2; + + + /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ + union { + + /// bytewise access to NOPT2 + uint8_t byte; + + /// skip bitwise access to register NOPT2 + + /// register _OPT_NOPT2 reset value + #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT2; + + + /** Misc. option (OPT3 at 0x4805) */ + union { + + /// bytewise access to OPT3 + uint8_t byte; + + /// skip bitwise access to register OPT3 + + /// register _OPT_OPT3 reset value + #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) + + } OPT3; + + + /** Misc. option (complementary byte) (NOPT3 at 0x4806) */ + union { + + /// bytewise access to NOPT3 + uint8_t byte; + + /// skip bitwise access to register NOPT3 + + /// register _OPT_NOPT3 reset value + #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT3; + + + /** Clock option (OPT4 at 0x4807) */ + union { + + /// bytewise access to OPT4 + uint8_t byte; + + /// skip bitwise access to register OPT4 + + /// register _OPT_OPT4 reset value + #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) + + } OPT4; + + + /** Clock option (complementary byte) (NOPT4 at 0x4808) */ + union { + + /// bytewise access to NOPT4 + uint8_t byte; + + /// skip bitwise access to register NOPT4 + + /// register _OPT_NOPT4 reset value + #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT4; + + + /** HSE clock startup (OPT5 at 0x4809) */ + union { + + /// bytewise access to OPT5 + uint8_t byte; + + /// skip bitwise access to register OPT5 + + /// register _OPT_OPT5 reset value + #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) + + } OPT5; + + + /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ + union { + + /// bytewise access to NOPT5 + uint8_t byte; + + /// skip bitwise access to register NOPT5 + + /// register _OPT_NOPT5 reset value + #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT5; + +} OPT_t; + +/// access to OPT SFR registers +#define sfr_OPT (*((OPT_t*) 0x4800)) + + +//------------------------ +// Module PORT +//------------------------ + +/** struct containing PORTA module registers */ +typedef struct { + + /** Port A data output latch register (ODR at 0x5000) */ + union { + + /// bytewise access to ODR + uint8_t byte; + + /// bitwise access to register ODR + struct { + BITS ODR0 : 1; // bit 0 + BITS ODR1 : 1; // bit 1 + BITS ODR2 : 1; // bit 2 + BITS ODR3 : 1; // bit 3 + BITS ODR4 : 1; // bit 4 + BITS ODR5 : 1; // bit 5 + BITS ODR6 : 1; // bit 6 + BITS ODR7 : 1; // bit 7 + }; // ODR bitfield + + /// register _PORT_ODR reset value + #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) + + } ODR; + + + /** Port A input pin value register (IDR at 0x5001) */ + union { + + /// bytewise access to IDR + uint8_t byte; + + /// bitwise access to register IDR + struct { + BITS IDR0 : 1; // bit 0 + BITS IDR1 : 1; // bit 1 + BITS IDR2 : 1; // bit 2 + BITS IDR3 : 1; // bit 3 + BITS IDR4 : 1; // bit 4 + BITS IDR5 : 1; // bit 5 + BITS IDR6 : 1; // bit 6 + BITS IDR7 : 1; // bit 7 + }; // IDR bitfield + + /// register _PORT_IDR reset value + #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) + + } IDR; + + + /** Port A data direction register (DDR at 0x5002) */ + union { + + /// bytewise access to DDR + uint8_t byte; + + /// bitwise access to register DDR + struct { + BITS DDR0 : 1; // bit 0 + BITS DDR1 : 1; // bit 1 + BITS DDR2 : 1; // bit 2 + BITS DDR3 : 1; // bit 3 + BITS DDR4 : 1; // bit 4 + BITS DDR5 : 1; // bit 5 + BITS DDR6 : 1; // bit 6 + BITS DDR7 : 1; // bit 7 + }; // DDR bitfield + + /// register _PORT_DDR reset value + #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) + + } DDR; + + + /** Port A control register 1 (CR1 at 0x5003) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS C10 : 1; // bit 0 + BITS C11 : 1; // bit 1 + BITS C12 : 1; // bit 2 + BITS C13 : 1; // bit 3 + BITS C14 : 1; // bit 4 + BITS C15 : 1; // bit 5 + BITS C16 : 1; // bit 6 + BITS C17 : 1; // bit 7 + }; // CR1 bitfield + + /// register _PORT_CR1 reset value + #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Port A control register 2 (CR2 at 0x5004) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS C20 : 1; // bit 0 + BITS C21 : 1; // bit 1 + BITS C22 : 1; // bit 2 + BITS C23 : 1; // bit 3 + BITS C24 : 1; // bit 4 + BITS C25 : 1; // bit 5 + BITS C26 : 1; // bit 6 + BITS C27 : 1; // bit 7 + }; // CR2 bitfield + + /// register _PORT_CR2 reset value + #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} PORT_t; + +/// access to PORTA SFR registers +#define sfr_PORTA (*((PORT_t*) 0x5000)) + + +/// access to PORTB SFR registers +#define sfr_PORTB (*((PORT_t*) 0x5005)) + + +/// access to PORTC SFR registers +#define sfr_PORTC (*((PORT_t*) 0x500a)) + + +/// access to PORTD SFR registers +#define sfr_PORTD (*((PORT_t*) 0x500f)) + + +/// access to PORTE SFR registers +#define sfr_PORTE (*((PORT_t*) 0x5014)) + + +/// access to PORTF SFR registers +#define sfr_PORTF (*((PORT_t*) 0x5019)) + + +//------------------------ +// Module SPI +//------------------------ + +/** struct containing SPI module registers */ +typedef struct { + + /** SPI control register 1 (CR1 at 0x5200) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CPHA : 1; // bit 0 + BITS CPOL : 1; // bit 1 + BITS MSTR : 1; // bit 2 + BITS BR : 3; // bits 3-5 + BITS SPE : 1; // bit 6 + BITS LSBFIRST : 1; // bit 7 + }; // CR1 bitfield + + /// register _SPI_CR1 reset value + #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** SPI control register 2 (CR2 at 0x5201) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SSI : 1; // bit 0 + BITS SSM : 1; // bit 1 + BITS RXONLY : 1; // bit 2 + BITS : 1; // 1 bit + BITS CRCNEXT : 1; // bit 4 + BITS CECEN : 1; // bit 5 + BITS BDOE : 1; // bit 6 + BITS BDM : 1; // bit 7 + }; // CR2 bitfield + + /// register _SPI_CR2 reset value + #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** SPI interrupt control register (ICR at 0x5202) */ + union { + + /// bytewise access to ICR + uint8_t byte; + + /// bitwise access to register ICR + struct { + BITS : 4; // 4 bits + BITS WKIE : 1; // bit 4 + BITS ERRIE : 1; // bit 5 + BITS RXIE : 1; // bit 6 + BITS TXIE : 1; // bit 7 + }; // ICR bitfield + + /// register _SPI_ICR reset value + #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) + + } ICR; + + + /** SPI status register (SR at 0x5203) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS RXNE : 1; // bit 0 + BITS TXE : 1; // bit 1 + BITS : 1; // 1 bit + BITS WKUP : 1; // bit 3 + BITS CRCERR : 1; // bit 4 + BITS MODF : 1; // bit 5 + BITS OVR : 1; // bit 6 + BITS BSY : 1; // bit 7 + }; // SR bitfield + + /// register _SPI_SR reset value + #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) + + } SR; + + + /** SPI data register (DR at 0x5204) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _SPI_DR reset value + #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** SPI CRC polynomial register (CRCPR at 0x5205) */ + union { + + /// bytewise access to CRCPR + uint8_t byte; + + /// bitwise access to register CRCPR + struct { + BITS CRCPOLY : 8; // bits 0-7 + }; // CRCPR bitfield + + /// register _SPI_CRCPR reset value + #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) + + } CRCPR; + + + /** SPI Rx CRC register (RXCRCR at 0x5206) */ + union { + + /// bytewise access to RXCRCR + uint8_t byte; + + /// bitwise access to register RXCRCR + struct { + BITS RXCRC : 8; // bits 0-7 + }; // RXCRCR bitfield + + /// register _SPI_RXCRCR reset value + #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } RXCRCR; + + + /** SPI Tx CRC register (TXCRCR at 0x5207) */ + union { + + /// bytewise access to TXCRCR + uint8_t byte; + + /// bitwise access to register TXCRCR + struct { + BITS TXCRC : 8; // bits 0-7 + }; // TXCRCR bitfield + + /// register _SPI_TXCRCR reset value + #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } TXCRCR; + +} SPI_t; + +/// access to SPI SFR registers +#define sfr_SPI (*((SPI_t*) 0x5200)) + + +//------------------------ +// Module SWIM +//------------------------ + +/** struct containing SWIM module registers */ +typedef struct { + + /** SWIM control status register (CSR at 0x7f80) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// skip bitwise access to register CSR + + /// register _SWIM_CSR reset value + #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + +} SWIM_t; + +/// access to SWIM SFR registers +#define sfr_SWIM (*((SWIM_t*) 0x7f80)) + + +//------------------------ +// Module TIM1 +//------------------------ + +/** struct containing TIM1 module registers */ +typedef struct { + + /** TIM1 control register 1 (CR1 at 0x5250) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM1_CR1 reset value + #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM1 control register 2 (CR2 at 0x5251) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS CCPG : 1; // bit 0 + BITS : 1; // 1 bit + BITS COMS : 1; // bit 2 + BITS : 1; // 1 bit + BITS MMS : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _TIM1_CR2 reset value + #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM1 slave mode control register (SMCR at 0x5252) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM1_SMCR reset value + #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM1 external trigger register (ETR at 0x5253) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM1_ETR reset value + #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM1 interrupt enable register (IER at 0x5254) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS CC4IE : 1; // bit 4 + BITS COMIE : 1; // bit 5 + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM1_IER reset value + #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM1 status register 1 (SR1 at 0x5255) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS CC4IF : 1; // bit 4 + BITS COMIF : 1; // bit 5 + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM1_SR1 reset value + #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM1 status register 2 (SR2 at 0x5256) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS CC4OF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR2 bitfield + + /// register _TIM1_SR2 reset value + #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM1 event generation register (EGR at 0x5257) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS CC4G : 1; // bit 4 + BITS COMG : 1; // bit 5 + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM1_EGR reset value + #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS OC1CE : 1; // bit 7 + }; // CCMR1 bitfield + + /// register _TIM1_CCMR1 reset value + #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS OC2CE : 1; // bit 7 + }; // CCMR2 bitfield + + /// register _TIM1_CCMR2 reset value + #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS OC3FE : 1; // bit 2 + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS OC3CE : 1; // bit 7 + }; // CCMR3 bitfield + + /// register _TIM1_CCMR3 reset value + #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ + union { + + /// bytewise access to CCMR4 + uint8_t byte; + + /// bitwise access to register CCMR4 + struct { + BITS CC4S : 2; // bits 0-1 + BITS OC4FE : 1; // bit 2 + BITS OC4PE : 1; // bit 3 + BITS OC4M : 3; // bits 4-6 + BITS OC4CE : 1; // bit 7 + }; // CCMR4 bitfield + + /// register _TIM1_CCMR4 reset value + #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) + + } CCMR4; + + + /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS CC1NE : 1; // bit 2 + BITS CC1NP : 1; // bit 3 + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS CC2NE : 1; // bit 6 + BITS CC2NP : 1; // bit 7 + }; // CCER1 bitfield + + /// register _TIM1_CCER1 reset value + #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS CC3NE : 1; // bit 2 + BITS CC3NP : 1; // bit 3 + BITS CC4E : 1; // bit 4 + BITS CC4P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER2 bitfield + + /// register _TIM1_CCER2 reset value + #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM1 counter high (CNTRH at 0x525e) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM1_CNTRH reset value + #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM1 counter low (CNTRL at 0x525f) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM1_CNTRL reset value + #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM1 prescaler register high (PSCRH at 0x5260) */ + union { + + /// bytewise access to PSCRH + uint8_t byte; + + /// bitwise access to register PSCRH + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRH bitfield + + /// register _TIM1_PSCRH reset value + #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) + + } PSCRH; + + + /** TIM1 prescaler register low (PSCRL at 0x5261) */ + union { + + /// bytewise access to PSCRL + uint8_t byte; + + /// bitwise access to register PSCRL + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRL bitfield + + /// register _TIM1_PSCRL reset value + #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) + + } PSCRL; + + + /** TIM1 auto-reload register high (ARRH at 0x5262) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM1_ARRH reset value + #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM1 auto-reload register low (ARRL at 0x5263) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM1_ARRL reset value + #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM1 repetition counter register (RCR at 0x5264) */ + union { + + /// bytewise access to RCR + uint8_t byte; + + /// bitwise access to register RCR + struct { + BITS REP : 8; // bits 0-7 + }; // RCR bitfield + + /// register _TIM1_RCR reset value + #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) + + } RCR; + + + /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM1_CCR1H reset value + #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM1_CCR1L reset value + #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM1_CCR2H reset value + #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM1_CCR2L reset value + #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM1_CCR3H reset value + #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM1_CCR3L reset value + #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + + + /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ + union { + + /// bytewise access to CCR4H + uint8_t byte; + + /// bitwise access to register CCR4H + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4H bitfield + + /// register _TIM1_CCR4H reset value + #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) + + } CCR4H; + + + /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ + union { + + /// bytewise access to CCR4L + uint8_t byte; + + /// bitwise access to register CCR4L + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4L bitfield + + /// register _TIM1_CCR4L reset value + #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) + + } CCR4L; + + + /** TIM1 break register (BKR at 0x526d) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS OSSR : 1; // bit 3 + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM1_BKR reset value + #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM1 dead-time register (DTR at 0x526e) */ + union { + + /// bytewise access to DTR + uint8_t byte; + + /// bitwise access to register DTR + struct { + BITS DTG : 8; // bits 0-7 + }; // DTR bitfield + + /// register _TIM1_DTR reset value + #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) + + } DTR; + + + /** TIM1 output idle state register (OISR at 0x526f) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS OIS1N : 1; // bit 1 + BITS OIS2 : 1; // bit 2 + BITS OIS2N : 1; // bit 3 + BITS OIS3 : 1; // bit 4 + BITS OIS3N : 1; // bit 5 + BITS OIS4 : 1; // bit 6 + BITS : 1; // 1 bit + }; // OISR bitfield + + /// register _TIM1_OISR reset value + #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + +} TIM1_t; + +/// access to TIM1 SFR registers +#define sfr_TIM1 (*((TIM1_t*) 0x5250)) + + +//------------------------ +// Module TIM2 +//------------------------ + +/** struct containing TIM2 module registers */ +typedef struct { + + /** TIM2 control register 1 (CR1 at 0x5300) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM2_CR1 reset value + #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** TIM2 Interrupt enable register (IER at 0x5303) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM2_IER reset value + #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM2 status register 1 (SR1 at 0x5304) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM2_SR1 reset value + #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM2 status register 2 (SR2 at 0x5305) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM2_SR2 reset value + #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM2 event generation register (EGR at 0x5306) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM2_EGR reset value + #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5307) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM2_CCMR1 reset value + #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5308) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM2_CCMR2 reset value + #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5309) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR3 bitfield + + /// register _TIM2_CCMR3 reset value + #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM2 capture/compare enable register 1 (CCER1 at 0x530a) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM2_CCER1 reset value + #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM2 capture/compare enable register 2 (CCER2 at 0x530b) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS : 6; // 6 bits + }; // CCER2 bitfield + + /// register _TIM2_CCER2 reset value + #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM2 counter high (CNTRH at 0x530c) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM2_CNTRH reset value + #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM2 counter low (CNTRL at 0x530d) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM2_CNTRL reset value + #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM2 prescaler register (PSCR at 0x530e) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM2_PSCR reset value + #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM2 auto-reload register high (ARRH at 0x530f) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM2_ARRH reset value + #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM2 auto-reload register low (ARRL at 0x5310) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM2_ARRL reset value + #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM2 capture/compare register 1 high (CCR1H at 0x5311) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM2_CCR1H reset value + #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM2 capture/compare register 1 low (CCR1L at 0x5312) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM2_CCR1L reset value + #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM2 capture/compare reg (CCR2H at 0x5313) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM2_CCR2H reset value + #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM2 capture/compare register 2 low (CCR2L at 0x5314) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM2_CCR2L reset value + #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM2 capture/compare register 3 high (CCR3H at 0x5315) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM2_CCR3H reset value + #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM2 capture/compare register 3 low (CCR3L at 0x5316) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM2_CCR3L reset value + #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + +} TIM2_t; + +/// access to TIM2 SFR registers +#define sfr_TIM2 (*((TIM2_t*) 0x5300)) + + +//------------------------ +// Module TIM4 +//------------------------ + +/** struct containing TIM4 module registers */ +typedef struct { + + /** TIM4 control register 1 (CR1 at 0x5340) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM4_CR1 reset value + #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** TIM4 interrupt enable register (IER at 0x5343) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM4_IER reset value + #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM4 status register (SR at 0x5344) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS UIF : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR bitfield + + /// register _TIM4_SR reset value + #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + + + /** TIM4 event generation register (EGR at 0x5345) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS : 5; // 5 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM4_EGR reset value + #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM4 counter (CNTR at 0x5346) */ + union { + + /// bytewise access to CNTR + uint8_t byte; + + /// bitwise access to register CNTR + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTR bitfield + + /// register _TIM4_CNTR reset value + #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) + + } CNTR; + + + /** TIM4 prescaler register (PSCR at 0x5347) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSCR bitfield + + /// register _TIM4_PSCR reset value + #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM4 auto-reload register (ARR at 0x5348) */ + union { + + /// bytewise access to ARR + uint8_t byte; + + /// bitwise access to register ARR + struct { + BITS ARR : 8; // bits 0-7 + }; // ARR bitfield + + /// register _TIM4_ARR reset value + #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) + + } ARR; + +} TIM4_t; + +/// access to TIM4 SFR registers +#define sfr_TIM4 (*((TIM4_t*) 0x5340)) + + +//------------------------ +// Module UART1 +//------------------------ + +/** struct containing UART1 module registers */ +typedef struct { + + /** UART1 status register (SR at 0x5230) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR_LHE : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART1_SR reset value + #define sfr_UART1_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART1 data register (DR at 0x5231) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART1_DR reset value + #define sfr_UART1_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART1 baud rate register 1 (BRR1 at 0x5232) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART1_BRR1 reset value + #define sfr_UART1_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART1 baud rate register 2 (BRR2 at 0x5233) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART1_BRR2 reset value + #define sfr_UART1_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART1 control register 1 (CR1 at 0x5234) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UART0 : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART1_CR1 reset value + #define sfr_UART1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART1 control register 2 (CR2 at 0x5235) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART1_CR2 reset value + #define sfr_UART1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART1 control register 3 (CR3 at 0x5236) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS LBCL : 1; // bit 0 + BITS CPHA : 1; // bit 1 + BITS CPOL : 1; // bit 2 + BITS CKEN : 1; // bit 3 + BITS STOP : 2; // bits 4-5 + BITS : 1; // 1 bit + BITS LINEN : 1; // bit 7 + }; // CR3 bitfield + + /// register _UART1_CR3 reset value + #define sfr_UART1_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART1 control register 4 (CR4 at 0x5237) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART1_CR4 reset value + #define sfr_UART1_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /** UART1 control register 5 (CR5 at 0x5238) */ + union { + + /// bytewise access to CR5 + uint8_t byte; + + /// bitwise access to register CR5 + struct { + BITS : 1; // 1 bit + BITS IREN : 1; // bit 1 + BITS IRLP : 1; // bit 2 + BITS HDSEL : 1; // bit 3 + BITS NACK : 1; // bit 4 + BITS SCEN : 1; // bit 5 + BITS : 2; // 2 bits + }; // CR5 bitfield + + /// register _UART1_CR5 reset value + #define sfr_UART1_CR5_RESET_VALUE ((uint8_t) 0x00) + + } CR5; + + + /** UART1 guard time register (GTR at 0x5239) */ + union { + + /// bytewise access to GTR + uint8_t byte; + + /// bitwise access to register GTR + struct { + BITS GT : 8; // bits 0-7 + }; // GTR bitfield + + /// register _UART1_GTR reset value + #define sfr_UART1_GTR_RESET_VALUE ((uint8_t) 0x00) + + } GTR; + + + /** UART1 prescaler register (PSCR at 0x523a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCR bitfield + + /// register _UART1_PSCR reset value + #define sfr_UART1_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + +} UART1_t; + +/// access to UART1 SFR registers +#define sfr_UART1 (*((UART1_t*) 0x5230)) + + +//------------------------ +// Module WWDG +//------------------------ + +/** struct containing WWDG module registers */ +typedef struct { + + /** WWDG control register (CR at 0x50d1) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS T0 : 1; // bit 0 + BITS T1 : 1; // bit 1 + BITS T2 : 1; // bit 2 + BITS T3 : 1; // bit 3 + BITS T4 : 1; // bit 4 + BITS T5 : 1; // bit 5 + BITS T6 : 1; // bit 6 + BITS WDGA : 1; // bit 7 + }; // CR bitfield + + /// register _WWDG_CR reset value + #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) + + } CR; + + + /** WWDR window register (WR at 0x50d2) */ + union { + + /// bytewise access to WR + uint8_t byte; + + /// bitwise access to register WR + struct { + BITS W0 : 1; // bit 0 + BITS W1 : 1; // bit 1 + BITS W2 : 1; // bit 2 + BITS W3 : 1; // bit 3 + BITS W4 : 1; // bit 4 + BITS W5 : 1; // bit 5 + BITS W6 : 1; // bit 6 + BITS : 1; // 1 bit + }; // WR bitfield + + /// register _WWDG_WR reset value + #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) + + } WR; + +} WWDG_t; + +/// access to WWDG SFR registers +#define sfr_WWDG (*((WWDG_t*) 0x50d1)) + + +// undefine local macros +#undef BITS + +// required for C++ +#ifdef __cplusplus + } // extern "C" +#endif + +/*------------------------------------------------------------------------- + END OF MODULE DEFINITION FOR MULTIPLE INLUSION +-------------------------------------------------------------------------*/ +#endif // STM8S103F3_H diff --git a/examples/native-blink/src/STM8S207K8.h b/examples/native-blink/src/STM8S207K8.h new file mode 100644 index 0000000..574a48a --- /dev/null +++ b/examples/native-blink/src/STM8S207K8.h @@ -0,0 +1,4648 @@ +/*------------------------------------------------------------------------- + + STM8S207K8.h - Device Declarations + + STM8S/STM8AF, high density with ROM bootloader + + Copyright (C) 2020, Georg Icking-Konert + + Mainstream Performance line 8-bit MCU with 64 Kbytes Flash, 24 MHz CPU, integrated EEPROM + + datasheet: https://www.st.com/resource/en/datasheet/stm8s207k8.pdf + reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf + + MIT License + + Copyright (c) 2020 Georg Icking-Konert + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. + +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- + MODULE DEFINITION FOR MULTIPLE INCLUSION +-------------------------------------------------------------------------*/ +#ifndef STM8S207K8_H +#define STM8S207K8_H + +// DEVICE NAME +#define DEVICE_STM8S207K8 + +// DEVICE FAMILY +#define FAMILY_STM8S + +// required for C++ +#ifdef __cplusplus + extern "C" { +#endif + + +/*------------------------------------------------------------------------- + INCLUDE FILES +-------------------------------------------------------------------------*/ +#include + + +/*------------------------------------------------------------------------- + COMPILER SPECIFIC SETTINGS +-------------------------------------------------------------------------*/ + +// Cosmic compiler +#if defined(__CSMC__) + + // macros to unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine + #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine + + // definition of inline functions + #define INLINE @inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling + #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode + #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + + +// IAR Compiler +#elif defined(__ICCSTM8__) + + // include intrinsic functions + #include + + // macros to unify ISR declaration and implementation + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define ISR_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define ISR_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling + #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt + #define ENTER_HALT() __halt() ///< put controller to HALT mode + #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) + + +// SDCC compiler +#elif defined(__SDCC) + + // store SDCC version in preprocessor friendly way + #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ + + __SDCC_VERSION_MINOR * 100 \ + + __SDCC_VERSION_PATCH) + + // unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine + #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 + #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine + #else + #error traps require SDCC >=3.4.3. Please update! + #endif + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling + #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode + #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + +// unsupported compiler -> stop +#else + #error: compiler not supported +#endif + + +/*------------------------------------------------------------------------- + FOR CONVENIENT PIN ACCESS +-------------------------------------------------------------------------*/ + +#define PIN0 0x01 +#define PIN1 0x02 +#define PIN2 0x04 +#define PIN3 0x08 +#define PIN4 0x10 +#define PIN5 0x20 +#define PIN6 0x40 +#define PIN7 0x80 + + +/*------------------------------------------------------------------------- + DEVICE MEMORY (size in bytes) +-------------------------------------------------------------------------*/ + +// RAM +#define RAM_ADDR_START 0x000000 +#define RAM_ADDR_END 0x0017FF +#define RAM_SIZE 6144 + + +// FLASH +#define FLASH_ADDR_START 0x008000 +#define FLASH_ADDR_END 0x017FFF +#define FLASH_SIZE 65536 + + +// SFR1 +#define SFR1_ADDR_START 0x005000 +#define SFR1_ADDR_END 0x0057FF +#define SFR1_SIZE 2048 + + +// SFR2 +#define SFR2_ADDR_START 0x007F00 +#define SFR2_ADDR_END 0x007FFF +#define SFR2_SIZE 256 + + +// BOOTROM +#define BOOTROM_ADDR_START 0x006000 +#define BOOTROM_ADDR_END 0x0067FF +#define BOOTROM_SIZE 2048 + + +// EEPROM +#define EEPROM_ADDR_START 0x004000 +#define EEPROM_ADDR_END 0x0043FF +#define EEPROM_SIZE 1024 + + +// OPTION +#define OPTION_ADDR_START 0x004800 +#define OPTION_ADDR_END 0x00487F +#define OPTION_SIZE 128 + + +// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) +#define FLASH_ADDR_WIDTH 32 ///< width of address space +#define FLASH_POINTER_T uint32_t ///< address variable type + + +/*------------------------------------------------------------------------- + UNIQUE IDENTIFIER (size in bytes) +-------------------------------------------------------------------------*/ + +#define UID_ADDR_START 0x48CD ///< start address of unique identifier +#define UID_SIZE 12 ///< size of unique identifier [B] +#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N + + +/*------------------------------------------------------------------------- + MISC OPTIONS +-------------------------------------------------------------------------*/ + +/// LSI frequency measurement channel +#define LSI_MEASURE_TIM3_IC1 + + +/*------------------------------------------------------------------------- + ISR Vector Table (SDCC, IAR) + Notes: + - IAR has an IRQ offset of +2 compared to datasheet and below numbers + - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' + - different interrupt sources may share the same IRQ +-------------------------------------------------------------------------*/ + +// interrupt IRQ +#define _TLI_VECTOR_ 0 +#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR +#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR +#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR +#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR +#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR +#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR +#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR +#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR +#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR +#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR +#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR +#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR +#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR +#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR +#define _TIM1_CAPCOM_BIF_VECTOR_ 11 ///< TIM1_CAPCOM_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_TIF_VECTOR_ 11 ///< TIM1_CAPCOM_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR +#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR +#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR +#define _TIM3_OVR_UIF_VECTOR_ 15 ///< TIM3_OVR_UIF interrupt vector: enable: TIM3_IER.UIE, pending: TIM3_SR1.UIF, priority: ITC_SPR4.VECT15SPR +#define _TIM3_CAPCOM_CC1IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC1IF interrupt vector: enable: TIM3_IER.CC1IE, pending: TIM3_SR1.CC1IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC2IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC2IF interrupt vector: enable: TIM3_IER.CC2IE, pending: TIM3_SR1.CC2IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC3IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC3IF interrupt vector: enable: TIM3_IER.CC3IE, pending: TIM3_SR1.CC3IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_TIF_VECTOR_ 16 ///< TIM3_CAPCOM_TIF interrupt vector: enable: TIM3_IER.TIE, pending: TIM3_SR1.TIF, priority: ITC_SPR5.VECT16SPR +#define _UART1_T_TC_VECTOR_ 17 ///< UART1_T_TC interrupt vector: enable: UART1_CR2.TCIEN, pending: UART1_SR.TC, priority: ITC_SPR5.VECT17SPR +#define _UART1_T_TXE_VECTOR_ 17 ///< UART1_T_TXE interrupt vector: enable: UART1_CR2.TIEN, pending: UART1_SR.TXE, priority: ITC_SPR5.VECT17SPR +#define _UART1_R_IDLE_VECTOR_ 18 ///< UART1_R_IDLE interrupt vector: enable: UART1_CR2.ILIEN, pending: UART1_SR.IDLE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_LBDF_VECTOR_ 18 ///< UART1_R_LBDF interrupt vector: enable: UART1_CR4.LBDIEN, pending: UART1_CR4.LBDF, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_OR_VECTOR_ 18 ///< UART1_R_OR interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.OR_LHE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_PE_VECTOR_ 18 ///< UART1_R_PE interrupt vector: enable: UART1_CR1.PIEN, pending: UART1_SR.PE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_RXNE_VECTOR_ 18 ///< UART1_R_RXNE interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.RXNE, priority: ITC_SPR5.VECT18SPR +#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR +#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR +#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR +#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR +#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR +#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR +#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR +#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR +#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR +#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR +#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR +#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR +#define _UART3_T_TC_VECTOR_ 20 ///< UART3_T_TC interrupt vector: enable: UART3_CR2.TCIEN, pending: UART3_SR.TC, priority: ITC_SPR6.VECT20SPR +#define _UART3_T_TXE_VECTOR_ 20 ///< UART3_T_TXE interrupt vector: enable: UART3_CR2.TIEN, pending: UART3_SR.TXE, priority: ITC_SPR6.VECT20SPR +#define _UART3_R_IDLE_VECTOR_ 21 ///< UART3_R_IDLE interrupt vector: enable: UART3_CR2.ILIEN, pending: UART3_SR.IDLE, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_LBDF_VECTOR_ 21 ///< UART3_R_LBDF interrupt vector: enable: UART3_CR4.LBDIEN, pending: UART3_CR4.LBDF, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_LHDF_VECTOR_ 21 ///< UART3_R_LHDF interrupt vector: enable: UART3_CR6.LHDIEN, pending: UART3_CR6.LHDF, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_OR_VECTOR_ 21 ///< UART3_R_OR interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.OR, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_PE_VECTOR_ 21 ///< UART3_R_PE interrupt vector: enable: UART3_CR1.PIEN, pending: UART3_SR.PE, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_RXNE_VECTOR_ 21 ///< UART3_R_RXNE interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.RXNE, priority: ITC_SPR6.VECT21SPR +#define _ADC2_AWDG_VECTOR_ 22 ///< ADC2_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR +#define _ADC2_EOC_VECTOR_ 22 ///< ADC2_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR +#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR +#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR +#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR + + +/*------------------------------------------------------------------------- + DEFINITION OF STM8 PERIPHERAL REGISTERS +-------------------------------------------------------------------------*/ + +//------------------------ +// Module ADC2 +//------------------------ + +/** struct containing ADC2 module registers */ +typedef struct { + + /** ADC control/status register (CSR at 0x5400) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS CH : 4; // bits 0-3 + BITS AWDIE : 1; // bit 4 + BITS EOCIE : 1; // bit 5 + BITS AWD : 1; // bit 6 + BITS EOC : 1; // bit 7 + }; // CSR bitfield + + /// register _ADC2_CSR reset value + #define sfr_ADC2_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + + + /** ADC configuration register 1 (CR1 at 0x5401) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS ADON : 1; // bit 0 + BITS CONT : 1; // bit 1 + BITS : 2; // 2 bits + BITS SPSEL : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR1 bitfield + + /// register _ADC2_CR1 reset value + #define sfr_ADC2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** ADC configuration register 2 (CR2 at 0x5402) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 1; // 1 bit + BITS SCAN : 1; // bit 1 + BITS : 1; // 1 bit + BITS ALIGN : 1; // bit 3 + BITS EXTSEL : 2; // bits 4-5 + BITS EXTTRIG : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _ADC2_CR2 reset value + #define sfr_ADC2_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** ADC configuration register 3 (CR3 at 0x5403) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 6; // 6 bits + BITS OVR : 1; // bit 6 + BITS DBUF : 1; // bit 7 + }; // CR3 bitfield + + /// register _ADC2_CR3 reset value + #define sfr_ADC2_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** ADC data register high (DRH at 0x5404) */ + union { + + /// bytewise access to DRH + uint8_t byte; + + /// bitwise access to register DRH + struct { + BITS DH : 8; // bits 0-7 + }; // DRH bitfield + + /// register _ADC2_DRH reset value + #define sfr_ADC2_DRH_RESET_VALUE ((uint8_t) 0x00) + + } DRH; + + + /** ADC data register low (DRL at 0x5405) */ + union { + + /// bytewise access to DRL + uint8_t byte; + + /// bitwise access to register DRL + struct { + BITS DL : 8; // bits 0-7 + }; // DRL bitfield + + /// register _ADC2_DRL reset value + #define sfr_ADC2_DRL_RESET_VALUE ((uint8_t) 0x00) + + } DRL; + + + /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ + union { + + /// bytewise access to TDRH + uint8_t byte; + + /// bitwise access to register TDRH + struct { + BITS TD : 8; // bits 0-7 + }; // TDRH bitfield + + /// register _ADC2_TDRH reset value + #define sfr_ADC2_TDRH_RESET_VALUE ((uint8_t) 0x00) + + } TDRH; + + + /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ + union { + + /// bytewise access to TDRL + uint8_t byte; + + /// bitwise access to register TDRL + struct { + BITS TL : 8; // bits 0-7 + }; // TDRL bitfield + + /// register _ADC2_TDRL reset value + #define sfr_ADC2_TDRL_RESET_VALUE ((uint8_t) 0x00) + + } TDRL; + +} ADC2_t; + +/// access to ADC2 SFR registers +#define sfr_ADC2 (*((ADC2_t*) 0x5400)) + + +//------------------------ +// Module AWU +//------------------------ + +/** struct containing AWU module registers */ +typedef struct { + + /** AWU control/status register 1 (CSR1 at 0x50f0) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS MSR : 1; // bit 0 + BITS : 3; // 3 bits + BITS AWUEN : 1; // bit 4 + BITS AWUF : 1; // bit 5 + BITS : 2; // 2 bits + }; // CSR1 bitfield + + /// register _AWU_CSR1 reset value + #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ + union { + + /// bytewise access to APR + uint8_t byte; + + /// bitwise access to register APR + struct { + BITS APR : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // APR bitfield + + /// register _AWU_APR reset value + #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) + + } APR; + + + /** AWU timebase selection register (TBR at 0x50f2) */ + union { + + /// bytewise access to TBR + uint8_t byte; + + /// bitwise access to register TBR + struct { + BITS AWUTB : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // TBR bitfield + + /// register _AWU_TBR reset value + #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) + + } TBR; + +} AWU_t; + +/// access to AWU SFR registers +#define sfr_AWU (*((AWU_t*) 0x50f0)) + + +//------------------------ +// Module BEEP +//------------------------ + +/** struct containing BEEP module registers */ +typedef struct { + + /** BEEP control/status register (CSR at 0x50f3) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS BEEPDIV : 5; // bits 0-4 + BITS BEEPEN : 1; // bit 5 + BITS BEEPSEL : 2; // bits 6-7 + }; // CSR bitfield + + /// register _BEEP_CSR reset value + #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) + + } CSR; + +} BEEP_t; + +/// access to BEEP SFR registers +#define sfr_BEEP (*((BEEP_t*) 0x50f3)) + + +//------------------------ +// Module CLK +//------------------------ + +/** struct containing CLK module registers */ +typedef struct { + + /** Internal clock control register (ICKR at 0x50c0) */ + union { + + /// bytewise access to ICKR + uint8_t byte; + + /// bitwise access to register ICKR + struct { + BITS HSIEN : 1; // bit 0 + BITS HSIRDY : 1; // bit 1 + BITS FHW : 1; // bit 2 + BITS LSIEN : 1; // bit 3 + BITS LSIRDY : 1; // bit 4 + BITS REGAH : 1; // bit 5 + BITS : 2; // 2 bits + }; // ICKR bitfield + + /// register _CLK_ICKR reset value + #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) + + } ICKR; + + + /** External clock control register (ECKR at 0x50c1) */ + union { + + /// bytewise access to ECKR + uint8_t byte; + + /// bitwise access to register ECKR + struct { + BITS HSEEN : 1; // bit 0 + BITS HSERDY : 1; // bit 1 + BITS : 6; // 6 bits + }; // ECKR bitfield + + /// register _CLK_ECKR reset value + #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) + + } ECKR; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** Clock master status register (CMSR at 0x50c3) */ + union { + + /// bytewise access to CMSR + uint8_t byte; + + /// bitwise access to register CMSR + struct { + BITS CKM : 8; // bits 0-7 + }; // CMSR bitfield + + /// register _CLK_CMSR reset value + #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) + + } CMSR; + + + /** Clock master switch register (SWR at 0x50c4) */ + union { + + /// bytewise access to SWR + uint8_t byte; + + /// bitwise access to register SWR + struct { + BITS SWI : 8; // bits 0-7 + }; // SWR bitfield + + /// register _CLK_SWR reset value + #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) + + } SWR; + + + /** Clock switch control register (SWCR at 0x50c5) */ + union { + + /// bytewise access to SWCR + uint8_t byte; + + /// bitwise access to register SWCR + struct { + BITS SWBSY : 1; // bit 0 + BITS SWEN : 1; // bit 1 + BITS SWIEN : 1; // bit 2 + BITS SWIF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SWCR bitfield + + /// register _CLK_SWCR reset value + #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) + + } SWCR; + + + /** Clock divider register (CKDIVR at 0x50c6) */ + union { + + /// bytewise access to CKDIVR + uint8_t byte; + + /// bitwise access to register CKDIVR + struct { + BITS CPUDIV : 3; // bits 0-2 + BITS HSIDIV : 2; // bits 3-4 + BITS : 3; // 3 bits + }; // CKDIVR bitfield + + /// register _CLK_CKDIVR reset value + #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) + + } CKDIVR; + + + /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ + union { + + /// bytewise access to PCKENR1 + uint8_t byte; + + /// bitwise access to register PCKENR1 + struct { + BITS PCKEN : 8; // bits 0-7 + }; // PCKENR1 bitfield + + /// register _CLK_PCKENR1 reset value + #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR1; + + + /** Clock security system register (CSSR at 0x50c8) */ + union { + + /// bytewise access to CSSR + uint8_t byte; + + /// bitwise access to register CSSR + struct { + BITS CSSEN : 1; // bit 0 + BITS AUX : 1; // bit 1 + BITS CSSDIE : 1; // bit 2 + BITS CSSD : 1; // bit 3 + BITS : 4; // 4 bits + }; // CSSR bitfield + + /// register _CLK_CSSR reset value + #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) + + } CSSR; + + + /** Configurable clock control register (CCOR at 0x50c9) */ + union { + + /// bytewise access to CCOR + uint8_t byte; + + /// bitwise access to register CCOR + struct { + BITS CCOEN : 1; // bit 0 + BITS CCOSEL : 4; // bits 1-4 + BITS CCORDY : 1; // bit 5 + BITS CC0BSY : 1; // bit 6 + BITS : 1; // 1 bit + }; // CCOR bitfield + + /// register _CLK_CCOR reset value + #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) + + } CCOR; + + + /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ + union { + + /// bytewise access to PCKENR2 + uint8_t byte; + + /// bitwise access to register PCKENR2 + struct { + BITS PCKEN2 : 8; // bits 0-7 + }; // PCKENR2 bitfield + + /// register _CLK_PCKENR2 reset value + #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR2; + + + /** CAN clock control register (CANCCR at 0x50cb) */ + union { + + /// bytewise access to CANCCR + uint8_t byte; + + /// bitwise access to register CANCCR + struct { + BITS CANDIV : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // CANCCR bitfield + + /// register _CLK_CANCCR reset value + #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) + + } CANCCR; + + + /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ + union { + + /// bytewise access to HSITRIMR + uint8_t byte; + + /// bitwise access to register HSITRIMR + struct { + BITS HSITRIM : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // HSITRIMR bitfield + + /// register _CLK_HSITRIMR reset value + #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) + + } HSITRIMR; + + + /** SWIM clock control register (SWIMCCR at 0x50cd) */ + union { + + /// bytewise access to SWIMCCR + uint8_t byte; + + /// bitwise access to register SWIMCCR + struct { + BITS SWIMCLK : 1; // bit 0 + BITS : 7; // 7 bits + }; // SWIMCCR bitfield + + /// register _CLK_SWIMCCR reset value + #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) + + } SWIMCCR; + +} CLK_t; + +/// access to CLK SFR registers +#define sfr_CLK (*((CLK_t*) 0x50c0)) + + +//------------------------ +// Module CPU +//------------------------ + +/** struct containing CPU module registers */ +typedef struct { + + /** Accumulator (A at 0x7f00) */ + union { + + /// bytewise access to A + uint8_t byte; + + /// skip bitwise access to register A + + /// register _CPU_A reset value + #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) + + } A; + + + /** Program counter extended (PCE at 0x7f01) */ + union { + + /// bytewise access to PCE + uint8_t byte; + + /// skip bitwise access to register PCE + + /// register _CPU_PCE reset value + #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) + + } PCE; + + + /** Program counter high (PCH at 0x7f02) */ + union { + + /// bytewise access to PCH + uint8_t byte; + + /// skip bitwise access to register PCH + + /// register _CPU_PCH reset value + #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) + + } PCH; + + + /** Program counter low (PCL at 0x7f03) */ + union { + + /// bytewise access to PCL + uint8_t byte; + + /// skip bitwise access to register PCL + + /// register _CPU_PCL reset value + #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) + + } PCL; + + + /** X index register high (XH at 0x7f04) */ + union { + + /// bytewise access to XH + uint8_t byte; + + /// skip bitwise access to register XH + + /// register _CPU_XH reset value + #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) + + } XH; + + + /** X index register low (XL at 0x7f05) */ + union { + + /// bytewise access to XL + uint8_t byte; + + /// skip bitwise access to register XL + + /// register _CPU_XL reset value + #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) + + } XL; + + + /** Y index register high (YH at 0x7f06) */ + union { + + /// bytewise access to YH + uint8_t byte; + + /// skip bitwise access to register YH + + /// register _CPU_YH reset value + #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) + + } YH; + + + /** Y index register low (YL at 0x7f07) */ + union { + + /// bytewise access to YL + uint8_t byte; + + /// skip bitwise access to register YL + + /// register _CPU_YL reset value + #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) + + } YL; + + + /** Stack pointer high (SPH at 0x7f08) */ + union { + + /// bytewise access to SPH + uint8_t byte; + + /// skip bitwise access to register SPH + + /// register _CPU_SPH reset value + #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x17) + + } SPH; + + + /** Stack pointer low (SPL at 0x7f09) */ + union { + + /// bytewise access to SPL + uint8_t byte; + + /// skip bitwise access to register SPL + + /// register _CPU_SPL reset value + #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) + + } SPL; + + + /** Condition code register (CCR at 0x7f0a) */ + union { + + /// bytewise access to CCR + uint8_t byte; + + /// bitwise access to register CCR + struct { + BITS C : 1; // bit 0 + BITS Z : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS I0 : 1; // bit 3 + BITS H : 1; // bit 4 + BITS I1 : 1; // bit 5 + BITS : 1; // 1 bit + BITS V : 1; // bit 7 + }; // CCR bitfield + + /// register _CPU_CCR reset value + #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) + + } CCR; + + + /// Reserved register (85B) + uint8_t Reserved_1[85]; + + + /** Global configuration register (CFG_GCR at 0x7f60) */ + union { + + /// bytewise access to CFG_GCR + uint8_t byte; + + /// bitwise access to register CFG_GCR + struct { + BITS SWO : 1; // bit 0 + BITS AL : 1; // bit 1 + BITS : 6; // 6 bits + }; // CFG_GCR bitfield + + /// register _CPU_CFG_GCR reset value + #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) + + } CFG_GCR; + +} CPU_t; + +/// access to CPU SFR registers +#define sfr_CPU (*((CPU_t*) 0x7f00)) + + +//------------------------ +// Module DM +//------------------------ + +/** struct containing DM module registers */ +typedef struct { + + /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ + union { + + /// bytewise access to BK1RE + uint8_t byte; + + /// skip bitwise access to register BK1RE + + /// register _DM_BK1RE reset value + #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RE; + + + /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ + union { + + /// bytewise access to BK1RH + uint8_t byte; + + /// skip bitwise access to register BK1RH + + /// register _DM_BK1RH reset value + #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RH; + + + /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ + union { + + /// bytewise access to BK1RL + uint8_t byte; + + /// skip bitwise access to register BK1RL + + /// register _DM_BK1RL reset value + #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RL; + + + /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ + union { + + /// bytewise access to BK2RE + uint8_t byte; + + /// skip bitwise access to register BK2RE + + /// register _DM_BK2RE reset value + #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RE; + + + /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ + union { + + /// bytewise access to BK2RH + uint8_t byte; + + /// skip bitwise access to register BK2RH + + /// register _DM_BK2RH reset value + #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RH; + + + /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ + union { + + /// bytewise access to BK2RL + uint8_t byte; + + /// skip bitwise access to register BK2RL + + /// register _DM_BK2RL reset value + #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RL; + + + /** DM debug module control register 1 (CR1 at 0x7f96) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// skip bitwise access to register CR1 + + /// register _DM_CR1 reset value + #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** DM debug module control register 2 (CR2 at 0x7f97) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// skip bitwise access to register CR2 + + /// register _DM_CR2 reset value + #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// skip bitwise access to register CSR1 + + /// register _DM_CSR1 reset value + #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) + + } CSR1; + + + /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// skip bitwise access to register CSR2 + + /// register _DM_CSR2 reset value + #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + + + /** DM enable function register (ENFCTR at 0x7f9a) */ + union { + + /// bytewise access to ENFCTR + uint8_t byte; + + /// skip bitwise access to register ENFCTR + + /// register _DM_ENFCTR reset value + #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) + + } ENFCTR; + +} DM_t; + +/// access to DM SFR registers +#define sfr_DM (*((DM_t*) 0x7f90)) + + +//------------------------ +// Module FLASH +//------------------------ + +/** struct containing FLASH module registers */ +typedef struct { + + /** Flash control register 1 (CR1 at 0x505a) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS FIX : 1; // bit 0 + BITS IE : 1; // bit 1 + BITS AHALT : 1; // bit 2 + BITS HALT : 1; // bit 3 + BITS : 4; // 4 bits + }; // CR1 bitfield + + /// register _FLASH_CR1 reset value + #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Flash control register 2 (CR2 at 0x505b) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS FPRG : 1; // bit 4 + BITS ERASE : 1; // bit 5 + BITS WPRG : 1; // bit 6 + BITS OPT : 1; // bit 7 + }; // CR2 bitfield + + /// register _FLASH_CR2 reset value + #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** Flash complementary control register 2 (NCR2 at 0x505c) */ + union { + + /// bytewise access to NCR2 + uint8_t byte; + + /// bitwise access to register NCR2 + struct { + BITS NPRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS NFPRG : 1; // bit 4 + BITS NERASE : 1; // bit 5 + BITS NWPRG : 1; // bit 6 + BITS NOPT : 1; // bit 7 + }; // NCR2 bitfield + + /// register _FLASH_NCR2 reset value + #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) + + } NCR2; + + + /** Flash protection register (FPR at 0x505d) */ + union { + + /// bytewise access to FPR + uint8_t byte; + + /// bitwise access to register FPR + struct { + BITS WPB0 : 1; // bit 0 + BITS WPB1 : 1; // bit 1 + BITS WPB2 : 1; // bit 2 + BITS WPB3 : 1; // bit 3 + BITS WPB4 : 1; // bit 4 + BITS WPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // FPR bitfield + + /// register _FLASH_FPR reset value + #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) + + } FPR; + + + /** Flash complementary protection register (NFPR at 0x505e) */ + union { + + /// bytewise access to NFPR + uint8_t byte; + + /// bitwise access to register NFPR + struct { + BITS NWPB0 : 1; // bit 0 + BITS NWPB1 : 1; // bit 1 + BITS NWPB2 : 1; // bit 2 + BITS NWPB3 : 1; // bit 3 + BITS NWPB4 : 1; // bit 4 + BITS NWPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // NFPR bitfield + + /// register _FLASH_NFPR reset value + #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) + + } NFPR; + + + /** Flash in-application programming status register (IAPSR at 0x505f) */ + union { + + /// bytewise access to IAPSR + uint8_t byte; + + /// bitwise access to register IAPSR + struct { + BITS WR_PG_DIS : 1; // bit 0 + BITS PUL : 1; // bit 1 + BITS EOP : 1; // bit 2 + BITS DUL : 1; // bit 3 + BITS : 2; // 2 bits + BITS HVOFF : 1; // bit 6 + BITS : 1; // 1 bit + }; // IAPSR bitfield + + /// register _FLASH_IAPSR reset value + #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) + + } IAPSR; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash Program memory unprotection register (PUKR at 0x5062) */ + union { + + /// bytewise access to PUKR + uint8_t byte; + + /// bitwise access to register PUKR + struct { + BITS MASS_PRG : 8; // bits 0-7 + }; // PUKR bitfield + + /// register _FLASH_PUKR reset value + #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) + + } PUKR; + + + /// Reserved register (1B) + uint8_t Reserved_2[1]; + + + /** Data EEPROM unprotection register (DUKR at 0x5064) */ + union { + + /// bytewise access to DUKR + uint8_t byte; + + /// bitwise access to register DUKR + struct { + BITS MASS_DATA : 8; // bits 0-7 + }; // DUKR bitfield + + /// register _FLASH_DUKR reset value + #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) + + } DUKR; + +} FLASH_t; + +/// access to FLASH SFR registers +#define sfr_FLASH (*((FLASH_t*) 0x505a)) + + +//------------------------ +// Module I2C +//------------------------ + +/** struct containing I2C module registers */ +typedef struct { + + /** I2C control register 1 (CR1 at 0x5210) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PE : 1; // bit 0 + BITS : 5; // 5 bits + BITS ENGC : 1; // bit 6 + BITS NOSTRETCH : 1; // bit 7 + }; // CR1 bitfield + + /// register _I2C_CR1 reset value + #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** I2C control register 2 (CR2 at 0x5211) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS START : 1; // bit 0 + BITS STOP : 1; // bit 1 + BITS ACK : 1; // bit 2 + BITS POS : 1; // bit 3 + BITS : 3; // 3 bits + BITS SWRST : 1; // bit 7 + }; // CR2 bitfield + + /// register _I2C_CR2 reset value + #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** I2C frequency register (FREQR at 0x5212) */ + union { + + /// bytewise access to FREQR + uint8_t byte; + + /// bitwise access to register FREQR + struct { + BITS FREQ : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // FREQR bitfield + + /// register _I2C_FREQR reset value + #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) + + } FREQR; + + + /** I2C own address register low (OARL at 0x5213) */ + union { + + /// bytewise access to OARL + uint8_t byte; + + /// bitwise access to register OARL + struct { + BITS ADD0 : 1; // bit 0 + BITS ADD : 7; // bits 1-7 + }; // OARL bitfield + + /// register _I2C_OARL reset value + #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) + + } OARL; + + + /** I2C own address register high (OARH at 0x5214) */ + union { + + /// bytewise access to OARH + uint8_t byte; + + /// bitwise access to register OARH + struct { + BITS : 1; // 1 bit + BITS ADD : 2; // bits 1-2 + BITS : 3; // 3 bits + BITS ADDCONF : 1; // bit 6 + BITS ADDMODE : 1; // bit 7 + }; // OARH bitfield + + /// register _I2C_OARH reset value + #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) + + } OARH; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** I2C data register (DR at 0x5216) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _I2C_DR reset value + #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** I2C status register 1 (SR1 at 0x5217) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS SB : 1; // bit 0 + BITS ADDR : 1; // bit 1 + BITS BTF : 1; // bit 2 + BITS ADD10 : 1; // bit 3 + BITS STOPF : 1; // bit 4 + BITS : 1; // 1 bit + BITS RXNE : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR1 bitfield + + /// register _I2C_SR1 reset value + #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** I2C status register 2 (SR2 at 0x5218) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS BERR : 1; // bit 0 + BITS ARLO : 1; // bit 1 + BITS AF : 1; // bit 2 + BITS OVR : 1; // bit 3 + BITS : 1; // 1 bit + BITS WUFH : 1; // bit 5 + BITS : 2; // 2 bits + }; // SR2 bitfield + + /// register _I2C_SR2 reset value + #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** I2C status register 3 (SR3 at 0x5219) */ + union { + + /// bytewise access to SR3 + uint8_t byte; + + /// bitwise access to register SR3 + struct { + BITS MSL : 1; // bit 0 + BITS BUSY : 1; // bit 1 + BITS TRA : 1; // bit 2 + BITS : 1; // 1 bit + BITS GENCALL : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR3 bitfield + + /// register _I2C_SR3 reset value + #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) + + } SR3; + + + /** I2C interrupt control register (ITR at 0x521a) */ + union { + + /// bytewise access to ITR + uint8_t byte; + + /// bitwise access to register ITR + struct { + BITS ITERREN : 1; // bit 0 + BITS ITEVTEN : 1; // bit 1 + BITS ITBUFEN : 1; // bit 2 + BITS : 5; // 5 bits + }; // ITR bitfield + + /// register _I2C_ITR reset value + #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) + + } ITR; + + + /** I2C clock control register low (CCRL at 0x521b) */ + union { + + /// bytewise access to CCRL + uint8_t byte; + + /// bitwise access to register CCRL + struct { + BITS CCR : 8; // bits 0-7 + }; // CCRL bitfield + + /// register _I2C_CCRL reset value + #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) + + } CCRL; + + + /** I2C clock control register high (CCRH at 0x521c) */ + union { + + /// bytewise access to CCRH + uint8_t byte; + + /// bitwise access to register CCRH + struct { + BITS CCR : 4; // bits 0-3 + BITS : 2; // 2 bits + BITS DUTY : 1; // bit 6 + BITS F_S : 1; // bit 7 + }; // CCRH bitfield + + /// register _I2C_CCRH reset value + #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) + + } CCRH; + + + /** I2C TRISE register (TRISER at 0x521d) */ + union { + + /// bytewise access to TRISER + uint8_t byte; + + /// bitwise access to register TRISER + struct { + BITS TRISE : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // TRISER bitfield + + /// register _I2C_TRISER reset value + #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) + + } TRISER; + + + /** I2C packet error checking register (PECR at 0x521e) */ + union { + + /// bytewise access to PECR + uint8_t byte; + + /// skip bitwise access to register PECR + + /// register _I2C_PECR reset value + #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) + + } PECR; + +} I2C_t; + +/// access to I2C SFR registers +#define sfr_I2C (*((I2C_t*) 0x5210)) + + +//------------------------ +// Module ITC +//------------------------ + +/** struct containing ITC module registers */ +typedef struct { + + /** External interrupt control register 1 (CR1 at 0x50a0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PAIS : 2; // bits 0-1 + BITS PBIS : 2; // bits 2-3 + BITS PCIS : 2; // bits 4-5 + BITS PDIS : 2; // bits 6-7 + }; // CR1 bitfield + + /// register _ITC_CR1 reset value + #define sfr_ITC_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** External interrupt control register 2 (CR2 at 0x50a1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PEIS : 2; // bits 0-1 + BITS TLIS : 1; // bit 2 + BITS : 5; // 5 bits + }; // CR2 bitfield + + /// register _ITC_CR2 reset value + #define sfr_ITC_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /// Reserved register (11982B) + uint8_t Reserved_1[11982]; + + + /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ + union { + + /// bytewise access to SPR1 + uint8_t byte; + + /// bitwise access to register SPR1 + struct { + BITS VECT0SPR : 2; // bits 0-1 + BITS VECT1SPR : 2; // bits 2-3 + BITS VECT2SPR : 2; // bits 4-5 + BITS VECT3SPR : 2; // bits 6-7 + }; // SPR1 bitfield + + /// register _ITC_SPR1 reset value + #define sfr_ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF) + + } SPR1; + + + /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ + union { + + /// bytewise access to SPR2 + uint8_t byte; + + /// bitwise access to register SPR2 + struct { + BITS VECT4SPR : 2; // bits 0-1 + BITS VECT5SPR : 2; // bits 2-3 + BITS VECT6SPR : 2; // bits 4-5 + BITS VECT7SPR : 2; // bits 6-7 + }; // SPR2 bitfield + + /// register _ITC_SPR2 reset value + #define sfr_ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF) + + } SPR2; + + + /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ + union { + + /// bytewise access to SPR3 + uint8_t byte; + + /// bitwise access to register SPR3 + struct { + BITS VECT8SPR : 2; // bits 0-1 + BITS VECT9SPR : 2; // bits 2-3 + BITS VECT10SPR : 2; // bits 4-5 + BITS VECT11SPR : 2; // bits 6-7 + }; // SPR3 bitfield + + /// register _ITC_SPR3 reset value + #define sfr_ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF) + + } SPR3; + + + /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ + union { + + /// bytewise access to SPR4 + uint8_t byte; + + /// bitwise access to register SPR4 + struct { + BITS VECT12SPR : 2; // bits 0-1 + BITS VECT13SPR : 2; // bits 2-3 + BITS VECT14SPR : 2; // bits 4-5 + BITS VECT15SPR : 2; // bits 6-7 + }; // SPR4 bitfield + + /// register _ITC_SPR4 reset value + #define sfr_ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF) + + } SPR4; + + + /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ + union { + + /// bytewise access to SPR5 + uint8_t byte; + + /// bitwise access to register SPR5 + struct { + BITS VECT16SPR : 2; // bits 0-1 + BITS VECT17SPR : 2; // bits 2-3 + BITS VECT18SPR : 2; // bits 4-5 + BITS VECT19SPR : 2; // bits 6-7 + }; // SPR5 bitfield + + /// register _ITC_SPR5 reset value + #define sfr_ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF) + + } SPR5; + + + /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ + union { + + /// bytewise access to SPR6 + uint8_t byte; + + /// bitwise access to register SPR6 + struct { + BITS VECT20SPR : 2; // bits 0-1 + BITS VECT21SPR : 2; // bits 2-3 + BITS VECT22SPR : 2; // bits 4-5 + BITS VECT23SPR : 2; // bits 6-7 + }; // SPR6 bitfield + + /// register _ITC_SPR6 reset value + #define sfr_ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF) + + } SPR6; + + + /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ + union { + + /// bytewise access to SPR7 + uint8_t byte; + + /// bitwise access to register SPR7 + struct { + BITS VECT24SPR : 2; // bits 0-1 + BITS VECT25SPR : 2; // bits 2-3 + BITS VECT26SPR : 2; // bits 4-5 + BITS VECT27SPR : 2; // bits 6-7 + }; // SPR7 bitfield + + /// register _ITC_SPR7 reset value + #define sfr_ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF) + + } SPR7; + + + /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ + union { + + /// bytewise access to SPR8 + uint8_t byte; + + /// bitwise access to register SPR8 + struct { + BITS VECT28SPR : 2; // bits 0-1 + BITS VECT29SPR : 2; // bits 2-3 + BITS : 4; // 4 bits + }; // SPR8 bitfield + + /// register _ITC_SPR8 reset value + #define sfr_ITC_SPR8_RESET_VALUE ((uint8_t) 0xFF) + + } SPR8; + +} ITC_t; + +/// access to ITC SFR registers +#define sfr_ITC (*((ITC_t*) 0x50a0)) + + +//------------------------ +// Module IWDG +//------------------------ + +/** struct containing IWDG module registers */ +typedef struct { + + /** IWDG key register (KR at 0x50e0) */ + union { + + /// bytewise access to KR + uint8_t byte; + + /// bitwise access to register KR + struct { + BITS KEY : 8; // bits 0-7 + }; // KR bitfield + + /// register _IWDG_KR reset value + #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) + + } KR; + + + /** IWDG prescaler register (PR at 0x50e1) */ + union { + + /// bytewise access to PR + uint8_t byte; + + /// bitwise access to register PR + struct { + BITS PR : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PR bitfield + + /// register _IWDG_PR reset value + #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) + + } PR; + + + /** IWDG reload register (RLR at 0x50e2) */ + union { + + /// bytewise access to RLR + uint8_t byte; + + /// bitwise access to register RLR + struct { + BITS RL : 8; // bits 0-7 + }; // RLR bitfield + + /// register _IWDG_RLR reset value + #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) + + } RLR; + +} IWDG_t; + +/// access to IWDG SFR registers +#define sfr_IWDG (*((IWDG_t*) 0x50e0)) + + +//------------------------ +// Module OPT +//------------------------ + +/** struct containing OPT module registers */ +typedef struct { + + /** Read-out protection (ROP) (OPT0 at 0x4800) */ + union { + + /// bytewise access to OPT0 + uint8_t byte; + + /// skip bitwise access to register OPT0 + + /// register _OPT_OPT0 reset value + #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) + + } OPT0; + + + /** User boot code (UBC) (OPT1 at 0x4801) */ + union { + + /// bytewise access to OPT1 + uint8_t byte; + + /// skip bitwise access to register OPT1 + + /// register _OPT_OPT1 reset value + #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) + + } OPT1; + + + /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ + union { + + /// bytewise access to NOPT1 + uint8_t byte; + + /// skip bitwise access to register NOPT1 + + /// register _OPT_NOPT1 reset value + #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT1; + + + /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ + union { + + /// bytewise access to OPT2 + uint8_t byte; + + /// skip bitwise access to register OPT2 + + /// register _OPT_OPT2 reset value + #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) + + } OPT2; + + + /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ + union { + + /// bytewise access to NOPT2 + uint8_t byte; + + /// skip bitwise access to register NOPT2 + + /// register _OPT_NOPT2 reset value + #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT2; + + + /** Watchdog option (OPT3 at 0x4805) */ + union { + + /// bytewise access to OPT3 + uint8_t byte; + + /// skip bitwise access to register OPT3 + + /// register _OPT_OPT3 reset value + #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) + + } OPT3; + + + /** Watchdog option (complementary byte) (NOPT3 at 0x4806) */ + union { + + /// bytewise access to NOPT3 + uint8_t byte; + + /// skip bitwise access to register NOPT3 + + /// register _OPT_NOPT3 reset value + #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT3; + + + /** Clock option (OPT4 at 0x4807) */ + union { + + /// bytewise access to OPT4 + uint8_t byte; + + /// skip bitwise access to register OPT4 + + /// register _OPT_OPT4 reset value + #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) + + } OPT4; + + + /** Clock option (complementary byte) (NOPT4 at 0x4808) */ + union { + + /// bytewise access to NOPT4 + uint8_t byte; + + /// skip bitwise access to register NOPT4 + + /// register _OPT_NOPT4 reset value + #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT4; + + + /** HSE clock startup (OPT5 at 0x4809) */ + union { + + /// bytewise access to OPT5 + uint8_t byte; + + /// skip bitwise access to register OPT5 + + /// register _OPT_OPT5 reset value + #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) + + } OPT5; + + + /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ + union { + + /// bytewise access to NOPT5 + uint8_t byte; + + /// skip bitwise access to register NOPT5 + + /// register _OPT_NOPT5 reset value + #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT5; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash wait states (OPT7 at 0x480d) */ + union { + + /// bytewise access to OPT7 + uint8_t byte; + + /// skip bitwise access to register OPT7 + + /// register _OPT_OPT7 reset value + #define sfr_OPT_OPT7_RESET_VALUE ((uint8_t) 0x00) + + } OPT7; + + + /** Flash wait states (complementary byte) (NOPT7 at 0x480e) */ + union { + + /// bytewise access to NOPT7 + uint8_t byte; + + /// skip bitwise access to register NOPT7 + + /// register _OPT_NOPT7 reset value + #define sfr_OPT_NOPT7_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT7; + + + /// Reserved register (111B) + uint8_t Reserved_2[111]; + + + /** Bootloader (OPTBL at 0x487e) */ + union { + + /// bytewise access to OPTBL + uint8_t byte; + + /// skip bitwise access to register OPTBL + + /// register _OPT_OPTBL reset value + #define sfr_OPT_OPTBL_RESET_VALUE ((uint8_t) 0x00) + + } OPTBL; + + + /** Bootloader (complementary byte) (NOPTBL at 0x487f) */ + union { + + /// bytewise access to NOPTBL + uint8_t byte; + + /// skip bitwise access to register NOPTBL + + /// register _OPT_NOPTBL reset value + #define sfr_OPT_NOPTBL_RESET_VALUE ((uint8_t) 0xFF) + + } NOPTBL; + +} OPT_t; + +/// access to OPT SFR registers +#define sfr_OPT (*((OPT_t*) 0x4800)) + + +//------------------------ +// Module PORT +//------------------------ + +/** struct containing PORTA module registers */ +typedef struct { + + /** Port A data output latch register (ODR at 0x5000) */ + union { + + /// bytewise access to ODR + uint8_t byte; + + /// bitwise access to register ODR + struct { + BITS ODR0 : 1; // bit 0 + BITS ODR1 : 1; // bit 1 + BITS ODR2 : 1; // bit 2 + BITS ODR3 : 1; // bit 3 + BITS ODR4 : 1; // bit 4 + BITS ODR5 : 1; // bit 5 + BITS ODR6 : 1; // bit 6 + BITS ODR7 : 1; // bit 7 + }; // ODR bitfield + + /// register _PORT_ODR reset value + #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) + + } ODR; + + + /** Port A input pin value register (IDR at 0x5001) */ + union { + + /// bytewise access to IDR + uint8_t byte; + + /// bitwise access to register IDR + struct { + BITS IDR0 : 1; // bit 0 + BITS IDR1 : 1; // bit 1 + BITS IDR2 : 1; // bit 2 + BITS IDR3 : 1; // bit 3 + BITS IDR4 : 1; // bit 4 + BITS IDR5 : 1; // bit 5 + BITS IDR6 : 1; // bit 6 + BITS IDR7 : 1; // bit 7 + }; // IDR bitfield + + /// register _PORT_IDR reset value + #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) + + } IDR; + + + /** Port A data direction register (DDR at 0x5002) */ + union { + + /// bytewise access to DDR + uint8_t byte; + + /// bitwise access to register DDR + struct { + BITS DDR0 : 1; // bit 0 + BITS DDR1 : 1; // bit 1 + BITS DDR2 : 1; // bit 2 + BITS DDR3 : 1; // bit 3 + BITS DDR4 : 1; // bit 4 + BITS DDR5 : 1; // bit 5 + BITS DDR6 : 1; // bit 6 + BITS DDR7 : 1; // bit 7 + }; // DDR bitfield + + /// register _PORT_DDR reset value + #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) + + } DDR; + + + /** Port A control register 1 (CR1 at 0x5003) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS C10 : 1; // bit 0 + BITS C11 : 1; // bit 1 + BITS C12 : 1; // bit 2 + BITS C13 : 1; // bit 3 + BITS C14 : 1; // bit 4 + BITS C15 : 1; // bit 5 + BITS C16 : 1; // bit 6 + BITS C17 : 1; // bit 7 + }; // CR1 bitfield + + /// register _PORT_CR1 reset value + #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Port A control register 2 (CR2 at 0x5004) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS C20 : 1; // bit 0 + BITS C21 : 1; // bit 1 + BITS C22 : 1; // bit 2 + BITS C23 : 1; // bit 3 + BITS C24 : 1; // bit 4 + BITS C25 : 1; // bit 5 + BITS C26 : 1; // bit 6 + BITS C27 : 1; // bit 7 + }; // CR2 bitfield + + /// register _PORT_CR2 reset value + #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} PORT_t; + +/// access to PORTA SFR registers +#define sfr_PORTA (*((PORT_t*) 0x5000)) + + +/// access to PORTB SFR registers +#define sfr_PORTB (*((PORT_t*) 0x5005)) + + +/// access to PORTC SFR registers +#define sfr_PORTC (*((PORT_t*) 0x500a)) + + +/// access to PORTD SFR registers +#define sfr_PORTD (*((PORT_t*) 0x500f)) + + +/// access to PORTE SFR registers +#define sfr_PORTE (*((PORT_t*) 0x5014)) + + +/// access to PORTF SFR registers +#define sfr_PORTF (*((PORT_t*) 0x5019)) + + +/// access to PORTG SFR registers +#define sfr_PORTG (*((PORT_t*) 0x501e)) + + +/// access to PORTH SFR registers +#define sfr_PORTH (*((PORT_t*) 0x5023)) + + +/// access to PORTI SFR registers +#define sfr_PORTI (*((PORT_t*) 0x5028)) + + +//------------------------ +// Module RST +//------------------------ + +/** struct containing RST module registers */ +typedef struct { + + /** Reset status register (SR at 0x50b3) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS WWDGF : 1; // bit 0 + BITS IWDGF : 1; // bit 1 + BITS ILLOPF : 1; // bit 2 + BITS SWIMF : 1; // bit 3 + BITS EMCF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR bitfield + + /// register _RST_SR reset value + #define sfr_RST_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + +} RST_t; + +/// access to RST SFR registers +#define sfr_RST (*((RST_t*) 0x50b3)) + + +//------------------------ +// Module SPI +//------------------------ + +/** struct containing SPI module registers */ +typedef struct { + + /** SPI control register 1 (CR1 at 0x5200) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CPHA : 1; // bit 0 + BITS CPOL : 1; // bit 1 + BITS MSTR : 1; // bit 2 + BITS BR : 3; // bits 3-5 + BITS SPE : 1; // bit 6 + BITS LSBFIRST : 1; // bit 7 + }; // CR1 bitfield + + /// register _SPI_CR1 reset value + #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** SPI control register 2 (CR2 at 0x5201) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SSI : 1; // bit 0 + BITS SSM : 1; // bit 1 + BITS RXONLY : 1; // bit 2 + BITS : 1; // 1 bit + BITS CRCNEXT : 1; // bit 4 + BITS CECEN : 1; // bit 5 + BITS BDOE : 1; // bit 6 + BITS BDM : 1; // bit 7 + }; // CR2 bitfield + + /// register _SPI_CR2 reset value + #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** SPI interrupt control register (ICR at 0x5202) */ + union { + + /// bytewise access to ICR + uint8_t byte; + + /// bitwise access to register ICR + struct { + BITS : 4; // 4 bits + BITS WKIE : 1; // bit 4 + BITS ERRIE : 1; // bit 5 + BITS RXIE : 1; // bit 6 + BITS TXIE : 1; // bit 7 + }; // ICR bitfield + + /// register _SPI_ICR reset value + #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) + + } ICR; + + + /** SPI status register (SR at 0x5203) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS RXNE : 1; // bit 0 + BITS TXE : 1; // bit 1 + BITS : 1; // 1 bit + BITS WKUP : 1; // bit 3 + BITS CRCERR : 1; // bit 4 + BITS MODF : 1; // bit 5 + BITS OVR : 1; // bit 6 + BITS BSY : 1; // bit 7 + }; // SR bitfield + + /// register _SPI_SR reset value + #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) + + } SR; + + + /** SPI data register (DR at 0x5204) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _SPI_DR reset value + #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** SPI CRC polynomial register (CRCPR at 0x5205) */ + union { + + /// bytewise access to CRCPR + uint8_t byte; + + /// bitwise access to register CRCPR + struct { + BITS CRCPOLY : 8; // bits 0-7 + }; // CRCPR bitfield + + /// register _SPI_CRCPR reset value + #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) + + } CRCPR; + + + /** SPI Rx CRC register (RXCRCR at 0x5206) */ + union { + + /// bytewise access to RXCRCR + uint8_t byte; + + /// bitwise access to register RXCRCR + struct { + BITS RXCRC : 8; // bits 0-7 + }; // RXCRCR bitfield + + /// register _SPI_RXCRCR reset value + #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } RXCRCR; + + + /** SPI Tx CRC register (TXCRCR at 0x5207) */ + union { + + /// bytewise access to TXCRCR + uint8_t byte; + + /// bitwise access to register TXCRCR + struct { + BITS TXCRC : 8; // bits 0-7 + }; // TXCRCR bitfield + + /// register _SPI_TXCRCR reset value + #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } TXCRCR; + +} SPI_t; + +/// access to SPI SFR registers +#define sfr_SPI (*((SPI_t*) 0x5200)) + + +//------------------------ +// Module SWIM +//------------------------ + +/** struct containing SWIM module registers */ +typedef struct { + + /** SWIM control status register (CSR at 0x7f80) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// skip bitwise access to register CSR + + /// register _SWIM_CSR reset value + #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + +} SWIM_t; + +/// access to SWIM SFR registers +#define sfr_SWIM (*((SWIM_t*) 0x7f80)) + + +//------------------------ +// Module TIM1 +//------------------------ + +/** struct containing TIM1 module registers */ +typedef struct { + + /** TIM1 control register 1 (CR1 at 0x5250) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM1_CR1 reset value + #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM1 control register 2 (CR2 at 0x5251) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS CCPG : 1; // bit 0 + BITS : 1; // 1 bit + BITS COMS : 1; // bit 2 + BITS : 1; // 1 bit + BITS MMS : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _TIM1_CR2 reset value + #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM1 slave mode control register (SMCR at 0x5252) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM1_SMCR reset value + #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM1 external trigger register (ETR at 0x5253) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM1_ETR reset value + #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM1 Interrupt enable register (IER at 0x5254) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS CC4IE : 1; // bit 4 + BITS COMIE : 1; // bit 5 + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM1_IER reset value + #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM1 status register 1 (SR1 at 0x5255) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS CC4IF : 1; // bit 4 + BITS COMIF : 1; // bit 5 + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM1_SR1 reset value + #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM1 status register 2 (SR2 at 0x5256) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS CC4OF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR2 bitfield + + /// register _TIM1_SR2 reset value + #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM1 event generation register (EGR at 0x5257) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS CC4G : 1; // bit 4 + BITS COMG : 1; // bit 5 + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM1_EGR reset value + #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS OC1CE : 1; // bit 7 + }; // CCMR1 bitfield + + /// register _TIM1_CCMR1 reset value + #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS OC2CE : 1; // bit 7 + }; // CCMR2 bitfield + + /// register _TIM1_CCMR2 reset value + #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS OC3FE : 1; // bit 2 + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS OC3CE : 1; // bit 7 + }; // CCMR3 bitfield + + /// register _TIM1_CCMR3 reset value + #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ + union { + + /// bytewise access to CCMR4 + uint8_t byte; + + /// bitwise access to register CCMR4 + struct { + BITS CC4S : 2; // bits 0-1 + BITS OC4FE : 1; // bit 2 + BITS OC4PE : 1; // bit 3 + BITS OC4M : 3; // bits 4-6 + BITS OC4CE : 1; // bit 7 + }; // CCMR4 bitfield + + /// register _TIM1_CCMR4 reset value + #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) + + } CCMR4; + + + /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS CC1NE : 1; // bit 2 + BITS CC1NP : 1; // bit 3 + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS CC2NE : 1; // bit 6 + BITS CC2NP : 1; // bit 7 + }; // CCER1 bitfield + + /// register _TIM1_CCER1 reset value + #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS CC3NE : 1; // bit 2 + BITS CC3NP : 1; // bit 3 + BITS CC4E : 1; // bit 4 + BITS CC4P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER2 bitfield + + /// register _TIM1_CCER2 reset value + #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM1 counter high (CNTRH at 0x525e) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM1_CNTRH reset value + #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM1 counter low (CNTRL at 0x525f) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM1_CNTRL reset value + #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM1 prescaler register high (PSCRH at 0x5260) */ + union { + + /// bytewise access to PSCRH + uint8_t byte; + + /// bitwise access to register PSCRH + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRH bitfield + + /// register _TIM1_PSCRH reset value + #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) + + } PSCRH; + + + /** TIM1 prescaler register low (PSCRL at 0x5261) */ + union { + + /// bytewise access to PSCRL + uint8_t byte; + + /// bitwise access to register PSCRL + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRL bitfield + + /// register _TIM1_PSCRL reset value + #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) + + } PSCRL; + + + /** TIM1 auto-reload register high (ARRH at 0x5262) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM1_ARRH reset value + #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM1 auto-reload register low (ARRL at 0x5263) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM1_ARRL reset value + #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM1 repetition counter register (RCR at 0x5264) */ + union { + + /// bytewise access to RCR + uint8_t byte; + + /// bitwise access to register RCR + struct { + BITS REP : 8; // bits 0-7 + }; // RCR bitfield + + /// register _TIM1_RCR reset value + #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) + + } RCR; + + + /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM1_CCR1H reset value + #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM1_CCR1L reset value + #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM1_CCR2H reset value + #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM1_CCR2L reset value + #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM1_CCR3H reset value + #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM1_CCR3L reset value + #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + + + /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ + union { + + /// bytewise access to CCR4H + uint8_t byte; + + /// bitwise access to register CCR4H + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4H bitfield + + /// register _TIM1_CCR4H reset value + #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) + + } CCR4H; + + + /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ + union { + + /// bytewise access to CCR4L + uint8_t byte; + + /// bitwise access to register CCR4L + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4L bitfield + + /// register _TIM1_CCR4L reset value + #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) + + } CCR4L; + + + /** TIM1 break register (BKR at 0x526d) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS OSSR : 1; // bit 3 + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM1_BKR reset value + #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM1 dead-time register (DTR at 0x526e) */ + union { + + /// bytewise access to DTR + uint8_t byte; + + /// bitwise access to register DTR + struct { + BITS DTG : 8; // bits 0-7 + }; // DTR bitfield + + /// register _TIM1_DTR reset value + #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) + + } DTR; + + + /** TIM1 output idle state register (OISR at 0x526f) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS OIS1N : 1; // bit 1 + BITS OIS2 : 1; // bit 2 + BITS OIS2N : 1; // bit 3 + BITS OIS3 : 1; // bit 4 + BITS OIS3N : 1; // bit 5 + BITS OIS4 : 1; // bit 6 + BITS : 1; // 1 bit + }; // OISR bitfield + + /// register _TIM1_OISR reset value + #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + +} TIM1_t; + +/// access to TIM1 SFR registers +#define sfr_TIM1 (*((TIM1_t*) 0x5250)) + + +//------------------------ +// Module TIM2 +//------------------------ + +/** struct containing TIM2 module registers */ +typedef struct { + + /** TIM2 control register 1 (CR1 at 0x5300) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM2_CR1 reset value + #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM2 interrupt enable register (IER at 0x5301) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM2_IER reset value + #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM2 status register 1 (SR1 at 0x5302) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM2_SR1 reset value + #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM2 status register 2 (SR2 at 0x5303) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM2_SR2 reset value + #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM2 event generation register (EGR at 0x5304) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM2_EGR reset value + #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5305) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM2_CCMR1 reset value + #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5306) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM2_CCMR2 reset value + #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5307) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR3 bitfield + + /// register _TIM2_CCMR3 reset value + #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM2 capture/compare enable register 1 (CCER1 at 0x5308) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM2_CCER1 reset value + #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM2 capture/compare enable register 2 (CCER2 at 0x5309) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS : 6; // 6 bits + }; // CCER2 bitfield + + /// register _TIM2_CCER2 reset value + #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM2 counter high (CNTRH at 0x530a) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM2_CNTRH reset value + #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM2 counter low (CNTRL at 0x530b) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM2_CNTRL reset value + #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM2 prescaler register (PSCR at 0x530c) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM2_PSCR reset value + #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM2 auto-reload register high (ARRH at 0x530d) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM2_ARRH reset value + #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM2 auto-reload register low (ARRL at 0x530e) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM2_ARRL reset value + #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM2 capture/compare register 1 high (CCR1H at 0x530f) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM2_CCR1H reset value + #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM2 capture/compare register 1 low (CCR1L at 0x5310) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM2_CCR1L reset value + #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM2 capture/compare reg (CCR2H at 0x5311) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM2_CCR2H reset value + #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM2 capture/compare register 2 low (CCR2L at 0x5312) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM2_CCR2L reset value + #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM2 capture/compare register 3 high (CCR3H at 0x5313) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM2_CCR3H reset value + #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM2 capture/compare register 3 low (CCR3L at 0x5314) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM2_CCR3L reset value + #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + +} TIM2_t; + +/// access to TIM2 SFR registers +#define sfr_TIM2 (*((TIM2_t*) 0x5300)) + + +//------------------------ +// Module TIM3 +//------------------------ + +/** struct containing TIM3 module registers */ +typedef struct { + + /** TIM3 control register 1 (CR1 at 0x5320) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM3_CR1 reset value + #define sfr_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM3 interrupt enable register (IER at 0x5321) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM3_IER reset value + #define sfr_TIM3_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM3 status register 1 (SR1 at 0x5322) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM3_SR1 reset value + #define sfr_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM3 status register 2 (SR2 at 0x5323) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM3_SR2 reset value + #define sfr_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM3 event generation register (EGR at 0x5324) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM3_EGR reset value + #define sfr_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM3 capture/compare mode register 1 (CCMR1 at 0x5325) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM3_CCMR1 reset value + #define sfr_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM3 capture/compare mode register 2 (CCMR2 at 0x5326) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM3_CCMR2 reset value + #define sfr_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM3 capture/compare enable register 1 (CCER1 at 0x5327) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM3_CCER1 reset value + #define sfr_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM3 counter high (CNTRH at 0x5328) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM3_CNTRH reset value + #define sfr_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM3 counter low (CNTRL at 0x5329) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM3_CNTRL reset value + #define sfr_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM3 prescaler register (PSCR at 0x532a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM3_PSCR reset value + #define sfr_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM3 auto-reload register high (ARRH at 0x532b) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM3_ARRH reset value + #define sfr_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM3 auto-reload register low (ARRL at 0x532c) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM3_ARRL reset value + #define sfr_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM3 capture/compare register 1 high (CCR1H at 0x532d) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM3_CCR1H reset value + #define sfr_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM3 capture/compare register 1 low (CCR1L at 0x532e) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM3_CCR1L reset value + #define sfr_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM3 capture/compare register 2 high (CCR2H at 0x532f) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM3_CCR2H reset value + #define sfr_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM3 capture/compare register 2 low (CCR2L at 0x5330) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM3_CCR2L reset value + #define sfr_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + +} TIM3_t; + +/// access to TIM3 SFR registers +#define sfr_TIM3 (*((TIM3_t*) 0x5320)) + + +//------------------------ +// Module TIM4 +//------------------------ + +/** struct containing TIM4 module registers */ +typedef struct { + + /** TIM4 control register 1 (CR1 at 0x5340) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM4_CR1 reset value + #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM4 interrupt enable register (IER at 0x5341) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM4_IER reset value + #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM4 status register (SR at 0x5342) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS UIF : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR bitfield + + /// register _TIM4_SR reset value + #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + + + /** TIM4 event generation register (EGR at 0x5343) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS : 5; // 5 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM4_EGR reset value + #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM4 counter (CNTR at 0x5344) */ + union { + + /// bytewise access to CNTR + uint8_t byte; + + /// bitwise access to register CNTR + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTR bitfield + + /// register _TIM4_CNTR reset value + #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) + + } CNTR; + + + /** TIM4 prescaler register (PSCR at 0x5345) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSCR bitfield + + /// register _TIM4_PSCR reset value + #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM4 auto-reload register (ARR at 0x5346) */ + union { + + /// bytewise access to ARR + uint8_t byte; + + /// bitwise access to register ARR + struct { + BITS ARR : 8; // bits 0-7 + }; // ARR bitfield + + /// register _TIM4_ARR reset value + #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) + + } ARR; + +} TIM4_t; + +/// access to TIM4 SFR registers +#define sfr_TIM4 (*((TIM4_t*) 0x5340)) + + +//------------------------ +// Module UART1 +//------------------------ + +/** struct containing UART1 module registers */ +typedef struct { + + /** UART1 status register (SR at 0x5230) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR_LHE : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART1_SR reset value + #define sfr_UART1_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART1 data register (DR at 0x5231) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART1_DR reset value + #define sfr_UART1_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART1 baud rate register 1 (BRR1 at 0x5232) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART1_BRR1 reset value + #define sfr_UART1_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART1 baud rate register 2 (BRR2 at 0x5233) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART1_BRR2 reset value + #define sfr_UART1_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART1 control register 1 (CR1 at 0x5234) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UART0 : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART1_CR1 reset value + #define sfr_UART1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART1 control register 2 (CR2 at 0x5235) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART1_CR2 reset value + #define sfr_UART1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART1 control register 3 (CR3 at 0x5236) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS LBCL : 1; // bit 0 + BITS CPHA : 1; // bit 1 + BITS CPOL : 1; // bit 2 + BITS CKEN : 1; // bit 3 + BITS STOP : 2; // bits 4-5 + BITS : 1; // 1 bit + BITS LINEN : 1; // bit 7 + }; // CR3 bitfield + + /// register _UART1_CR3 reset value + #define sfr_UART1_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART1 control register 4 (CR4 at 0x5237) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART1_CR4 reset value + #define sfr_UART1_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /** UART1 control register 5 (CR5 at 0x5238) */ + union { + + /// bytewise access to CR5 + uint8_t byte; + + /// bitwise access to register CR5 + struct { + BITS : 1; // 1 bit + BITS IREN : 1; // bit 1 + BITS IRLP : 1; // bit 2 + BITS HDSEL : 1; // bit 3 + BITS NACK : 1; // bit 4 + BITS SCEN : 1; // bit 5 + BITS : 2; // 2 bits + }; // CR5 bitfield + + /// register _UART1_CR5 reset value + #define sfr_UART1_CR5_RESET_VALUE ((uint8_t) 0x00) + + } CR5; + + + /** UART1 guard time register (GTR at 0x5239) */ + union { + + /// bytewise access to GTR + uint8_t byte; + + /// bitwise access to register GTR + struct { + BITS GT : 8; // bits 0-7 + }; // GTR bitfield + + /// register _UART1_GTR reset value + #define sfr_UART1_GTR_RESET_VALUE ((uint8_t) 0x00) + + } GTR; + + + /** UART1 prescaler register (PSCR at 0x523a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCR bitfield + + /// register _UART1_PSCR reset value + #define sfr_UART1_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + +} UART1_t; + +/// access to UART1 SFR registers +#define sfr_UART1 (*((UART1_t*) 0x5230)) + + +//------------------------ +// Module UART3 +//------------------------ + +/** struct containing UART3 module registers */ +typedef struct { + + /** UART3 status register (SR at 0x5240) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART3_SR reset value + #define sfr_UART3_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART3 data register (DR at 0x5241) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART3_DR reset value + #define sfr_UART3_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART3 baud rate register 1 (BRR1 at 0x5242) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART3_BRR1 reset value + #define sfr_UART3_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART3 baud rate register 2 (BRR2 at 0x5243) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART3_BRR2 reset value + #define sfr_UART3_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART3 control register 1 (CR1 at 0x5244) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UARTD : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART3_CR1 reset value + #define sfr_UART3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART3 control register 2 (CR2 at 0x5245) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART3_CR2 reset value + #define sfr_UART3_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART3 control register 3 (CR3 at 0x5246) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 4; // 4 bits + BITS STOP : 2; // bits 4-5 + BITS LINEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR3 bitfield + + /// register _UART3_CR3 reset value + #define sfr_UART3_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART3 control register 4 (CR4 at 0x5247) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART3_CR4 reset value + #define sfr_UART3_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** UART3 control register 6 (CR6 at 0x5249) */ + union { + + /// bytewise access to CR6 + uint8_t byte; + + /// bitwise access to register CR6 + struct { + BITS LSF : 1; // bit 0 + BITS LHDF : 1; // bit 1 + BITS LHDIEN : 1; // bit 2 + BITS : 1; // 1 bit + BITS LASE : 1; // bit 4 + BITS LSLV : 1; // bit 5 + BITS : 1; // 1 bit + BITS LDUM : 1; // bit 7 + }; // CR6 bitfield + + /// register _UART3_CR6 reset value + #define sfr_UART3_CR6_RESET_VALUE ((uint8_t) 0x00) + + } CR6; + +} UART3_t; + +/// access to UART3 SFR registers +#define sfr_UART3 (*((UART3_t*) 0x5240)) + + +//------------------------ +// Module WWDG +//------------------------ + +/** struct containing WWDG module registers */ +typedef struct { + + /** WWDG control register (CR at 0x50d1) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS T0 : 1; // bit 0 + BITS T1 : 1; // bit 1 + BITS T2 : 1; // bit 2 + BITS T3 : 1; // bit 3 + BITS T4 : 1; // bit 4 + BITS T5 : 1; // bit 5 + BITS T6 : 1; // bit 6 + BITS WDGA : 1; // bit 7 + }; // CR bitfield + + /// register _WWDG_CR reset value + #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) + + } CR; + + + /** WWDR window register (WR at 0x50d2) */ + union { + + /// bytewise access to WR + uint8_t byte; + + /// bitwise access to register WR + struct { + BITS W0 : 1; // bit 0 + BITS W1 : 1; // bit 1 + BITS W2 : 1; // bit 2 + BITS W3 : 1; // bit 3 + BITS W4 : 1; // bit 4 + BITS W5 : 1; // bit 5 + BITS W6 : 1; // bit 6 + BITS : 1; // 1 bit + }; // WR bitfield + + /// register _WWDG_WR reset value + #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) + + } WR; + +} WWDG_t; + +/// access to WWDG SFR registers +#define sfr_WWDG (*((WWDG_t*) 0x50d1)) + + +// undefine local macros +#undef BITS + +// required for C++ +#ifdef __cplusplus + } // extern "C" +#endif + +/*------------------------------------------------------------------------- + END OF MODULE DEFINITION FOR MULTIPLE INLUSION +-------------------------------------------------------------------------*/ +#endif // STM8S207K8_H diff --git a/examples/native-blink/src/STM8S208RB.h b/examples/native-blink/src/STM8S208RB.h new file mode 100644 index 0000000..31523aa --- /dev/null +++ b/examples/native-blink/src/STM8S208RB.h @@ -0,0 +1,6376 @@ +/*------------------------------------------------------------------------- + + STM8S208RB.h - Device Declarations + + STM8S/STM8AF, high density with ROM bootloader + + Copyright (C) 2020, Georg Icking-Konert + + Mainstream Performance line 8-bit MCU with 128 Kbyes Flash, 24 MHz CPU, integrated EEPROM + + datasheet: https://www.st.com/resource/en/datasheet/stm8s208rb.pdf + reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf + + MIT License + + Copyright (c) 2020 Georg Icking-Konert + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in all + copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + SOFTWARE. + +-------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------- + MODULE DEFINITION FOR MULTIPLE INCLUSION +-------------------------------------------------------------------------*/ +#ifndef STM8S208RB_H +#define STM8S208RB_H + +// DEVICE NAME +#define DEVICE_STM8S208RB + +// DEVICE FAMILY +#define FAMILY_STM8S + +// required for C++ +#ifdef __cplusplus + extern "C" { +#endif + + +/*------------------------------------------------------------------------- + INCLUDE FILES +-------------------------------------------------------------------------*/ +#include + + +/*------------------------------------------------------------------------- + COMPILER SPECIFIC SETTINGS +-------------------------------------------------------------------------*/ + +// Cosmic compiler +#if defined(__CSMC__) + + // macros to unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine + #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine + + // definition of inline functions + #define INLINE @inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling + #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode + #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + + +// IAR Compiler +#elif defined(__ICCSTM8__) + + // include intrinsic functions + #include + + // macros to unify ISR declaration and implementation + #define STRINGVECTOR(x) #x + #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) + #define ISR_HANDLER( a, b ) \ + _Pragma( VECTOR_ID( (b)+2 ) ) \ + __interrupt void (a)( void ) + #define ISR_HANDLER_TRAP(a) \ + _Pragma( VECTOR_ID( 1 ) ) \ + __interrupt void (a) (void) + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling + #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt + #define ENTER_HALT() __halt() ///< put controller to HALT mode + #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) + + +// SDCC compiler +#elif defined(__SDCC) + + // store SDCC version in preprocessor friendly way + #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ + + __SDCC_VERSION_MINOR * 100 \ + + __SDCC_VERSION_PATCH) + + // unify ISR declaration and implementation + #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine + #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 + #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine + #else + #error traps require SDCC >=3.4.3. Please update! + #endif + + // definition of inline functions + #define INLINE static inline ///< keyword for inline functions + + // common assembler instructions + #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) + #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling + #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling + #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) + #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt + #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode + #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) + + // data type in bit fields + #define BITS unsigned int ///< data type in bit structs (follow C90 standard) + +// unsupported compiler -> stop +#else + #error: compiler not supported +#endif + + +/*------------------------------------------------------------------------- + FOR CONVENIENT PIN ACCESS +-------------------------------------------------------------------------*/ + +#define PIN0 0x01 +#define PIN1 0x02 +#define PIN2 0x04 +#define PIN3 0x08 +#define PIN4 0x10 +#define PIN5 0x20 +#define PIN6 0x40 +#define PIN7 0x80 + + +/*------------------------------------------------------------------------- + DEVICE MEMORY (size in bytes) +-------------------------------------------------------------------------*/ + +// RAM +#define RAM_ADDR_START 0x000000 +#define RAM_ADDR_END 0x0017FF +#define RAM_SIZE 6144 + + +// FLASH +#define FLASH_ADDR_START 0x008000 +#define FLASH_ADDR_END 0x027FFF +#define FLASH_SIZE 131072 + + +// SFR1 +#define SFR1_ADDR_START 0x005000 +#define SFR1_ADDR_END 0x0057FF +#define SFR1_SIZE 2048 + + +// SFR2 +#define SFR2_ADDR_START 0x007F00 +#define SFR2_ADDR_END 0x007FFF +#define SFR2_SIZE 256 + + +// BOOTROM +#define BOOTROM_ADDR_START 0x006000 +#define BOOTROM_ADDR_END 0x0067FF +#define BOOTROM_SIZE 2048 + + +// EEPROM +#define EEPROM_ADDR_START 0x004000 +#define EEPROM_ADDR_END 0x0047FF +#define EEPROM_SIZE 2048 + + +// OPTION +#define OPTION_ADDR_START 0x004800 +#define OPTION_ADDR_END 0x00487F +#define OPTION_SIZE 128 + + +// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) +#define FLASH_ADDR_WIDTH 32 ///< width of address space +#define FLASH_POINTER_T uint32_t ///< address variable type + + +/*------------------------------------------------------------------------- + UNIQUE IDENTIFIER (size in bytes) +-------------------------------------------------------------------------*/ + +#define UID_ADDR_START 0x48CD ///< start address of unique identifier +#define UID_SIZE 12 ///< size of unique identifier [B] +#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N + + +/*------------------------------------------------------------------------- + MISC OPTIONS +-------------------------------------------------------------------------*/ + +/// LSI frequency measurement channel +#define LSI_MEASURE_TIM3_IC1 + + +/*------------------------------------------------------------------------- + ISR Vector Table (SDCC, IAR) + Notes: + - IAR has an IRQ offset of +2 compared to datasheet and below numbers + - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' + - different interrupt sources may share the same IRQ +-------------------------------------------------------------------------*/ + +// interrupt IRQ +#define _TLI_VECTOR_ 0 +#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR +#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR +#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR +#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR +#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR +#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR +#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR +#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR +#define _CAN_FMP_VECTOR_ 8 ///< CAN_FMP interrupt vector: enable: CAN_IER.FMPIE, pending: CAN_RFR.FMP, priority: ITC_SPR3.VECT8SPR +#define _CAN_FOVR_VECTOR_ 8 ///< CAN_FOVR interrupt vector: enable: CAN_IER.FOVIE, pending: CAN_RFR.FOVR, priority: ITC_SPR3.VECT8SPR +#define _CAN_FULL_VECTOR_ 8 ///< CAN_FULL interrupt vector: enable: CAN_IER.FFIE, pending: CAN_RFR.FULL, priority: ITC_SPR3.VECT8SPR +#define _CAN_BOFF_VECTOR_ 9 ///< CAN_BOFF interrupt vector: enable: CAN_EIER.BOFIE, pending: CAN_ESR.BOFF, priority: ITC_SPR3.VECT9SPR +#define _CAN_EPVF_VECTOR_ 9 ///< CAN_EPVF interrupt vector: enable: CAN_EIER.EPVIE, pending: CAN_ESR.EPVF, priority: ITC_SPR3.VECT9SPR +#define _CAN_EWGF_VECTOR_ 9 ///< CAN_EWGF interrupt vector: enable: CAN_EIER.EWGIE, pending: CAN_ESR.EWGF, priority: ITC_SPR3.VECT9SPR +#define _CAN_LEC0_VECTOR_ 9 ///< CAN_LEC0 interrupt vector: enable: CAN_EIER.LECIE, pending: CAN_ESR.LEC0, priority: ITC_SPR3.VECT9SPR +#define _CAN_LEC1_VECTOR_ 9 ///< CAN_LEC1 interrupt vector: enable: CAN_EIER.LECIE, pending: CAN_ESR.LEC1, priority: ITC_SPR3.VECT9SPR +#define _CAN_LEC2_VECTOR_ 9 ///< CAN_LEC2 interrupt vector: enable: CAN_EIER.LECIE, pending: CAN_ESR.LEC2, priority: ITC_SPR3.VECT9SPR +#define _CAN_RQCP0_VECTOR_ 9 ///< CAN_RQCP0 interrupt vector: enable: CAN_IER.TMEIE, pending: CAN_TSR.RQCP0, priority: ITC_SPR3.VECT9SPR +#define _CAN_RQCP1_VECTOR_ 9 ///< CAN_RQCP1 interrupt vector: enable: CAN_IER.TMEIE, pending: CAN_TSR.RQCP1, priority: ITC_SPR3.VECT9SPR +#define _CAN_RQCP2_VECTOR_ 9 ///< CAN_RQCP2 interrupt vector: enable: CAN_IER.TMEIE, pending: CAN_TSR.RQCP2, priority: ITC_SPR3.VECT9SPR +#define _CAN_WKUI_VECTOR_ 9 ///< CAN_WKUI interrupt vector: enable: CAN_IER.WKUIE, pending: CAN_MSR.WKUI, priority: ITC_SPR3.VECT9SPR +#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR +#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR +#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR +#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR +#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR +#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR +#define _TIM1_CAPCOM_BIF_VECTOR_ 11 ///< TIM1_CAPCOM_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_TIF_VECTOR_ 11 ///< TIM1_CAPCOM_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR +#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR +#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR +#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR +#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR +#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR +#define _TIM3_OVR_UIF_VECTOR_ 15 ///< TIM3_OVR_UIF interrupt vector: enable: TIM3_IER.UIE, pending: TIM3_SR1.UIF, priority: ITC_SPR4.VECT15SPR +#define _TIM3_CAPCOM_CC1IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC1IF interrupt vector: enable: TIM3_IER.CC1IE, pending: TIM3_SR1.CC1IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC2IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC2IF interrupt vector: enable: TIM3_IER.CC2IE, pending: TIM3_SR1.CC2IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_CC3IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC3IF interrupt vector: enable: TIM3_IER.CC3IE, pending: TIM3_SR1.CC3IF, priority: ITC_SPR5.VECT16SPR +#define _TIM3_CAPCOM_TIF_VECTOR_ 16 ///< TIM3_CAPCOM_TIF interrupt vector: enable: TIM3_IER.TIE, pending: TIM3_SR1.TIF, priority: ITC_SPR5.VECT16SPR +#define _UART1_T_TC_VECTOR_ 17 ///< UART1_T_TC interrupt vector: enable: UART1_CR2.TCIEN, pending: UART1_SR.TC, priority: ITC_SPR5.VECT17SPR +#define _UART1_T_TXE_VECTOR_ 17 ///< UART1_T_TXE interrupt vector: enable: UART1_CR2.TIEN, pending: UART1_SR.TXE, priority: ITC_SPR5.VECT17SPR +#define _UART1_R_IDLE_VECTOR_ 18 ///< UART1_R_IDLE interrupt vector: enable: UART1_CR2.ILIEN, pending: UART1_SR.IDLE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_LBDF_VECTOR_ 18 ///< UART1_R_LBDF interrupt vector: enable: UART1_CR4.LBDIEN, pending: UART1_CR4.LBDF, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_OR_VECTOR_ 18 ///< UART1_R_OR interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.OR_LHE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_PE_VECTOR_ 18 ///< UART1_R_PE interrupt vector: enable: UART1_CR1.PIEN, pending: UART1_SR.PE, priority: ITC_SPR5.VECT18SPR +#define _UART1_R_RXNE_VECTOR_ 18 ///< UART1_R_RXNE interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.RXNE, priority: ITC_SPR5.VECT18SPR +#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR +#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR +#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR +#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR +#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR +#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR +#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR +#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR +#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR +#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR +#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR +#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR +#define _UART3_T_TC_VECTOR_ 20 ///< UART3_T_TC interrupt vector: enable: UART3_CR2.TCIEN, pending: UART3_SR.TC, priority: ITC_SPR6.VECT20SPR +#define _UART3_T_TXE_VECTOR_ 20 ///< UART3_T_TXE interrupt vector: enable: UART3_CR2.TIEN, pending: UART3_SR.TXE, priority: ITC_SPR6.VECT20SPR +#define _UART3_R_IDLE_VECTOR_ 21 ///< UART3_R_IDLE interrupt vector: enable: UART3_CR2.ILIEN, pending: UART3_SR.IDLE, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_LBDF_VECTOR_ 21 ///< UART3_R_LBDF interrupt vector: enable: UART3_CR4.LBDIEN, pending: UART3_CR4.LBDF, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_LHDF_VECTOR_ 21 ///< UART3_R_LHDF interrupt vector: enable: UART3_CR6.LHDIEN, pending: UART3_CR6.LHDF, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_OR_VECTOR_ 21 ///< UART3_R_OR interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.OR, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_PE_VECTOR_ 21 ///< UART3_R_PE interrupt vector: enable: UART3_CR1.PIEN, pending: UART3_SR.PE, priority: ITC_SPR6.VECT21SPR +#define _UART3_R_RXNE_VECTOR_ 21 ///< UART3_R_RXNE interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.RXNE, priority: ITC_SPR6.VECT21SPR +#define _ADC2_AWDG_VECTOR_ 22 ///< ADC2_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR +#define _ADC2_EOC_VECTOR_ 22 ///< ADC2_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR +#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR +#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR +#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR + + +/*------------------------------------------------------------------------- + DEFINITION OF STM8 PERIPHERAL REGISTERS +-------------------------------------------------------------------------*/ + +//------------------------ +// Module ADC2 +//------------------------ + +/** struct containing ADC2 module registers */ +typedef struct { + + /** ADC control/status register (CSR at 0x5400) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS CH : 4; // bits 0-3 + BITS AWDIE : 1; // bit 4 + BITS EOCIE : 1; // bit 5 + BITS AWD : 1; // bit 6 + BITS EOC : 1; // bit 7 + }; // CSR bitfield + + /// register _ADC2_CSR reset value + #define sfr_ADC2_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + + + /** ADC configuration register 1 (CR1 at 0x5401) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS ADON : 1; // bit 0 + BITS CONT : 1; // bit 1 + BITS : 2; // 2 bits + BITS SPSEL : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR1 bitfield + + /// register _ADC2_CR1 reset value + #define sfr_ADC2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** ADC configuration register 2 (CR2 at 0x5402) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS : 1; // 1 bit + BITS SCAN : 1; // bit 1 + BITS : 1; // 1 bit + BITS ALIGN : 1; // bit 3 + BITS EXTSEL : 2; // bits 4-5 + BITS EXTTRIG : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _ADC2_CR2 reset value + #define sfr_ADC2_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** ADC configuration register 3 (CR3 at 0x5403) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 6; // 6 bits + BITS OVR : 1; // bit 6 + BITS DBUF : 1; // bit 7 + }; // CR3 bitfield + + /// register _ADC2_CR3 reset value + #define sfr_ADC2_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** ADC data register high (DRH at 0x5404) */ + union { + + /// bytewise access to DRH + uint8_t byte; + + /// bitwise access to register DRH + struct { + BITS DH : 8; // bits 0-7 + }; // DRH bitfield + + /// register _ADC2_DRH reset value + #define sfr_ADC2_DRH_RESET_VALUE ((uint8_t) 0x00) + + } DRH; + + + /** ADC data register low (DRL at 0x5405) */ + union { + + /// bytewise access to DRL + uint8_t byte; + + /// bitwise access to register DRL + struct { + BITS DL : 8; // bits 0-7 + }; // DRL bitfield + + /// register _ADC2_DRL reset value + #define sfr_ADC2_DRL_RESET_VALUE ((uint8_t) 0x00) + + } DRL; + + + /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ + union { + + /// bytewise access to TDRH + uint8_t byte; + + /// bitwise access to register TDRH + struct { + BITS TD : 8; // bits 0-7 + }; // TDRH bitfield + + /// register _ADC2_TDRH reset value + #define sfr_ADC2_TDRH_RESET_VALUE ((uint8_t) 0x00) + + } TDRH; + + + /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ + union { + + /// bytewise access to TDRL + uint8_t byte; + + /// bitwise access to register TDRL + struct { + BITS TL : 8; // bits 0-7 + }; // TDRL bitfield + + /// register _ADC2_TDRL reset value + #define sfr_ADC2_TDRL_RESET_VALUE ((uint8_t) 0x00) + + } TDRL; + +} ADC2_t; + +/// access to ADC2 SFR registers +#define sfr_ADC2 (*((ADC2_t*) 0x5400)) + + +//------------------------ +// Module AWU +//------------------------ + +/** struct containing AWU module registers */ +typedef struct { + + /** AWU control/status register 1 (CSR1 at 0x50f0) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// bitwise access to register CSR1 + struct { + BITS MSR : 1; // bit 0 + BITS : 3; // 3 bits + BITS AWUEN : 1; // bit 4 + BITS AWUF : 1; // bit 5 + BITS : 2; // 2 bits + }; // CSR1 bitfield + + /// register _AWU_CSR1 reset value + #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) + + } CSR1; + + + /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ + union { + + /// bytewise access to APR + uint8_t byte; + + /// bitwise access to register APR + struct { + BITS APR : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // APR bitfield + + /// register _AWU_APR reset value + #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) + + } APR; + + + /** AWU timebase selection register (TBR at 0x50f2) */ + union { + + /// bytewise access to TBR + uint8_t byte; + + /// bitwise access to register TBR + struct { + BITS AWUTB : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // TBR bitfield + + /// register _AWU_TBR reset value + #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) + + } TBR; + +} AWU_t; + +/// access to AWU SFR registers +#define sfr_AWU (*((AWU_t*) 0x50f0)) + + +//------------------------ +// Module BEEP +//------------------------ + +/** struct containing BEEP module registers */ +typedef struct { + + /** BEEP control/status register (CSR at 0x50f3) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// bitwise access to register CSR + struct { + BITS BEEPDIV : 5; // bits 0-4 + BITS BEEPEN : 1; // bit 5 + BITS BEEPSEL : 2; // bits 6-7 + }; // CSR bitfield + + /// register _BEEP_CSR reset value + #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) + + } CSR; + +} BEEP_t; + +/// access to BEEP SFR registers +#define sfr_BEEP (*((BEEP_t*) 0x50f3)) + + +//------------------------ +// Module CLK +//------------------------ + +/** struct containing CLK module registers */ +typedef struct { + + /** Internal clock control register (ICKR at 0x50c0) */ + union { + + /// bytewise access to ICKR + uint8_t byte; + + /// bitwise access to register ICKR + struct { + BITS HSIEN : 1; // bit 0 + BITS HSIRDY : 1; // bit 1 + BITS FHW : 1; // bit 2 + BITS LSIEN : 1; // bit 3 + BITS LSIRDY : 1; // bit 4 + BITS REGAH : 1; // bit 5 + BITS : 2; // 2 bits + }; // ICKR bitfield + + /// register _CLK_ICKR reset value + #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) + + } ICKR; + + + /** External clock control register (ECKR at 0x50c1) */ + union { + + /// bytewise access to ECKR + uint8_t byte; + + /// bitwise access to register ECKR + struct { + BITS HSEEN : 1; // bit 0 + BITS HSERDY : 1; // bit 1 + BITS : 6; // 6 bits + }; // ECKR bitfield + + /// register _CLK_ECKR reset value + #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) + + } ECKR; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** Clock master status register (CMSR at 0x50c3) */ + union { + + /// bytewise access to CMSR + uint8_t byte; + + /// bitwise access to register CMSR + struct { + BITS CKM : 8; // bits 0-7 + }; // CMSR bitfield + + /// register _CLK_CMSR reset value + #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) + + } CMSR; + + + /** Clock master switch register (SWR at 0x50c4) */ + union { + + /// bytewise access to SWR + uint8_t byte; + + /// bitwise access to register SWR + struct { + BITS SWI : 8; // bits 0-7 + }; // SWR bitfield + + /// register _CLK_SWR reset value + #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) + + } SWR; + + + /** Clock switch control register (SWCR at 0x50c5) */ + union { + + /// bytewise access to SWCR + uint8_t byte; + + /// bitwise access to register SWCR + struct { + BITS SWBSY : 1; // bit 0 + BITS SWEN : 1; // bit 1 + BITS SWIEN : 1; // bit 2 + BITS SWIF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SWCR bitfield + + /// register _CLK_SWCR reset value + #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) + + } SWCR; + + + /** Clock divider register (CKDIVR at 0x50c6) */ + union { + + /// bytewise access to CKDIVR + uint8_t byte; + + /// bitwise access to register CKDIVR + struct { + BITS CPUDIV : 3; // bits 0-2 + BITS HSIDIV : 2; // bits 3-4 + BITS : 3; // 3 bits + }; // CKDIVR bitfield + + /// register _CLK_CKDIVR reset value + #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) + + } CKDIVR; + + + /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ + union { + + /// bytewise access to PCKENR1 + uint8_t byte; + + /// bitwise access to register PCKENR1 + struct { + BITS PCKEN : 8; // bits 0-7 + }; // PCKENR1 bitfield + + /// register _CLK_PCKENR1 reset value + #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR1; + + + /** Clock security system register (CSSR at 0x50c8) */ + union { + + /// bytewise access to CSSR + uint8_t byte; + + /// bitwise access to register CSSR + struct { + BITS CSSEN : 1; // bit 0 + BITS AUX : 1; // bit 1 + BITS CSSDIE : 1; // bit 2 + BITS CSSD : 1; // bit 3 + BITS : 4; // 4 bits + }; // CSSR bitfield + + /// register _CLK_CSSR reset value + #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) + + } CSSR; + + + /** Configurable clock control register (CCOR at 0x50c9) */ + union { + + /// bytewise access to CCOR + uint8_t byte; + + /// bitwise access to register CCOR + struct { + BITS CCOEN : 1; // bit 0 + BITS CCOSEL : 4; // bits 1-4 + BITS CCORDY : 1; // bit 5 + BITS CC0BSY : 1; // bit 6 + BITS : 1; // 1 bit + }; // CCOR bitfield + + /// register _CLK_CCOR reset value + #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) + + } CCOR; + + + /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ + union { + + /// bytewise access to PCKENR2 + uint8_t byte; + + /// bitwise access to register PCKENR2 + struct { + BITS PCKEN2 : 8; // bits 0-7 + }; // PCKENR2 bitfield + + /// register _CLK_PCKENR2 reset value + #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) + + } PCKENR2; + + + /** CAN clock control register (CANCCR at 0x50cb) */ + union { + + /// bytewise access to CANCCR + uint8_t byte; + + /// bitwise access to register CANCCR + struct { + BITS CANDIV : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // CANCCR bitfield + + /// register _CLK_CANCCR reset value + #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) + + } CANCCR; + + + /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ + union { + + /// bytewise access to HSITRIMR + uint8_t byte; + + /// bitwise access to register HSITRIMR + struct { + BITS HSITRIM : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // HSITRIMR bitfield + + /// register _CLK_HSITRIMR reset value + #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) + + } HSITRIMR; + + + /** SWIM clock control register (SWIMCCR at 0x50cd) */ + union { + + /// bytewise access to SWIMCCR + uint8_t byte; + + /// bitwise access to register SWIMCCR + struct { + BITS SWIMCLK : 1; // bit 0 + BITS : 7; // 7 bits + }; // SWIMCCR bitfield + + /// register _CLK_SWIMCCR reset value + #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) + + } SWIMCCR; + +} CLK_t; + +/// access to CLK SFR registers +#define sfr_CLK (*((CLK_t*) 0x50c0)) + + +//------------------------ +// Module CPU +//------------------------ + +/** struct containing CPU module registers */ +typedef struct { + + /** Accumulator (A at 0x7f00) */ + union { + + /// bytewise access to A + uint8_t byte; + + /// skip bitwise access to register A + + /// register _CPU_A reset value + #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) + + } A; + + + /** Program counter extended (PCE at 0x7f01) */ + union { + + /// bytewise access to PCE + uint8_t byte; + + /// skip bitwise access to register PCE + + /// register _CPU_PCE reset value + #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) + + } PCE; + + + /** Program counter high (PCH at 0x7f02) */ + union { + + /// bytewise access to PCH + uint8_t byte; + + /// skip bitwise access to register PCH + + /// register _CPU_PCH reset value + #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) + + } PCH; + + + /** Program counter low (PCL at 0x7f03) */ + union { + + /// bytewise access to PCL + uint8_t byte; + + /// skip bitwise access to register PCL + + /// register _CPU_PCL reset value + #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) + + } PCL; + + + /** X index register high (XH at 0x7f04) */ + union { + + /// bytewise access to XH + uint8_t byte; + + /// skip bitwise access to register XH + + /// register _CPU_XH reset value + #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) + + } XH; + + + /** X index register low (XL at 0x7f05) */ + union { + + /// bytewise access to XL + uint8_t byte; + + /// skip bitwise access to register XL + + /// register _CPU_XL reset value + #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) + + } XL; + + + /** Y index register high (YH at 0x7f06) */ + union { + + /// bytewise access to YH + uint8_t byte; + + /// skip bitwise access to register YH + + /// register _CPU_YH reset value + #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) + + } YH; + + + /** Y index register low (YL at 0x7f07) */ + union { + + /// bytewise access to YL + uint8_t byte; + + /// skip bitwise access to register YL + + /// register _CPU_YL reset value + #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) + + } YL; + + + /** Stack pointer high (SPH at 0x7f08) */ + union { + + /// bytewise access to SPH + uint8_t byte; + + /// skip bitwise access to register SPH + + /// register _CPU_SPH reset value + #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x17) + + } SPH; + + + /** Stack pointer low (SPL at 0x7f09) */ + union { + + /// bytewise access to SPL + uint8_t byte; + + /// skip bitwise access to register SPL + + /// register _CPU_SPL reset value + #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) + + } SPL; + + + /** Condition code register (CCR at 0x7f0a) */ + union { + + /// bytewise access to CCR + uint8_t byte; + + /// bitwise access to register CCR + struct { + BITS C : 1; // bit 0 + BITS Z : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS I0 : 1; // bit 3 + BITS H : 1; // bit 4 + BITS I1 : 1; // bit 5 + BITS : 1; // 1 bit + BITS V : 1; // bit 7 + }; // CCR bitfield + + /// register _CPU_CCR reset value + #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) + + } CCR; + + + /// Reserved register (85B) + uint8_t Reserved_1[85]; + + + /** Global configuration register (CFG_GCR at 0x7f60) */ + union { + + /// bytewise access to CFG_GCR + uint8_t byte; + + /// bitwise access to register CFG_GCR + struct { + BITS SWO : 1; // bit 0 + BITS AL : 1; // bit 1 + BITS : 6; // 6 bits + }; // CFG_GCR bitfield + + /// register _CPU_CFG_GCR reset value + #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) + + } CFG_GCR; + +} CPU_t; + +/// access to CPU SFR registers +#define sfr_CPU (*((CPU_t*) 0x7f00)) + + +//------------------------ +// Module DM +//------------------------ + +/** struct containing DM module registers */ +typedef struct { + + /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ + union { + + /// bytewise access to BK1RE + uint8_t byte; + + /// skip bitwise access to register BK1RE + + /// register _DM_BK1RE reset value + #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RE; + + + /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ + union { + + /// bytewise access to BK1RH + uint8_t byte; + + /// skip bitwise access to register BK1RH + + /// register _DM_BK1RH reset value + #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RH; + + + /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ + union { + + /// bytewise access to BK1RL + uint8_t byte; + + /// skip bitwise access to register BK1RL + + /// register _DM_BK1RL reset value + #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK1RL; + + + /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ + union { + + /// bytewise access to BK2RE + uint8_t byte; + + /// skip bitwise access to register BK2RE + + /// register _DM_BK2RE reset value + #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RE; + + + /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ + union { + + /// bytewise access to BK2RH + uint8_t byte; + + /// skip bitwise access to register BK2RH + + /// register _DM_BK2RH reset value + #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RH; + + + /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ + union { + + /// bytewise access to BK2RL + uint8_t byte; + + /// skip bitwise access to register BK2RL + + /// register _DM_BK2RL reset value + #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) + + } BK2RL; + + + /** DM debug module control register 1 (CR1 at 0x7f96) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// skip bitwise access to register CR1 + + /// register _DM_CR1 reset value + #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** DM debug module control register 2 (CR2 at 0x7f97) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// skip bitwise access to register CR2 + + /// register _DM_CR2 reset value + #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ + union { + + /// bytewise access to CSR1 + uint8_t byte; + + /// skip bitwise access to register CSR1 + + /// register _DM_CSR1 reset value + #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) + + } CSR1; + + + /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ + union { + + /// bytewise access to CSR2 + uint8_t byte; + + /// skip bitwise access to register CSR2 + + /// register _DM_CSR2 reset value + #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) + + } CSR2; + + + /** DM enable function register (ENFCTR at 0x7f9a) */ + union { + + /// bytewise access to ENFCTR + uint8_t byte; + + /// skip bitwise access to register ENFCTR + + /// register _DM_ENFCTR reset value + #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) + + } ENFCTR; + +} DM_t; + +/// access to DM SFR registers +#define sfr_DM (*((DM_t*) 0x7f90)) + + +//------------------------ +// Module FLASH +//------------------------ + +/** struct containing FLASH module registers */ +typedef struct { + + /** Flash control register 1 (CR1 at 0x505a) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS FIX : 1; // bit 0 + BITS IE : 1; // bit 1 + BITS AHALT : 1; // bit 2 + BITS HALT : 1; // bit 3 + BITS : 4; // 4 bits + }; // CR1 bitfield + + /// register _FLASH_CR1 reset value + #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Flash control register 2 (CR2 at 0x505b) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS FPRG : 1; // bit 4 + BITS ERASE : 1; // bit 5 + BITS WPRG : 1; // bit 6 + BITS OPT : 1; // bit 7 + }; // CR2 bitfield + + /// register _FLASH_CR2 reset value + #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** Flash complementary control register 2 (NCR2 at 0x505c) */ + union { + + /// bytewise access to NCR2 + uint8_t byte; + + /// bitwise access to register NCR2 + struct { + BITS NPRG : 1; // bit 0 + BITS : 3; // 3 bits + BITS NFPRG : 1; // bit 4 + BITS NERASE : 1; // bit 5 + BITS NWPRG : 1; // bit 6 + BITS NOPT : 1; // bit 7 + }; // NCR2 bitfield + + /// register _FLASH_NCR2 reset value + #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) + + } NCR2; + + + /** Flash protection register (FPR at 0x505d) */ + union { + + /// bytewise access to FPR + uint8_t byte; + + /// bitwise access to register FPR + struct { + BITS WPB0 : 1; // bit 0 + BITS WPB1 : 1; // bit 1 + BITS WPB2 : 1; // bit 2 + BITS WPB3 : 1; // bit 3 + BITS WPB4 : 1; // bit 4 + BITS WPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // FPR bitfield + + /// register _FLASH_FPR reset value + #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) + + } FPR; + + + /** Flash complementary protection register (NFPR at 0x505e) */ + union { + + /// bytewise access to NFPR + uint8_t byte; + + /// bitwise access to register NFPR + struct { + BITS NWPB0 : 1; // bit 0 + BITS NWPB1 : 1; // bit 1 + BITS NWPB2 : 1; // bit 2 + BITS NWPB3 : 1; // bit 3 + BITS NWPB4 : 1; // bit 4 + BITS NWPB5 : 1; // bit 5 + BITS : 2; // 2 bits + }; // NFPR bitfield + + /// register _FLASH_NFPR reset value + #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) + + } NFPR; + + + /** Flash in-application programming status register (IAPSR at 0x505f) */ + union { + + /// bytewise access to IAPSR + uint8_t byte; + + /// bitwise access to register IAPSR + struct { + BITS WR_PG_DIS : 1; // bit 0 + BITS PUL : 1; // bit 1 + BITS EOP : 1; // bit 2 + BITS DUL : 1; // bit 3 + BITS : 2; // 2 bits + BITS HVOFF : 1; // bit 6 + BITS : 1; // 1 bit + }; // IAPSR bitfield + + /// register _FLASH_IAPSR reset value + #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) + + } IAPSR; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash Program memory unprotection register (PUKR at 0x5062) */ + union { + + /// bytewise access to PUKR + uint8_t byte; + + /// bitwise access to register PUKR + struct { + BITS MASS_PRG : 8; // bits 0-7 + }; // PUKR bitfield + + /// register _FLASH_PUKR reset value + #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) + + } PUKR; + + + /// Reserved register (1B) + uint8_t Reserved_2[1]; + + + /** Data EEPROM unprotection register (DUKR at 0x5064) */ + union { + + /// bytewise access to DUKR + uint8_t byte; + + /// bitwise access to register DUKR + struct { + BITS MASS_DATA : 8; // bits 0-7 + }; // DUKR bitfield + + /// register _FLASH_DUKR reset value + #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) + + } DUKR; + +} FLASH_t; + +/// access to FLASH SFR registers +#define sfr_FLASH (*((FLASH_t*) 0x505a)) + + +//------------------------ +// Module I2C +//------------------------ + +/** struct containing I2C module registers */ +typedef struct { + + /** I2C control register 1 (CR1 at 0x5210) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PE : 1; // bit 0 + BITS : 5; // 5 bits + BITS ENGC : 1; // bit 6 + BITS NOSTRETCH : 1; // bit 7 + }; // CR1 bitfield + + /// register _I2C_CR1 reset value + #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** I2C control register 2 (CR2 at 0x5211) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS START : 1; // bit 0 + BITS STOP : 1; // bit 1 + BITS ACK : 1; // bit 2 + BITS POS : 1; // bit 3 + BITS : 3; // 3 bits + BITS SWRST : 1; // bit 7 + }; // CR2 bitfield + + /// register _I2C_CR2 reset value + #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** I2C frequency register (FREQR at 0x5212) */ + union { + + /// bytewise access to FREQR + uint8_t byte; + + /// bitwise access to register FREQR + struct { + BITS FREQ : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // FREQR bitfield + + /// register _I2C_FREQR reset value + #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) + + } FREQR; + + + /** I2C own address register low (OARL at 0x5213) */ + union { + + /// bytewise access to OARL + uint8_t byte; + + /// bitwise access to register OARL + struct { + BITS ADD0 : 1; // bit 0 + BITS ADD : 7; // bits 1-7 + }; // OARL bitfield + + /// register _I2C_OARL reset value + #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) + + } OARL; + + + /** I2C own address register high (OARH at 0x5214) */ + union { + + /// bytewise access to OARH + uint8_t byte; + + /// bitwise access to register OARH + struct { + BITS : 1; // 1 bit + BITS ADD : 2; // bits 1-2 + BITS : 3; // 3 bits + BITS ADDCONF : 1; // bit 6 + BITS ADDMODE : 1; // bit 7 + }; // OARH bitfield + + /// register _I2C_OARH reset value + #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) + + } OARH; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** I2C data register (DR at 0x5216) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _I2C_DR reset value + #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** I2C status register 1 (SR1 at 0x5217) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS SB : 1; // bit 0 + BITS ADDR : 1; // bit 1 + BITS BTF : 1; // bit 2 + BITS ADD10 : 1; // bit 3 + BITS STOPF : 1; // bit 4 + BITS : 1; // 1 bit + BITS RXNE : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR1 bitfield + + /// register _I2C_SR1 reset value + #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** I2C status register 2 (SR2 at 0x5218) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS BERR : 1; // bit 0 + BITS ARLO : 1; // bit 1 + BITS AF : 1; // bit 2 + BITS OVR : 1; // bit 3 + BITS : 1; // 1 bit + BITS WUFH : 1; // bit 5 + BITS : 2; // 2 bits + }; // SR2 bitfield + + /// register _I2C_SR2 reset value + #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** I2C status register 3 (SR3 at 0x5219) */ + union { + + /// bytewise access to SR3 + uint8_t byte; + + /// bitwise access to register SR3 + struct { + BITS MSL : 1; // bit 0 + BITS BUSY : 1; // bit 1 + BITS TRA : 1; // bit 2 + BITS : 1; // 1 bit + BITS GENCALL : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR3 bitfield + + /// register _I2C_SR3 reset value + #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) + + } SR3; + + + /** I2C interrupt control register (ITR at 0x521a) */ + union { + + /// bytewise access to ITR + uint8_t byte; + + /// bitwise access to register ITR + struct { + BITS ITERREN : 1; // bit 0 + BITS ITEVTEN : 1; // bit 1 + BITS ITBUFEN : 1; // bit 2 + BITS : 5; // 5 bits + }; // ITR bitfield + + /// register _I2C_ITR reset value + #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) + + } ITR; + + + /** I2C clock control register low (CCRL at 0x521b) */ + union { + + /// bytewise access to CCRL + uint8_t byte; + + /// bitwise access to register CCRL + struct { + BITS CCR : 8; // bits 0-7 + }; // CCRL bitfield + + /// register _I2C_CCRL reset value + #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) + + } CCRL; + + + /** I2C clock control register high (CCRH at 0x521c) */ + union { + + /// bytewise access to CCRH + uint8_t byte; + + /// bitwise access to register CCRH + struct { + BITS CCR : 4; // bits 0-3 + BITS : 2; // 2 bits + BITS DUTY : 1; // bit 6 + BITS F_S : 1; // bit 7 + }; // CCRH bitfield + + /// register _I2C_CCRH reset value + #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) + + } CCRH; + + + /** I2C TRISE register (TRISER at 0x521d) */ + union { + + /// bytewise access to TRISER + uint8_t byte; + + /// bitwise access to register TRISER + struct { + BITS TRISE : 6; // bits 0-5 + BITS : 2; // 2 bits + }; // TRISER bitfield + + /// register _I2C_TRISER reset value + #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) + + } TRISER; + + + /** I2C packet error checking register (PECR at 0x521e) */ + union { + + /// bytewise access to PECR + uint8_t byte; + + /// skip bitwise access to register PECR + + /// register _I2C_PECR reset value + #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) + + } PECR; + +} I2C_t; + +/// access to I2C SFR registers +#define sfr_I2C (*((I2C_t*) 0x5210)) + + +//------------------------ +// Module ITC +//------------------------ + +/** struct containing ITC module registers */ +typedef struct { + + /** External interrupt control register 1 (CR1 at 0x50a0) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PAIS : 2; // bits 0-1 + BITS PBIS : 2; // bits 2-3 + BITS PCIS : 2; // bits 4-5 + BITS PDIS : 2; // bits 6-7 + }; // CR1 bitfield + + /// register _ITC_CR1 reset value + #define sfr_ITC_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** External interrupt control register 2 (CR2 at 0x50a1) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS PEIS : 2; // bits 0-1 + BITS TLIS : 1; // bit 2 + BITS : 5; // 5 bits + }; // CR2 bitfield + + /// register _ITC_CR2 reset value + #define sfr_ITC_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /// Reserved register (11982B) + uint8_t Reserved_1[11982]; + + + /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ + union { + + /// bytewise access to SPR1 + uint8_t byte; + + /// bitwise access to register SPR1 + struct { + BITS VECT0SPR : 2; // bits 0-1 + BITS VECT1SPR : 2; // bits 2-3 + BITS VECT2SPR : 2; // bits 4-5 + BITS VECT3SPR : 2; // bits 6-7 + }; // SPR1 bitfield + + /// register _ITC_SPR1 reset value + #define sfr_ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF) + + } SPR1; + + + /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ + union { + + /// bytewise access to SPR2 + uint8_t byte; + + /// bitwise access to register SPR2 + struct { + BITS VECT4SPR : 2; // bits 0-1 + BITS VECT5SPR : 2; // bits 2-3 + BITS VECT6SPR : 2; // bits 4-5 + BITS VECT7SPR : 2; // bits 6-7 + }; // SPR2 bitfield + + /// register _ITC_SPR2 reset value + #define sfr_ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF) + + } SPR2; + + + /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ + union { + + /// bytewise access to SPR3 + uint8_t byte; + + /// bitwise access to register SPR3 + struct { + BITS VECT8SPR : 2; // bits 0-1 + BITS VECT9SPR : 2; // bits 2-3 + BITS VECT10SPR : 2; // bits 4-5 + BITS VECT11SPR : 2; // bits 6-7 + }; // SPR3 bitfield + + /// register _ITC_SPR3 reset value + #define sfr_ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF) + + } SPR3; + + + /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ + union { + + /// bytewise access to SPR4 + uint8_t byte; + + /// bitwise access to register SPR4 + struct { + BITS VECT12SPR : 2; // bits 0-1 + BITS VECT13SPR : 2; // bits 2-3 + BITS VECT14SPR : 2; // bits 4-5 + BITS VECT15SPR : 2; // bits 6-7 + }; // SPR4 bitfield + + /// register _ITC_SPR4 reset value + #define sfr_ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF) + + } SPR4; + + + /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ + union { + + /// bytewise access to SPR5 + uint8_t byte; + + /// bitwise access to register SPR5 + struct { + BITS VECT16SPR : 2; // bits 0-1 + BITS VECT17SPR : 2; // bits 2-3 + BITS VECT18SPR : 2; // bits 4-5 + BITS VECT19SPR : 2; // bits 6-7 + }; // SPR5 bitfield + + /// register _ITC_SPR5 reset value + #define sfr_ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF) + + } SPR5; + + + /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ + union { + + /// bytewise access to SPR6 + uint8_t byte; + + /// bitwise access to register SPR6 + struct { + BITS VECT20SPR : 2; // bits 0-1 + BITS VECT21SPR : 2; // bits 2-3 + BITS VECT22SPR : 2; // bits 4-5 + BITS VECT23SPR : 2; // bits 6-7 + }; // SPR6 bitfield + + /// register _ITC_SPR6 reset value + #define sfr_ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF) + + } SPR6; + + + /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ + union { + + /// bytewise access to SPR7 + uint8_t byte; + + /// bitwise access to register SPR7 + struct { + BITS VECT24SPR : 2; // bits 0-1 + BITS VECT25SPR : 2; // bits 2-3 + BITS VECT26SPR : 2; // bits 4-5 + BITS VECT27SPR : 2; // bits 6-7 + }; // SPR7 bitfield + + /// register _ITC_SPR7 reset value + #define sfr_ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF) + + } SPR7; + + + /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ + union { + + /// bytewise access to SPR8 + uint8_t byte; + + /// bitwise access to register SPR8 + struct { + BITS VECT28SPR : 2; // bits 0-1 + BITS VECT29SPR : 2; // bits 2-3 + BITS : 4; // 4 bits + }; // SPR8 bitfield + + /// register _ITC_SPR8 reset value + #define sfr_ITC_SPR8_RESET_VALUE ((uint8_t) 0xFF) + + } SPR8; + +} ITC_t; + +/// access to ITC SFR registers +#define sfr_ITC (*((ITC_t*) 0x50a0)) + + +//------------------------ +// Module IWDG +//------------------------ + +/** struct containing IWDG module registers */ +typedef struct { + + /** IWDG key register (KR at 0x50e0) */ + union { + + /// bytewise access to KR + uint8_t byte; + + /// bitwise access to register KR + struct { + BITS KEY : 8; // bits 0-7 + }; // KR bitfield + + /// register _IWDG_KR reset value + #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) + + } KR; + + + /** IWDG prescaler register (PR at 0x50e1) */ + union { + + /// bytewise access to PR + uint8_t byte; + + /// bitwise access to register PR + struct { + BITS PR : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PR bitfield + + /// register _IWDG_PR reset value + #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) + + } PR; + + + /** IWDG reload register (RLR at 0x50e2) */ + union { + + /// bytewise access to RLR + uint8_t byte; + + /// bitwise access to register RLR + struct { + BITS RL : 8; // bits 0-7 + }; // RLR bitfield + + /// register _IWDG_RLR reset value + #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) + + } RLR; + +} IWDG_t; + +/// access to IWDG SFR registers +#define sfr_IWDG (*((IWDG_t*) 0x50e0)) + + +//------------------------ +// Module OPT +//------------------------ + +/** struct containing OPT module registers */ +typedef struct { + + /** Read-out protection (ROP) (OPT0 at 0x4800) */ + union { + + /// bytewise access to OPT0 + uint8_t byte; + + /// skip bitwise access to register OPT0 + + /// register _OPT_OPT0 reset value + #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) + + } OPT0; + + + /** User boot code (UBC) (OPT1 at 0x4801) */ + union { + + /// bytewise access to OPT1 + uint8_t byte; + + /// skip bitwise access to register OPT1 + + /// register _OPT_OPT1 reset value + #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) + + } OPT1; + + + /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ + union { + + /// bytewise access to NOPT1 + uint8_t byte; + + /// skip bitwise access to register NOPT1 + + /// register _OPT_NOPT1 reset value + #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT1; + + + /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ + union { + + /// bytewise access to OPT2 + uint8_t byte; + + /// skip bitwise access to register OPT2 + + /// register _OPT_OPT2 reset value + #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) + + } OPT2; + + + /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ + union { + + /// bytewise access to NOPT2 + uint8_t byte; + + /// skip bitwise access to register NOPT2 + + /// register _OPT_NOPT2 reset value + #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT2; + + + /** Misc. option (OPT3 at 0x4805) */ + union { + + /// bytewise access to OPT3 + uint8_t byte; + + /// skip bitwise access to register OPT3 + + /// register _OPT_OPT3 reset value + #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) + + } OPT3; + + + /** Misc. option (complementary byte) (NOPT3 at 0x4806) */ + union { + + /// bytewise access to NOPT3 + uint8_t byte; + + /// skip bitwise access to register NOPT3 + + /// register _OPT_NOPT3 reset value + #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT3; + + + /** Clock option (OPT4 at 0x4807) */ + union { + + /// bytewise access to OPT4 + uint8_t byte; + + /// skip bitwise access to register OPT4 + + /// register _OPT_OPT4 reset value + #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) + + } OPT4; + + + /** Clock option (complementary byte) (NOPT4 at 0x4808) */ + union { + + /// bytewise access to NOPT4 + uint8_t byte; + + /// skip bitwise access to register NOPT4 + + /// register _OPT_NOPT4 reset value + #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT4; + + + /** HSE clock startup (OPT5 at 0x4809) */ + union { + + /// bytewise access to OPT5 + uint8_t byte; + + /// skip bitwise access to register OPT5 + + /// register _OPT_OPT5 reset value + #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) + + } OPT5; + + + /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ + union { + + /// bytewise access to NOPT5 + uint8_t byte; + + /// skip bitwise access to register NOPT5 + + /// register _OPT_NOPT5 reset value + #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT5; + + + /// Reserved register (2B) + uint8_t Reserved_1[2]; + + + /** Flash wait states (OPT7 at 0x480d) */ + union { + + /// bytewise access to OPT7 + uint8_t byte; + + /// skip bitwise access to register OPT7 + + /// register _OPT_OPT7 reset value + #define sfr_OPT_OPT7_RESET_VALUE ((uint8_t) 0x00) + + } OPT7; + + + /** Flash wait states (complementary byte) (NOPT7 at 0x480e) */ + union { + + /// bytewise access to NOPT7 + uint8_t byte; + + /// skip bitwise access to register NOPT7 + + /// register _OPT_NOPT7 reset value + #define sfr_OPT_NOPT7_RESET_VALUE ((uint8_t) 0xFF) + + } NOPT7; + + + /// Reserved register (111B) + uint8_t Reserved_2[111]; + + + /** Bootloader (OPTBL at 0x487e) */ + union { + + /// bytewise access to OPTBL + uint8_t byte; + + /// skip bitwise access to register OPTBL + + /// register _OPT_OPTBL reset value + #define sfr_OPT_OPTBL_RESET_VALUE ((uint8_t) 0x00) + + } OPTBL; + + + /** Bootloader (complementary byte) (NOPTBL at 0x487f) */ + union { + + /// bytewise access to NOPTBL + uint8_t byte; + + /// skip bitwise access to register NOPTBL + + /// register _OPT_NOPTBL reset value + #define sfr_OPT_NOPTBL_RESET_VALUE ((uint8_t) 0xFF) + + } NOPTBL; + +} OPT_t; + +/// access to OPT SFR registers +#define sfr_OPT (*((OPT_t*) 0x4800)) + + +//------------------------ +// Module PORT +//------------------------ + +/** struct containing PORTA module registers */ +typedef struct { + + /** Port A data output latch register (ODR at 0x5000) */ + union { + + /// bytewise access to ODR + uint8_t byte; + + /// bitwise access to register ODR + struct { + BITS ODR0 : 1; // bit 0 + BITS ODR1 : 1; // bit 1 + BITS ODR2 : 1; // bit 2 + BITS ODR3 : 1; // bit 3 + BITS ODR4 : 1; // bit 4 + BITS ODR5 : 1; // bit 5 + BITS ODR6 : 1; // bit 6 + BITS ODR7 : 1; // bit 7 + }; // ODR bitfield + + /// register _PORT_ODR reset value + #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) + + } ODR; + + + /** Port A input pin value register (IDR at 0x5001) */ + union { + + /// bytewise access to IDR + uint8_t byte; + + /// bitwise access to register IDR + struct { + BITS IDR0 : 1; // bit 0 + BITS IDR1 : 1; // bit 1 + BITS IDR2 : 1; // bit 2 + BITS IDR3 : 1; // bit 3 + BITS IDR4 : 1; // bit 4 + BITS IDR5 : 1; // bit 5 + BITS IDR6 : 1; // bit 6 + BITS IDR7 : 1; // bit 7 + }; // IDR bitfield + + /// register _PORT_IDR reset value + #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) + + } IDR; + + + /** Port A data direction register (DDR at 0x5002) */ + union { + + /// bytewise access to DDR + uint8_t byte; + + /// bitwise access to register DDR + struct { + BITS DDR0 : 1; // bit 0 + BITS DDR1 : 1; // bit 1 + BITS DDR2 : 1; // bit 2 + BITS DDR3 : 1; // bit 3 + BITS DDR4 : 1; // bit 4 + BITS DDR5 : 1; // bit 5 + BITS DDR6 : 1; // bit 6 + BITS DDR7 : 1; // bit 7 + }; // DDR bitfield + + /// register _PORT_DDR reset value + #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) + + } DDR; + + + /** Port A control register 1 (CR1 at 0x5003) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS C10 : 1; // bit 0 + BITS C11 : 1; // bit 1 + BITS C12 : 1; // bit 2 + BITS C13 : 1; // bit 3 + BITS C14 : 1; // bit 4 + BITS C15 : 1; // bit 5 + BITS C16 : 1; // bit 6 + BITS C17 : 1; // bit 7 + }; // CR1 bitfield + + /// register _PORT_CR1 reset value + #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** Port A control register 2 (CR2 at 0x5004) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS C20 : 1; // bit 0 + BITS C21 : 1; // bit 1 + BITS C22 : 1; // bit 2 + BITS C23 : 1; // bit 3 + BITS C24 : 1; // bit 4 + BITS C25 : 1; // bit 5 + BITS C26 : 1; // bit 6 + BITS C27 : 1; // bit 7 + }; // CR2 bitfield + + /// register _PORT_CR2 reset value + #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + +} PORT_t; + +/// access to PORTA SFR registers +#define sfr_PORTA (*((PORT_t*) 0x5000)) + + +/// access to PORTB SFR registers +#define sfr_PORTB (*((PORT_t*) 0x5005)) + + +/// access to PORTC SFR registers +#define sfr_PORTC (*((PORT_t*) 0x500a)) + + +/// access to PORTD SFR registers +#define sfr_PORTD (*((PORT_t*) 0x500f)) + + +/// access to PORTE SFR registers +#define sfr_PORTE (*((PORT_t*) 0x5014)) + + +/// access to PORTF SFR registers +#define sfr_PORTF (*((PORT_t*) 0x5019)) + + +/// access to PORTG SFR registers +#define sfr_PORTG (*((PORT_t*) 0x501e)) + + +/// access to PORTH SFR registers +#define sfr_PORTH (*((PORT_t*) 0x5023)) + + +/// access to PORTI SFR registers +#define sfr_PORTI (*((PORT_t*) 0x5028)) + + +//------------------------ +// Module RST +//------------------------ + +/** struct containing RST module registers */ +typedef struct { + + /** Reset status register (SR at 0x50b3) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS WWDGF : 1; // bit 0 + BITS IWDGF : 1; // bit 1 + BITS ILLOPF : 1; // bit 2 + BITS SWIMF : 1; // bit 3 + BITS EMCF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR bitfield + + /// register _RST_SR reset value + #define sfr_RST_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + +} RST_t; + +/// access to RST SFR registers +#define sfr_RST (*((RST_t*) 0x50b3)) + + +//------------------------ +// Module SPI +//------------------------ + +/** struct containing SPI module registers */ +typedef struct { + + /** SPI control register 1 (CR1 at 0x5200) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CPHA : 1; // bit 0 + BITS CPOL : 1; // bit 1 + BITS MSTR : 1; // bit 2 + BITS BR : 3; // bits 3-5 + BITS SPE : 1; // bit 6 + BITS LSBFIRST : 1; // bit 7 + }; // CR1 bitfield + + /// register _SPI_CR1 reset value + #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** SPI control register 2 (CR2 at 0x5201) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SSI : 1; // bit 0 + BITS SSM : 1; // bit 1 + BITS RXONLY : 1; // bit 2 + BITS : 1; // 1 bit + BITS CRCNEXT : 1; // bit 4 + BITS CECEN : 1; // bit 5 + BITS BDOE : 1; // bit 6 + BITS BDM : 1; // bit 7 + }; // CR2 bitfield + + /// register _SPI_CR2 reset value + #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** SPI interrupt control register (ICR at 0x5202) */ + union { + + /// bytewise access to ICR + uint8_t byte; + + /// bitwise access to register ICR + struct { + BITS : 4; // 4 bits + BITS WKIE : 1; // bit 4 + BITS ERRIE : 1; // bit 5 + BITS RXIE : 1; // bit 6 + BITS TXIE : 1; // bit 7 + }; // ICR bitfield + + /// register _SPI_ICR reset value + #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) + + } ICR; + + + /** SPI status register (SR at 0x5203) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS RXNE : 1; // bit 0 + BITS TXE : 1; // bit 1 + BITS : 1; // 1 bit + BITS WKUP : 1; // bit 3 + BITS CRCERR : 1; // bit 4 + BITS MODF : 1; // bit 5 + BITS OVR : 1; // bit 6 + BITS BSY : 1; // bit 7 + }; // SR bitfield + + /// register _SPI_SR reset value + #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) + + } SR; + + + /** SPI data register (DR at 0x5204) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _SPI_DR reset value + #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** SPI CRC polynomial register (CRCPR at 0x5205) */ + union { + + /// bytewise access to CRCPR + uint8_t byte; + + /// bitwise access to register CRCPR + struct { + BITS CRCPOLY : 8; // bits 0-7 + }; // CRCPR bitfield + + /// register _SPI_CRCPR reset value + #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) + + } CRCPR; + + + /** SPI Rx CRC register (RXCRCR at 0x5206) */ + union { + + /// bytewise access to RXCRCR + uint8_t byte; + + /// bitwise access to register RXCRCR + struct { + BITS RXCRC : 8; // bits 0-7 + }; // RXCRCR bitfield + + /// register _SPI_RXCRCR reset value + #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } RXCRCR; + + + /** SPI Tx CRC register (TXCRCR at 0x5207) */ + union { + + /// bytewise access to TXCRCR + uint8_t byte; + + /// bitwise access to register TXCRCR + struct { + BITS TXCRC : 8; // bits 0-7 + }; // TXCRCR bitfield + + /// register _SPI_TXCRCR reset value + #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) + + } TXCRCR; + +} SPI_t; + +/// access to SPI SFR registers +#define sfr_SPI (*((SPI_t*) 0x5200)) + + +//------------------------ +// Module SWIM +//------------------------ + +/** struct containing SWIM module registers */ +typedef struct { + + /** SWIM control status register (CSR at 0x7f80) */ + union { + + /// bytewise access to CSR + uint8_t byte; + + /// skip bitwise access to register CSR + + /// register _SWIM_CSR reset value + #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) + + } CSR; + +} SWIM_t; + +/// access to SWIM SFR registers +#define sfr_SWIM (*((SWIM_t*) 0x7f80)) + + +//------------------------ +// Module TIM1 +//------------------------ + +/** struct containing TIM1 module registers */ +typedef struct { + + /** TIM1 control register 1 (CR1 at 0x5250) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS DIR : 1; // bit 4 + BITS CMS : 2; // bits 5-6 + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM1_CR1 reset value + #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM1 control register 2 (CR2 at 0x5251) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS CCPG : 1; // bit 0 + BITS : 1; // 1 bit + BITS COMS : 1; // bit 2 + BITS : 1; // 1 bit + BITS MMS : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CR2 bitfield + + /// register _TIM1_CR2 reset value + #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** TIM1 slave mode control register (SMCR at 0x5252) */ + union { + + /// bytewise access to SMCR + uint8_t byte; + + /// bitwise access to register SMCR + struct { + BITS SMS : 3; // bits 0-2 + BITS : 1; // 1 bit + BITS TS : 3; // bits 4-6 + BITS MSM : 1; // bit 7 + }; // SMCR bitfield + + /// register _TIM1_SMCR reset value + #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) + + } SMCR; + + + /** TIM1 external trigger register (ETR at 0x5253) */ + union { + + /// bytewise access to ETR + uint8_t byte; + + /// bitwise access to register ETR + struct { + BITS ETF : 4; // bits 0-3 + BITS ETPS : 2; // bits 4-5 + BITS ECE : 1; // bit 6 + BITS ETP : 1; // bit 7 + }; // ETR bitfield + + /// register _TIM1_ETR reset value + #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) + + } ETR; + + + /** TIM1 Interrupt enable register (IER at 0x5254) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS CC4IE : 1; // bit 4 + BITS COMIE : 1; // bit 5 + BITS TIE : 1; // bit 6 + BITS BIE : 1; // bit 7 + }; // IER bitfield + + /// register _TIM1_IER reset value + #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM1 status register 1 (SR1 at 0x5255) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS CC4IF : 1; // bit 4 + BITS COMIF : 1; // bit 5 + BITS TIF : 1; // bit 6 + BITS BIF : 1; // bit 7 + }; // SR1 bitfield + + /// register _TIM1_SR1 reset value + #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM1 status register 2 (SR2 at 0x5256) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS CC4OF : 1; // bit 4 + BITS : 3; // 3 bits + }; // SR2 bitfield + + /// register _TIM1_SR2 reset value + #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM1 event generation register (EGR at 0x5257) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS CC4G : 1; // bit 4 + BITS COMG : 1; // bit 5 + BITS TG : 1; // bit 6 + BITS BG : 1; // bit 7 + }; // EGR bitfield + + /// register _TIM1_EGR reset value + #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS OC1FE : 1; // bit 2 + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS OC1CE : 1; // bit 7 + }; // CCMR1 bitfield + + /// register _TIM1_CCMR1 reset value + #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS OC2FE : 1; // bit 2 + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS OC2CE : 1; // bit 7 + }; // CCMR2 bitfield + + /// register _TIM1_CCMR2 reset value + #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS OC3FE : 1; // bit 2 + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS OC3CE : 1; // bit 7 + }; // CCMR3 bitfield + + /// register _TIM1_CCMR3 reset value + #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ + union { + + /// bytewise access to CCMR4 + uint8_t byte; + + /// bitwise access to register CCMR4 + struct { + BITS CC4S : 2; // bits 0-1 + BITS OC4FE : 1; // bit 2 + BITS OC4PE : 1; // bit 3 + BITS OC4M : 3; // bits 4-6 + BITS OC4CE : 1; // bit 7 + }; // CCMR4 bitfield + + /// register _TIM1_CCMR4 reset value + #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) + + } CCMR4; + + + /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS CC1NE : 1; // bit 2 + BITS CC1NP : 1; // bit 3 + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS CC2NE : 1; // bit 6 + BITS CC2NP : 1; // bit 7 + }; // CCER1 bitfield + + /// register _TIM1_CCER1 reset value + #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS CC3NE : 1; // bit 2 + BITS CC3NP : 1; // bit 3 + BITS CC4E : 1; // bit 4 + BITS CC4P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER2 bitfield + + /// register _TIM1_CCER2 reset value + #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM1 counter high (CNTRH at 0x525e) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM1_CNTRH reset value + #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM1 counter low (CNTRL at 0x525f) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM1_CNTRL reset value + #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM1 prescaler register high (PSCRH at 0x5260) */ + union { + + /// bytewise access to PSCRH + uint8_t byte; + + /// bitwise access to register PSCRH + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRH bitfield + + /// register _TIM1_PSCRH reset value + #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) + + } PSCRH; + + + /** TIM1 prescaler register low (PSCRL at 0x5261) */ + union { + + /// bytewise access to PSCRL + uint8_t byte; + + /// bitwise access to register PSCRL + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCRL bitfield + + /// register _TIM1_PSCRL reset value + #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) + + } PSCRL; + + + /** TIM1 auto-reload register high (ARRH at 0x5262) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM1_ARRH reset value + #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM1 auto-reload register low (ARRL at 0x5263) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM1_ARRL reset value + #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM1 repetition counter register (RCR at 0x5264) */ + union { + + /// bytewise access to RCR + uint8_t byte; + + /// bitwise access to register RCR + struct { + BITS REP : 8; // bits 0-7 + }; // RCR bitfield + + /// register _TIM1_RCR reset value + #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) + + } RCR; + + + /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM1_CCR1H reset value + #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM1_CCR1L reset value + #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM1_CCR2H reset value + #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM1_CCR2L reset value + #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM1_CCR3H reset value + #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM1_CCR3L reset value + #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + + + /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ + union { + + /// bytewise access to CCR4H + uint8_t byte; + + /// bitwise access to register CCR4H + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4H bitfield + + /// register _TIM1_CCR4H reset value + #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) + + } CCR4H; + + + /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ + union { + + /// bytewise access to CCR4L + uint8_t byte; + + /// bitwise access to register CCR4L + struct { + BITS CCR4 : 8; // bits 0-7 + }; // CCR4L bitfield + + /// register _TIM1_CCR4L reset value + #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) + + } CCR4L; + + + /** TIM1 break register (BKR at 0x526d) */ + union { + + /// bytewise access to BKR + uint8_t byte; + + /// bitwise access to register BKR + struct { + BITS LOCK : 2; // bits 0-1 + BITS OSSI : 1; // bit 2 + BITS OSSR : 1; // bit 3 + BITS BKE : 1; // bit 4 + BITS BKP : 1; // bit 5 + BITS AOE : 1; // bit 6 + BITS MOE : 1; // bit 7 + }; // BKR bitfield + + /// register _TIM1_BKR reset value + #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) + + } BKR; + + + /** TIM1 dead-time register (DTR at 0x526e) */ + union { + + /// bytewise access to DTR + uint8_t byte; + + /// bitwise access to register DTR + struct { + BITS DTG : 8; // bits 0-7 + }; // DTR bitfield + + /// register _TIM1_DTR reset value + #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) + + } DTR; + + + /** TIM1 output idle state register (OISR at 0x526f) */ + union { + + /// bytewise access to OISR + uint8_t byte; + + /// bitwise access to register OISR + struct { + BITS OIS1 : 1; // bit 0 + BITS OIS1N : 1; // bit 1 + BITS OIS2 : 1; // bit 2 + BITS OIS2N : 1; // bit 3 + BITS OIS3 : 1; // bit 4 + BITS OIS3N : 1; // bit 5 + BITS OIS4 : 1; // bit 6 + BITS : 1; // 1 bit + }; // OISR bitfield + + /// register _TIM1_OISR reset value + #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) + + } OISR; + +} TIM1_t; + +/// access to TIM1 SFR registers +#define sfr_TIM1 (*((TIM1_t*) 0x5250)) + + +//------------------------ +// Module TIM2 +//------------------------ + +/** struct containing TIM2 module registers */ +typedef struct { + + /** TIM2 control register 1 (CR1 at 0x5300) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM2_CR1 reset value + #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM2 interrupt enable register (IER at 0x5301) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM2_IER reset value + #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM2 status register 1 (SR1 at 0x5302) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM2_SR1 reset value + #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM2 status register 2 (SR2 at 0x5303) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM2_SR2 reset value + #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM2 event generation register (EGR at 0x5304) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM2_EGR reset value + #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5305) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM2_CCMR1 reset value + #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5306) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM2_CCMR2 reset value + #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5307) */ + union { + + /// bytewise access to CCMR3 + uint8_t byte; + + /// bitwise access to register CCMR3 + struct { + BITS CC3S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC3PE : 1; // bit 3 + BITS OC3M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR3 bitfield + + /// register _TIM2_CCMR3 reset value + #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) + + } CCMR3; + + + /** TIM2 capture/compare enable register 1 (CCER1 at 0x5308) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM2_CCER1 reset value + #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM2 capture/compare enable register 2 (CCER2 at 0x5309) */ + union { + + /// bytewise access to CCER2 + uint8_t byte; + + /// bitwise access to register CCER2 + struct { + BITS CC3E : 1; // bit 0 + BITS CC3P : 1; // bit 1 + BITS : 6; // 6 bits + }; // CCER2 bitfield + + /// register _TIM2_CCER2 reset value + #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) + + } CCER2; + + + /** TIM2 counter high (CNTRH at 0x530a) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM2_CNTRH reset value + #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM2 counter low (CNTRL at 0x530b) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM2_CNTRL reset value + #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM2 prescaler register (PSCR at 0x530c) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM2_PSCR reset value + #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM2 auto-reload register high (ARRH at 0x530d) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM2_ARRH reset value + #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM2 auto-reload register low (ARRL at 0x530e) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM2_ARRL reset value + #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM2 capture/compare register 1 high (CCR1H at 0x530f) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM2_CCR1H reset value + #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM2 capture/compare register 1 low (CCR1L at 0x5310) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM2_CCR1L reset value + #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM2 capture/compare reg (CCR2H at 0x5311) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM2_CCR2H reset value + #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM2 capture/compare register 2 low (CCR2L at 0x5312) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM2_CCR2L reset value + #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + + + /** TIM2 capture/compare register 3 high (CCR3H at 0x5313) */ + union { + + /// bytewise access to CCR3H + uint8_t byte; + + /// bitwise access to register CCR3H + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3H bitfield + + /// register _TIM2_CCR3H reset value + #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) + + } CCR3H; + + + /** TIM2 capture/compare register 3 low (CCR3L at 0x5314) */ + union { + + /// bytewise access to CCR3L + uint8_t byte; + + /// bitwise access to register CCR3L + struct { + BITS CCR3 : 8; // bits 0-7 + }; // CCR3L bitfield + + /// register _TIM2_CCR3L reset value + #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) + + } CCR3L; + +} TIM2_t; + +/// access to TIM2 SFR registers +#define sfr_TIM2 (*((TIM2_t*) 0x5300)) + + +//------------------------ +// Module TIM3 +//------------------------ + +/** struct containing TIM3 module registers */ +typedef struct { + + /** TIM3 control register 1 (CR1 at 0x5320) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM3_CR1 reset value + #define sfr_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM3 interrupt enable register (IER at 0x5321) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS CC1IE : 1; // bit 1 + BITS CC2IE : 1; // bit 2 + BITS CC3IE : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM3_IER reset value + #define sfr_TIM3_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM3 status register 1 (SR1 at 0x5322) */ + union { + + /// bytewise access to SR1 + uint8_t byte; + + /// bitwise access to register SR1 + struct { + BITS UIF : 1; // bit 0 + BITS CC1IF : 1; // bit 1 + BITS CC2IF : 1; // bit 2 + BITS CC3IF : 1; // bit 3 + BITS : 2; // 2 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR1 bitfield + + /// register _TIM3_SR1 reset value + #define sfr_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00) + + } SR1; + + + /** TIM3 status register 2 (SR2 at 0x5323) */ + union { + + /// bytewise access to SR2 + uint8_t byte; + + /// bitwise access to register SR2 + struct { + BITS : 1; // 1 bit + BITS CC1OF : 1; // bit 1 + BITS CC2OF : 1; // bit 2 + BITS CC3OF : 1; // bit 3 + BITS : 4; // 4 bits + }; // SR2 bitfield + + /// register _TIM3_SR2 reset value + #define sfr_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00) + + } SR2; + + + /** TIM3 event generation register (EGR at 0x5324) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS CC1G : 1; // bit 1 + BITS CC2G : 1; // bit 2 + BITS CC3G : 1; // bit 3 + BITS : 2; // 2 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM3_EGR reset value + #define sfr_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM3 capture/compare mode register 1 (CCMR1 at 0x5325) */ + union { + + /// bytewise access to CCMR1 + uint8_t byte; + + /// bitwise access to register CCMR1 + struct { + BITS CC1S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC1PE : 1; // bit 3 + BITS OC1M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR1 bitfield + + /// register _TIM3_CCMR1 reset value + #define sfr_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00) + + } CCMR1; + + + /** TIM3 capture/compare mode register 2 (CCMR2 at 0x5326) */ + union { + + /// bytewise access to CCMR2 + uint8_t byte; + + /// bitwise access to register CCMR2 + struct { + BITS CC2S : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS OC2PE : 1; // bit 3 + BITS OC2M : 3; // bits 4-6 + BITS : 1; // 1 bit + }; // CCMR2 bitfield + + /// register _TIM3_CCMR2 reset value + #define sfr_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00) + + } CCMR2; + + + /** TIM3 capture/compare enable register 1 (CCER1 at 0x5327) */ + union { + + /// bytewise access to CCER1 + uint8_t byte; + + /// bitwise access to register CCER1 + struct { + BITS CC1E : 1; // bit 0 + BITS CC1P : 1; // bit 1 + BITS : 2; // 2 bits + BITS CC2E : 1; // bit 4 + BITS CC2P : 1; // bit 5 + BITS : 2; // 2 bits + }; // CCER1 bitfield + + /// register _TIM3_CCER1 reset value + #define sfr_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00) + + } CCER1; + + + /** TIM3 counter high (CNTRH at 0x5328) */ + union { + + /// bytewise access to CNTRH + uint8_t byte; + + /// bitwise access to register CNTRH + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRH bitfield + + /// register _TIM3_CNTRH reset value + #define sfr_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00) + + } CNTRH; + + + /** TIM3 counter low (CNTRL at 0x5329) */ + union { + + /// bytewise access to CNTRL + uint8_t byte; + + /// bitwise access to register CNTRL + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTRL bitfield + + /// register _TIM3_CNTRL reset value + #define sfr_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00) + + } CNTRL; + + + /** TIM3 prescaler register (PSCR at 0x532a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 4; // bits 0-3 + BITS : 4; // 4 bits + }; // PSCR bitfield + + /// register _TIM3_PSCR reset value + #define sfr_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM3 auto-reload register high (ARRH at 0x532b) */ + union { + + /// bytewise access to ARRH + uint8_t byte; + + /// bitwise access to register ARRH + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRH bitfield + + /// register _TIM3_ARRH reset value + #define sfr_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF) + + } ARRH; + + + /** TIM3 auto-reload register low (ARRL at 0x532c) */ + union { + + /// bytewise access to ARRL + uint8_t byte; + + /// bitwise access to register ARRL + struct { + BITS ARR : 8; // bits 0-7 + }; // ARRL bitfield + + /// register _TIM3_ARRL reset value + #define sfr_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF) + + } ARRL; + + + /** TIM3 capture/compare register 1 high (CCR1H at 0x532d) */ + union { + + /// bytewise access to CCR1H + uint8_t byte; + + /// bitwise access to register CCR1H + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1H bitfield + + /// register _TIM3_CCR1H reset value + #define sfr_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00) + + } CCR1H; + + + /** TIM3 capture/compare register 1 low (CCR1L at 0x532e) */ + union { + + /// bytewise access to CCR1L + uint8_t byte; + + /// bitwise access to register CCR1L + struct { + BITS CCR1 : 8; // bits 0-7 + }; // CCR1L bitfield + + /// register _TIM3_CCR1L reset value + #define sfr_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00) + + } CCR1L; + + + /** TIM3 capture/compare register 2 high (CCR2H at 0x532f) */ + union { + + /// bytewise access to CCR2H + uint8_t byte; + + /// bitwise access to register CCR2H + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2H bitfield + + /// register _TIM3_CCR2H reset value + #define sfr_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00) + + } CCR2H; + + + /** TIM3 capture/compare register 2 low (CCR2L at 0x5330) */ + union { + + /// bytewise access to CCR2L + uint8_t byte; + + /// bitwise access to register CCR2L + struct { + BITS CCR2 : 8; // bits 0-7 + }; // CCR2L bitfield + + /// register _TIM3_CCR2L reset value + #define sfr_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00) + + } CCR2L; + +} TIM3_t; + +/// access to TIM3 SFR registers +#define sfr_TIM3 (*((TIM3_t*) 0x5320)) + + +//------------------------ +// Module TIM4 +//------------------------ + +/** struct containing TIM4 module registers */ +typedef struct { + + /** TIM4 control register 1 (CR1 at 0x5340) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS CEN : 1; // bit 0 + BITS UDIS : 1; // bit 1 + BITS URS : 1; // bit 2 + BITS OPM : 1; // bit 3 + BITS : 3; // 3 bits + BITS ARPE : 1; // bit 7 + }; // CR1 bitfield + + /// register _TIM4_CR1 reset value + #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** TIM4 interrupt enable register (IER at 0x5341) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS UIE : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIE : 1; // bit 6 + BITS : 1; // 1 bit + }; // IER bitfield + + /// register _TIM4_IER reset value + #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** TIM4 status register (SR at 0x5342) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS UIF : 1; // bit 0 + BITS : 5; // 5 bits + BITS TIF : 1; // bit 6 + BITS : 1; // 1 bit + }; // SR bitfield + + /// register _TIM4_SR reset value + #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) + + } SR; + + + /** TIM4 event generation register (EGR at 0x5343) */ + union { + + /// bytewise access to EGR + uint8_t byte; + + /// bitwise access to register EGR + struct { + BITS UG : 1; // bit 0 + BITS : 5; // 5 bits + BITS TG : 1; // bit 6 + BITS : 1; // 1 bit + }; // EGR bitfield + + /// register _TIM4_EGR reset value + #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) + + } EGR; + + + /** TIM4 counter (CNTR at 0x5344) */ + union { + + /// bytewise access to CNTR + uint8_t byte; + + /// bitwise access to register CNTR + struct { + BITS CNT : 8; // bits 0-7 + }; // CNTR bitfield + + /// register _TIM4_CNTR reset value + #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) + + } CNTR; + + + /** TIM4 prescaler register (PSCR at 0x5345) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSCR bitfield + + /// register _TIM4_PSCR reset value + #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + + + /** TIM4 auto-reload register (ARR at 0x5346) */ + union { + + /// bytewise access to ARR + uint8_t byte; + + /// bitwise access to register ARR + struct { + BITS ARR : 8; // bits 0-7 + }; // ARR bitfield + + /// register _TIM4_ARR reset value + #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) + + } ARR; + +} TIM4_t; + +/// access to TIM4 SFR registers +#define sfr_TIM4 (*((TIM4_t*) 0x5340)) + + +//------------------------ +// Module UART1 +//------------------------ + +/** struct containing UART1 module registers */ +typedef struct { + + /** UART1 status register (SR at 0x5230) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR_LHE : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART1_SR reset value + #define sfr_UART1_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART1 data register (DR at 0x5231) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART1_DR reset value + #define sfr_UART1_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART1 baud rate register 1 (BRR1 at 0x5232) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART1_BRR1 reset value + #define sfr_UART1_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART1 baud rate register 2 (BRR2 at 0x5233) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART1_BRR2 reset value + #define sfr_UART1_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART1 control register 1 (CR1 at 0x5234) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UART0 : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART1_CR1 reset value + #define sfr_UART1_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART1 control register 2 (CR2 at 0x5235) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART1_CR2 reset value + #define sfr_UART1_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART1 control register 3 (CR3 at 0x5236) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS LBCL : 1; // bit 0 + BITS CPHA : 1; // bit 1 + BITS CPOL : 1; // bit 2 + BITS CKEN : 1; // bit 3 + BITS STOP : 2; // bits 4-5 + BITS : 1; // 1 bit + BITS LINEN : 1; // bit 7 + }; // CR3 bitfield + + /// register _UART1_CR3 reset value + #define sfr_UART1_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART1 control register 4 (CR4 at 0x5237) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART1_CR4 reset value + #define sfr_UART1_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /** UART1 control register 5 (CR5 at 0x5238) */ + union { + + /// bytewise access to CR5 + uint8_t byte; + + /// bitwise access to register CR5 + struct { + BITS : 1; // 1 bit + BITS IREN : 1; // bit 1 + BITS IRLP : 1; // bit 2 + BITS HDSEL : 1; // bit 3 + BITS NACK : 1; // bit 4 + BITS SCEN : 1; // bit 5 + BITS : 2; // 2 bits + }; // CR5 bitfield + + /// register _UART1_CR5 reset value + #define sfr_UART1_CR5_RESET_VALUE ((uint8_t) 0x00) + + } CR5; + + + /** UART1 guard time register (GTR at 0x5239) */ + union { + + /// bytewise access to GTR + uint8_t byte; + + /// bitwise access to register GTR + struct { + BITS GT : 8; // bits 0-7 + }; // GTR bitfield + + /// register _UART1_GTR reset value + #define sfr_UART1_GTR_RESET_VALUE ((uint8_t) 0x00) + + } GTR; + + + /** UART1 prescaler register (PSCR at 0x523a) */ + union { + + /// bytewise access to PSCR + uint8_t byte; + + /// bitwise access to register PSCR + struct { + BITS PSC : 8; // bits 0-7 + }; // PSCR bitfield + + /// register _UART1_PSCR reset value + #define sfr_UART1_PSCR_RESET_VALUE ((uint8_t) 0x00) + + } PSCR; + +} UART1_t; + +/// access to UART1 SFR registers +#define sfr_UART1 (*((UART1_t*) 0x5230)) + + +//------------------------ +// Module UART3 +//------------------------ + +/** struct containing UART3 module registers */ +typedef struct { + + /** UART3 status register (SR at 0x5240) */ + union { + + /// bytewise access to SR + uint8_t byte; + + /// bitwise access to register SR + struct { + BITS PE : 1; // bit 0 + BITS FE : 1; // bit 1 + BITS NF : 1; // bit 2 + BITS OR : 1; // bit 3 + BITS IDLE : 1; // bit 4 + BITS RXNE : 1; // bit 5 + BITS TC : 1; // bit 6 + BITS TXE : 1; // bit 7 + }; // SR bitfield + + /// register _UART3_SR reset value + #define sfr_UART3_SR_RESET_VALUE ((uint8_t) 0xC0) + + } SR; + + + /** UART3 data register (DR at 0x5241) */ + union { + + /// bytewise access to DR + uint8_t byte; + + /// bitwise access to register DR + struct { + BITS DR : 8; // bits 0-7 + }; // DR bitfield + + /// register _UART3_DR reset value + #define sfr_UART3_DR_RESET_VALUE ((uint8_t) 0x00) + + } DR; + + + /** UART3 baud rate register 1 (BRR1 at 0x5242) */ + union { + + /// bytewise access to BRR1 + uint8_t byte; + + /// bitwise access to register BRR1 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR1 bitfield + + /// register _UART3_BRR1 reset value + #define sfr_UART3_BRR1_RESET_VALUE ((uint8_t) 0x00) + + } BRR1; + + + /** UART3 baud rate register 2 (BRR2 at 0x5243) */ + union { + + /// bytewise access to BRR2 + uint8_t byte; + + /// bitwise access to register BRR2 + struct { + BITS UART_DIV : 8; // bits 0-7 + }; // BRR2 bitfield + + /// register _UART3_BRR2 reset value + #define sfr_UART3_BRR2_RESET_VALUE ((uint8_t) 0x00) + + } BRR2; + + + /** UART3 control register 1 (CR1 at 0x5244) */ + union { + + /// bytewise access to CR1 + uint8_t byte; + + /// bitwise access to register CR1 + struct { + BITS PIEN : 1; // bit 0 + BITS PS : 1; // bit 1 + BITS PCEN : 1; // bit 2 + BITS WAKE : 1; // bit 3 + BITS M : 1; // bit 4 + BITS UARTD : 1; // bit 5 + BITS T8 : 1; // bit 6 + BITS R8 : 1; // bit 7 + }; // CR1 bitfield + + /// register _UART3_CR1 reset value + #define sfr_UART3_CR1_RESET_VALUE ((uint8_t) 0x00) + + } CR1; + + + /** UART3 control register 2 (CR2 at 0x5245) */ + union { + + /// bytewise access to CR2 + uint8_t byte; + + /// bitwise access to register CR2 + struct { + BITS SBK : 1; // bit 0 + BITS RWU : 1; // bit 1 + BITS REN : 1; // bit 2 + BITS TEN : 1; // bit 3 + BITS ILIEN : 1; // bit 4 + BITS RIEN : 1; // bit 5 + BITS TCIEN : 1; // bit 6 + BITS TIEN : 1; // bit 7 + }; // CR2 bitfield + + /// register _UART3_CR2 reset value + #define sfr_UART3_CR2_RESET_VALUE ((uint8_t) 0x00) + + } CR2; + + + /** UART3 control register 3 (CR3 at 0x5246) */ + union { + + /// bytewise access to CR3 + uint8_t byte; + + /// bitwise access to register CR3 + struct { + BITS : 4; // 4 bits + BITS STOP : 2; // bits 4-5 + BITS LINEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR3 bitfield + + /// register _UART3_CR3 reset value + #define sfr_UART3_CR3_RESET_VALUE ((uint8_t) 0x00) + + } CR3; + + + /** UART3 control register 4 (CR4 at 0x5247) */ + union { + + /// bytewise access to CR4 + uint8_t byte; + + /// bitwise access to register CR4 + struct { + BITS ADD : 4; // bits 0-3 + BITS LBDF : 1; // bit 4 + BITS LBDL : 1; // bit 5 + BITS LBDIEN : 1; // bit 6 + BITS : 1; // 1 bit + }; // CR4 bitfield + + /// register _UART3_CR4 reset value + #define sfr_UART3_CR4_RESET_VALUE ((uint8_t) 0x00) + + } CR4; + + + /// Reserved register (1B) + uint8_t Reserved_1[1]; + + + /** UART3 control register 6 (CR6 at 0x5249) */ + union { + + /// bytewise access to CR6 + uint8_t byte; + + /// bitwise access to register CR6 + struct { + BITS LSF : 1; // bit 0 + BITS LHDF : 1; // bit 1 + BITS LHDIEN : 1; // bit 2 + BITS : 1; // 1 bit + BITS LASE : 1; // bit 4 + BITS LSLV : 1; // bit 5 + BITS : 1; // 1 bit + BITS LDUM : 1; // bit 7 + }; // CR6 bitfield + + /// register _UART3_CR6 reset value + #define sfr_UART3_CR6_RESET_VALUE ((uint8_t) 0x00) + + } CR6; + +} UART3_t; + +/// access to UART3 SFR registers +#define sfr_UART3 (*((UART3_t*) 0x5240)) + + +//------------------------ +// Module WWDG +//------------------------ + +/** struct containing WWDG module registers */ +typedef struct { + + /** WWDG control register (CR at 0x50d1) */ + union { + + /// bytewise access to CR + uint8_t byte; + + /// bitwise access to register CR + struct { + BITS T0 : 1; // bit 0 + BITS T1 : 1; // bit 1 + BITS T2 : 1; // bit 2 + BITS T3 : 1; // bit 3 + BITS T4 : 1; // bit 4 + BITS T5 : 1; // bit 5 + BITS T6 : 1; // bit 6 + BITS WDGA : 1; // bit 7 + }; // CR bitfield + + /// register _WWDG_CR reset value + #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) + + } CR; + + + /** WWDR window register (WR at 0x50d2) */ + union { + + /// bytewise access to WR + uint8_t byte; + + /// bitwise access to register WR + struct { + BITS W0 : 1; // bit 0 + BITS W1 : 1; // bit 1 + BITS W2 : 1; // bit 2 + BITS W3 : 1; // bit 3 + BITS W4 : 1; // bit 4 + BITS W5 : 1; // bit 5 + BITS W6 : 1; // bit 6 + BITS : 1; // 1 bit + }; // WR bitfield + + /// register _WWDG_WR reset value + #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) + + } WR; + +} WWDG_t; + +/// access to WWDG SFR registers +#define sfr_WWDG (*((WWDG_t*) 0x50d1)) + + +//------------------------ +// Module CAN +//------------------------ + +/** struct containing CAN module registers */ +typedef struct { + + /** CAN master control register (MCR at 0x5420) */ + union { + + /// bytewise access to MCR + uint8_t byte; + + /// bitwise access to register MCR + struct { + BITS INRQ : 1; // bit 0 + BITS SLEEP : 1; // bit 1 + BITS TXFP : 1; // bit 2 + BITS RFLM : 1; // bit 3 + BITS NART : 1; // bit 4 + BITS AWUM : 1; // bit 5 + BITS ABOM : 1; // bit 6 + BITS TTOM : 1; // bit 7 + }; // MCR bitfield + + /// register CAN_MCR reset value + #define sfr_CAN_MCR_RESET_VALUE ((uint8_t) 0x02) + + } MCR; + + + /** CAN master status register (MSR at 0x5421) */ + union { + + /// bytewise access to MSR + uint8_t byte; + + /// bitwise access to register MSR + struct { + BITS INAK : 1; // bit 0 + BITS SLAK : 1; // bit 1 + BITS ERRI : 1; // bit 2 + BITS WKUI : 1; // bit 3 + BITS TX : 1; // bit 4 + BITS RX : 1; // bit 5 + BITS : 2; // 2 bits + }; // MSR bitfield + + /// register CAN_MSR reset value + #define sfr_CAN_MSR_RESET_VALUE ((uint8_t) 0x02) + + } MSR; + + + /** CAN transmit status register (TSR at 0x5422) */ + union { + + /// bytewise access to TSR + uint8_t byte; + + /// bitwise access to register TSR + struct { + BITS RQCP0 : 1; // bit 0 + BITS RQCP1 : 1; // bit 1 + BITS RQCP2 : 1; // bit 2 + BITS : 1; // 1 bit + BITS TXQOK0 : 1; // bit 4 + BITS TXQOK1 : 1; // bit 5 + BITS TXQOK2 : 1; // bit 6 + BITS : 1; // 1 bit + }; // TSR bitfield + + /// register CAN_TSR reset value + #define sfr_CAN_TSR_RESET_VALUE ((uint8_t) 0x00) + + } TSR; + + + /** CAN transmit priority register (TPR at 0x5423) */ + union { + + /// bytewise access to TPR + uint8_t byte; + + /// bitwise access to register TPR + struct { + BITS CODE0 : 1; // bit 0 + BITS CODE1 : 1; // bit 1 + BITS TME0 : 1; // bit 2 + BITS TME1 : 1; // bit 3 + BITS TME2 : 1; // bit 4 + BITS LOW0 : 1; // bit 5 + BITS LOW1 : 1; // bit 6 + BITS LOW2 : 1; // bit 7 + }; // TPR bitfield + + /// register CAN_TPR reset value + #define sfr_CAN_TPR_RESET_VALUE ((uint8_t) 0x0C) + + } TPR; + + + /** CAN receive FIFO register (RFR at 0x5424) */ + union { + + /// bytewise access to RFR + uint8_t byte; + + /// bitwise access to register RFR + struct { + BITS FMP : 2; // bits 0-1 + BITS : 1; // 1 bit + BITS FULL : 1; // bit 3 + BITS FOVR : 1; // bit 4 + BITS RFOM : 1; // bit 5 + BITS : 2; // 2 bits + }; // RFR bitfield + + /// register CAN_RFR reset value + #define sfr_CAN_RFR_RESET_VALUE ((uint8_t) 0x00) + + } RFR; + + + /** CAN interrupt enable register (IER at 0x5425) */ + union { + + /// bytewise access to IER + uint8_t byte; + + /// bitwise access to register IER + struct { + BITS TMEIE : 1; // bit 0 + BITS FMPIE : 1; // bit 1 + BITS FFIE : 1; // bit 2 + BITS FOVIE : 1; // bit 3 (mismatch with IAR!) + BITS : 3; // 3 bits + BITS WKUIE : 1; // bit 7 + }; // IER bitfield + + /// register CAN_IER reset value + #define sfr_CAN_IER_RESET_VALUE ((uint8_t) 0x00) + + } IER; + + + /** CAN diagnosis register (DGR at 0x5426) */ + union { + + /// bytewise access to DGR + uint8_t byte; + + /// bitwise access to register DGR + struct { + BITS LBKM : 1; // bit 0 + BITS SILM : 1; // bit 1 + BITS SAMP : 1; // bit 2 + BITS RX : 1; // bit 3 + BITS TXM2E : 1; // bit 4 + BITS : 3; // 3 bits + }; // DGR bitfield + + /// register CAN_DGR reset value + #define sfr_CAN_DGR_RESET_VALUE ((uint8_t) 0x0C) + + } DGR; + + + /** CAN page selection register (PSR at 0x5427) */ + union { + + /// bytewise access to PSR + uint8_t byte; + + /// bitwise access to register PSR + struct { + BITS PS : 3; // bits 0-2 + BITS : 5; // 5 bits + }; // PSR bitfield + + /// register CAN_PSR reset value + #define sfr_CAN_PSR_RESET_VALUE ((uint8_t) 0x00) + + } PSR; + + + /** CAN paged register 0 (at 0x5428) */ + union { + + /// Page 0: CAN message control/status register (CAN_MCSR) + union { + + /// bytewise access to MCSR + uint8_t byte; + + /// bitwise access to register MCSR + struct { + BITS TXRQ : 1; // bit 0 + BITS ABRQ : 1; // bit 1 + BITS RQCP : 1; // bit 2 + BITS TXOK : 1; // bit 3 + BITS ALST : 1; // bit 4 + BITS TERR : 1; // bit 5 + BITS : 2; // 2 bits + }; // MCSR bitfield + + /// register CAN_MCSR reset value + #define sfr_CAN_MCSR_RESET_VALUE ((uint8_t) 0x00) + + } MCSR; + + + /// Page 1: CAN message control/status register (CAN_MCSR), see page 0 + + + /// Page 2: CAN filter bank 0 register 1 (CAN_F0R1) + union { + + /// bytewise access to F0R1 + uint8_t byte; + + /// bitwise access to register F0R1 + struct { + BITS FB : 8; // bits 0-7 + }; // F0R1 bitfield + + /// no register reset value + + } F0R1; + + + /// Page 3: CAN filter bank 2 register 1 (CAN_F2R1) + union { + + /// bytewise access to F2R1 + uint8_t byte; + + /// bitwise access to register F2R1 + struct { + BITS FB : 8; // bits 0-7 + }; // F2R1 bitfield + + /// no register reset value + + } F2R1; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F4R1) + union { + + /// bytewise access to F4R1 + uint8_t byte; + + /// bitwise access to register F4R1 + struct { + BITS FB : 8; // bits 0-7 + }; // F4R1 bitfield + + /// no register reset value + + } F4R1; + + + /// Page 5: CAN message control/status register (CAN_MCSR), see page 0 + + + /// Page 6: CAN error status register (CAN_ESR) + union { + + /// bytewise access to ESR + uint8_t byte; + + /// bitwise access to register ESR + struct { + BITS EWGF : 1; // bit 0 + BITS EPVF : 1; // bit 1 + BITS BOFF : 1; // bit 2 + BITS : 1; // 1 bit + BITS LEC : 3; // bits 4..6 + BITS : 1; // 1 bit + }; // ESR bitfield + + /// register CAN_ESR reset value + #define sfr_CAN_ESR_RESET_VALUE ((uint8_t) 0x00) + + } ESR; + + + /// Page 7: CAN mailbox filter match index register (CAN_MFMIR) + union { + + /// bytewise access to MFMIR + uint8_t byte; + + /// bitwise access to register MFMIR + struct { + BITS FMI : 8; // bits 0-7 + }; // MFMIR bitfield + + /// no register reset value + + } MFMIR; + + }; // CAN paged register 0 + + + /** CAN paged register 1 (at 0x5429) */ + union { + + /// Page 0: CAN mailbox data length control register (CAN_MDLCR) + union { + + /// bytewise access to MDLCR + uint8_t byte; + + /// bitwise access to register MDLCR + struct { + BITS DLC : 4; // bits 0-3 + BITS : 3; // 3 bits + BITS TGT : 1; // bit 7 + }; // MDLCR bitfield + + /// no register reset value + + } MDLCR; + + + /// Page 1: CAN mailbox data length control register (CAN_MDLCR), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F0R2) + union { + + /// bytewise access to F0R2 + uint8_t byte; + + /// bitwise access to register F0R2 + struct { + BITS FB : 8; // bits 0-7 + }; // F0R2 bitfield + + /// no register reset value + + } F0R2; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F2R2) + union { + + /// bytewise access to F2R2 + uint8_t byte; + + /// bitwise access to register F2R2 + struct { + BITS FB : 8; // bits 0-7 + }; // F2R2 bitfield + + /// no register reset value + + } F2R2; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F4R2) + union { + + /// bytewise access to F4R2 + uint8_t byte; + + /// bitwise access to register F4R2 + struct { + BITS FB : 8; // bits 0-7 + }; // F4R2 bitfield + + /// no register reset value + + } F4R2; + + + /// Page 5: CAN mailbox data length control register (CAN_MDLCR), see page 0 + + + /// Page 6: CAN error interrupt enable register (CAN_EIER) + union { + + /// bytewise access to EIER + uint8_t byte; + + /// bitwise access to register EIER + struct { + BITS EWGIE : 1; // bit 0 + BITS EPVIE : 1; // bit 1 + BITS BOFIE : 1; // bit 2 + BITS : 1; // 1 bit + BITS LECIE : 1; // bit 4 + BITS : 2; // 2 bits + BITS ERRIE : 1; // bit 7 + }; // EIER bitfield + + /// register CAN_EIER reset value + #define sfr_CAN_EIER_RESET_VALUE ((uint8_t) 0x00) + + } EIER; + + + /// Page 7: CAN mailbox data length control register (CAN_MDLCR), see page 0 + + }; // CAN paged register 1 + + + /** CAN paged register 2 (at 0x542a) */ + union { + + /// Page 0: CAN mailbox identifier register 1 (CAN_MIDR1) + union { + + /// bytewise access to MIDR1 + uint8_t byte; + + /// bitwise access to register MIDR1 + struct { + BITS ID : 5; // bits 0-4 + BITS RTR : 1; // bit 5 + BITS IDE : 1; // bit 6 + BITS : 1; // 1 bit + }; // MIDR1 bitfield + + /// no register reset value + + } MIDR1; + + + /// Page 1: CAN mailbox identifier register 1 (CAN_MIDR1), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F0R3) + union { + + /// bytewise access to F0R3 + uint8_t byte; + + /// bitwise access to register F0R3 + struct { + BITS FB : 8; // bits 0-7 + }; // F0R3 bitfield + + /// no register reset value + + } F0R3; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F2R3) + union { + + /// bytewise access to F2R3 + uint8_t byte; + + /// bitwise access to register F2R3 + struct { + BITS FB : 8; // bits 0-7 + }; // F2R3 bitfield + + /// no register reset value + + } F2R3; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F4R3) + union { + + /// bytewise access to F4R3 + uint8_t byte; + + /// bitwise access to register F4R3 + struct { + BITS FB : 8; // bits 0-7 + }; // F4R3 bitfield + + /// no register reset value + + } F4R3; + + + /// Page 5: CAN mailbox identifier register 1 (CAN_MIDR1), see page 0 + + + /// Page 6:CAN transmit error counter register (CAN_TECR) + union { + + /// bytewise access to TECR + uint8_t byte; + + /// bitwise access to register TECR + struct { + BITS EWGIE : 1; // bit 0 + BITS EPVIE : 1; // bit 1 + BITS BOFIE : 1; // bit 2 + BITS : 1; // 1 bit + BITS LECIE : 1; // bit 4 + BITS : 2; // 2 bits + BITS ERRIE : 1; // bit 7 + }; // TECR bitfield + + /// register CAN_TECR reset value + #define sfr_CAN_TECR_RESET_VALUE ((uint8_t) 0x00) + + } TECR; + + + /// Page 7: CAN mailbox identifier register 1 (CAN_MIDR1), see page 0 + + }; // CAN paged register 2 + + + /** CAN paged register 3 (at 0x542b) */ + union { + + /// Page 0: CAN mailbox identifier register 2 (CAN_MIDR2) + union { + + /// bytewise access to MIDR2 + uint8_t byte; + + /// bitwise access to register MIDR2 + struct { + BITS EXID : 2; // bits 0-1 + BITS ID : 6; // bits 2-7 + }; // MIDR2 bitfield + + /// no register reset value + + } MIDR2; + + + /// Page 1: CAN mailbox identifier register 2 (CAN_MIDR2), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F0R4) + union { + + /// bytewise access to F0R4 + uint8_t byte; + + /// bitwise access to register F0R4 + struct { + BITS FB : 8; // bits 0-7 + }; // F0R4 bitfield + + /// no register reset value + + } F0R4; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F2R4) + union { + + /// bytewise access to F2R4 + uint8_t byte; + + /// bitwise access to register F2R4 + struct { + BITS FB : 8; // bits 0-7 + }; // F2R4 bitfield + + /// no register reset value + + } F2R4; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F4R4) + union { + + /// bytewise access to F4R4 + uint8_t byte; + + /// bitwise access to register F4R4 + struct { + BITS FB : 8; // bits 0-7 + }; // F4R4 bitfield + + /// no register reset value + + } F4R4; + + + /// Page 5: CAN mailbox identifier register 2 (CAN_MIDR2), see page 0 + + + /// Page 6: CAN receive error counter register (CAN_RECR) + union { + + /// bytewise access to RECR + uint8_t byte; + + /// bitwise access to register RECR + struct { + BITS REC : 8; // bits 0-7 + }; // RECR bitfield + + /// register CAN_RECR reset value + #define sfr_CAN_RECR_RESET_VALUE ((uint8_t) 0x00) + + } RECR; + + + /// Page 7: CAN mailbox identifier register 2 (CAN_MIDR2), see page 0 + + }; // CAN paged register 3 + + + /** CAN paged register 4 (0x542c) */ + union { + + /// Page 0: CAN mailbox identifier register 3 (CAN_MIDR3) + union { + + /// bytewise access to MIDR3 + uint8_t byte; + + /// bitwise access to register MIDR3 + struct { + BITS EXID : 8; // bits 0-7 + }; // MIDR3 bitfield + + /// no register reset value + + } MIDR3; + + + /// Page 1: CAN mailbox identifier register 3 (CAN_MIDR3), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F0R5) + union { + + /// bytewise access to F0R5 + uint8_t byte; + + /// bitwise access to register F0R5 + struct { + BITS FB : 8; // bits 0-7 + }; // F0R5 bitfield + + /// no register reset value + + } F0R5; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F2R5) + union { + + /// bytewise access to F2R5 + uint8_t byte; + + /// bitwise access to register F2R5 + struct { + BITS FB : 8; // bits 0-7 + }; // F2R5 bitfield + + /// no register reset value + + } F2R5; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F4R5) + union { + + /// bytewise access to F4R5 + uint8_t byte; + + /// bitwise access to register F4R5 + struct { + BITS FB : 8; // bits 0-7 + }; // F4R5 bitfield + + /// no register reset value + + } F4R5; + + + /// Page 5: CAN mailbox identifier register 3 (CAN_MIDR3), see page 0 + + + /// Page 6: CAN bit timing register 1 (CAN_BTR1) + union { + + /// bytewise access to BTR1 + uint8_t byte; + + /// bitwise access to register BTR1 + struct { + BITS BRP : 6; // bits 0-5 + BITS SJW : 2; // bits 6-7 + }; // BTR1 bitfield + + /// register CAN_BTR1 reset value + #define sfr_CAN_BTR1_RESET_VALUE ((uint8_t) 0x40) + + } BTR1; + + + /// Page 7: CAN mailbox identifier register 3 (CAN_MIDR3), see page 0 + + }; // CAN paged register 4 + + + /** CAN paged register 5 (at 0x542d) */ + union { + + /// Page 0: CAN mailbox identifier register 4 (CAN_MIDR4) + union { + + /// bytewise access to MIDR4 + uint8_t byte; + + /// bitwise access to register MIDR4 + struct { + BITS EXID : 8; // bits 0-7 + }; // MIDR4 bitfield + + /// no register reset value + + } MIDR4; + + + /// Page 1: CAN mailbox identifier register 4 (CAN_MIDR4), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F0R6) + union { + + /// bytewise access to F0R6 + uint8_t byte; + + /// bitwise access to register F0R6 + struct { + BITS FB : 8; // bits 0-7 + }; // F0R6 bitfield + + /// no register reset value + + } F0R6; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F2R6) + union { + + /// bytewise access to F2R6 + uint8_t byte; + + /// bitwise access to register F2R6 + struct { + BITS FB : 8; // bits 0-7 + }; // F2R6 bitfield + + /// no register reset value + + } F2R6; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F4R6) + union { + + /// bytewise access to F4R6 + uint8_t byte; + + /// bitwise access to register F4R6 + struct { + BITS FB : 8; // bits 0-7 + }; // F4R6 bitfield + + /// no register reset value + + } F4R6; + + + /// Page 5: CAN mailbox identifier register 4 (CAN_MIDR4), see page 0 + + + /// Page 6: CAN bit timing register 2 (CAN_BTR2) + union { + + /// bytewise access to BTR2 + uint8_t byte; + + /// bitwise access to register BTR2 + struct { + BITS BS1 : 4; // bits 0-3 + BITS BS2 : 3; // bits 4-6 + BITS CLK : 1; // bit 7 (undocumented in newer UM!) + }; // BTR2 bitfield + + /// register CAN_BTR2 reset value + #define sfr_CAN_BTR2_RESET_VALUE ((uint8_t) 0x23) + + } BTR2; + + + /// Page 7: CAN mailbox identifier register 4 (CAN_MIDR4), see page 0 + + }; // CAN paged register 5 + + + /** CAN paged register 6 (at 0x542e) */ + union { + + /// Page 0: CAN mailbox data register 1 (CAN_MDAR1) + union { + + /// bytewise access to MDAR1 + uint8_t byte; + + /// bitwise access to register MDAR1 + struct { + BITS DATA : 8; // bits 0-7 + }; // MDAR1 bitfield + + /// no register reset value + + } MDAR1; + + + /// Page 1: CAN mailbox data register 1 (CAN_MDAR1), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F0R7) + union { + + /// bytewise access to F0R7 + uint8_t byte; + + /// bitwise access to register F0R7 + struct { + BITS FB : 8; // bits 0-7 + }; // F0R7 bitfield + + /// no register reset value + + } F0R7; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F2R7) + union { + + /// bytewise access to F2R7 + uint8_t byte; + + /// bitwise access to register F2R7 + struct { + BITS FB : 8; // bits 0-7 + }; // F2R7 bitfield + + /// no register reset value + + } F2R7; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F4R7) + union { + + /// bytewise access to F4R7 + uint8_t byte; + + /// bitwise access to register F4R7 + struct { + BITS FB : 8; // bits 0-7 + }; // F4R7 bitfield + + /// no register reset value + + } F4R7; + + + /// Page 5: CAN mailbox data register 1 (CAN_MDAR1), see page 0 + + + /// Page 6: Reserved + + + /// Page 7: CAN mailbox data register 1 (CAN_MDAR1), see page 0 + + }; // CAN paged register 6 + + + /** CAN paged register 7 (at 0x542f) */ + union { + + /// Page 0: CAN mailbox data register 1 (CAN_MDAR2) + union { + + /// bytewise access to MDAR2 + uint8_t byte; + + /// bitwise access to register MDAR2 + struct { + BITS DATA : 8; // bits 0-7 + }; // MDAR2 bitfield + + /// no register reset value + + } MDAR2; + + + /// Page 1: CAN mailbox data register 2 (CAN_MDAR2), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F0R8) + union { + + /// bytewise access to F0R8 + uint8_t byte; + + /// bitwise access to register F0R8 + struct { + BITS FB : 8; // bits 0-7 + }; // F0R8 bitfield + + /// no register reset value + + } F0R8; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F2R8) + union { + + /// bytewise access to F2R8 + uint8_t byte; + + /// bitwise access to register F2R8 + struct { + BITS FB : 8; // bits 0-7 + }; // F2R8 bitfield + + /// no register reset value + + } F2R8; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F4R8) + union { + + /// bytewise access to F4R8 + uint8_t byte; + + /// bitwise access to register F4R8 + struct { + BITS FB : 8; // bits 0-7 + }; // F4R8 bitfield + + /// no register reset value + + } F4R8; + + + /// Page 5: CAN mailbox data register 2 (CAN_MDAR2), see page 0 + + + /// Page 6: Reserved + + + /// Page 7: CAN mailbox data register 2 (CAN_MDAR2), see page 0 + + }; // CAN paged register 7 + + + /** CAN paged register 8 (at 0x5430) */ + union { + + /// Page 0: CAN mailbox data register 1 (CAN_MDAR3) + union { + + /// bytewise access to MDAR3 + uint8_t byte; + + /// bitwise access to register MDAR3 + struct { + BITS DATA : 8; // bits 0-7 + }; // MDAR3 bitfield + + /// no register reset value + + } MDAR3; + + + /// Page 1: CAN mailbox data register 3 (CAN_MDAR3), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F1R1) + union { + + /// bytewise access to F1R1 + uint8_t byte; + + /// bitwise access to register F1R1 + struct { + BITS FB : 8; // bits 0-7 + }; // F1R1 bitfield + + /// no register reset value + + } F1R1; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F3R1) + union { + + /// bytewise access to F3R1 + uint8_t byte; + + /// bitwise access to register F3R1 + struct { + BITS FB : 8; // bits 0-7 + }; // F3R1 bitfield + + /// no register reset value + + } F3R1; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F5R1) + union { + + /// bytewise access to F5R1 + uint8_t byte; + + /// bitwise access to register F5R1 + struct { + BITS FB : 8; // bits 0-7 + }; // F5R1 bitfield + + /// no register reset value + + } F5R1; + + + /// Page 5: CAN mailbox data register 3 (CAN_MDAR3), see page 0 + + + /// Page 6: CAN filter mode register 1 (CAN_FMR1) + union { + + /// bytewise access to FMR1 + uint8_t byte; + + /// bitwise access to register FMR1 + struct { + BITS FML0 : 1; // bit 0 + BITS FMH0 : 1; // bit 1 + BITS FML1 : 1; // bit 2 + BITS FMH1 : 1; // bit 3 + BITS FML2 : 1; // bit 4 + BITS FMH2 : 1; // bit 5 + BITS FML3 : 1; // bit 6 + BITS FMH3 : 1; // bit 7 + }; // FMR1 bitfield + + /// register CAN_FMR1 reset value + #define sfr_CAN_FMR1_RESET_VALUE ((uint8_t) 0x00) + + } FMR1; + + + /// Page 7: CAN mailbox data register 3 (CAN_MDAR3), see page 0 + + }; // CAN paged register 8 + + + /** CAN paged register 9 (at 0x5431) */ + union { + + /// Page 0: CAN mailbox data register 1 (CAN_MDAR4) + union { + + /// bytewise access to MDAR4 + uint8_t byte; + + /// bitwise access to register MDAR4 + struct { + BITS DATA : 8; // bits 0-7 + }; // MDAR4 bitfield + + /// no register reset value + + } MDAR4; + + + /// Page 1: CAN mailbox data register 4 (CAN_MDAR4), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F1R2) + union { + + /// bytewise access to F1R2 + uint8_t byte; + + /// bitwise access to register F1R2 + struct { + BITS FB : 8; // bits 0-7 + }; // F1R2 bitfield + + /// no register reset value + + } F1R2; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F3R2) + union { + + /// bytewise access to F3R2 + uint8_t byte; + + /// bitwise access to register F3R2 + struct { + BITS FB : 8; // bits 0-7 + }; // F3R2 bitfield + + /// no register reset value + + } F3R2; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F5R2) + union { + + /// bytewise access to F5R2 + uint8_t byte; + + /// bitwise access to register F5R2 + struct { + BITS FB : 8; // bits 0-7 + }; // F5R2 bitfield + + /// no register reset value + + } F5R2; + + + /// Page 5: CAN mailbox data register 4 (CAN_MDAR4), see page 0 + + + /// Page 6: CAN filter mode register 2 (CAN_FMR2) + union { + + /// bytewise access to FMR2 + uint8_t byte; + + /// bitwise access to register FMR2 + struct { + BITS FML4 : 1; // bit 0 + BITS FMH4 : 1; // bit 1 + BITS FML5 : 1; // bit 2 + BITS FMH5 : 1; // bit 3 + BITS : 4; // 4 bits + }; // FMR2 bitfield + + /// register CAN_FMR2 reset value + #define sfr_CAN_FMR2_RESET_VALUE ((uint8_t) 0x00) + + } FMR2; + + + /// Page 7: CAN mailbox data register 4 (CAN_MDAR4), see page 0 + + }; // CAN paged register 9 + + + /** CAN paged register A (at 0x5432) */ + union { + + /// Page 0: CAN mailbox data register 1 (CAN_MDAR5) + union { + + /// bytewise access to MDAR5 + uint8_t byte; + + /// bitwise access to register MDAR5 + struct { + BITS DATA : 8; // bits 0-7 + }; // MDAR5 bitfield + + /// no register reset value + + } MDAR5; + + + /// Page 1: CAN mailbox data register 5 (CAN_MDAR5), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F1R3) + union { + + /// bytewise access to F1R3 + uint8_t byte; + + /// bitwise access to register F1R3 + struct { + BITS FB : 8; // bits 0-7 + }; // F1R3 bitfield + + /// no register reset value + + } F1R3; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F3R3) + union { + + /// bytewise access to F3R3 + uint8_t byte; + + /// bitwise access to register F3R3 + struct { + BITS FB : 8; // bits 0-7 + }; // F3R3 bitfield + + /// no register reset value + + } F3R3; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F5R3) + union { + + /// bytewise access to F5R3 + uint8_t byte; + + /// bitwise access to register F5R3 + struct { + BITS FB : 8; // bits 0-7 + }; // F5R3 bitfield + + /// no register reset value + + } F5R3; + + + /// Page 5: CAN mailbox data register 5 (CAN_MDAR5), see page 0 + + + /// Page 6: CAN filter configuration register 1 (CAN_FCR1) + union { + + /// bytewise access to FCR1 + uint8_t byte; + + /// bitwise access to register FCR1 + struct { + BITS FACT0 : 1; // bit 0 + BITS FSC0 : 2; // bits 1-2 + BITS : 1; // 1 bit + BITS FACT1 : 1; // bit 4 + BITS FSC1 : 1; // bit 5-6 + BITS : 1; // 1 bit + }; // FCR1 bitfield + + /// register CAN_FCR1 reset value + #define sfr_CAN_FCR1_RESET_VALUE ((uint8_t) 0x00) + + } FCR1; + + + /// Page 7: CAN mailbox data register 5 (CAN_MDAR5), see page 0 + + }; // CAN paged register A + + + /** CAN paged register B (at 0x5433) */ + union { + + /// Page 0: CAN mailbox data register 1 (CAN_MDAR6) + union { + + /// bytewise access to MDAR6 + uint8_t byte; + + /// bitwise access to register MDAR6 + struct { + BITS DATA : 8; // bits 0-7 + }; // MDAR6 bitfield + + /// no register reset value + + } MDAR6; + + + /// Page 1: CAN mailbox data register 6 (CAN_MDAR6), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F1R4) + union { + + /// bytewise access to F1R4 + uint8_t byte; + + /// bitwise access to register F1R4 + struct { + BITS FB : 8; // bits 0-7 + }; // F1R4 bitfield + + /// no register reset value + + } F1R4; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F3R4) + union { + + /// bytewise access to F3R4 + uint8_t byte; + + /// bitwise access to register F3R4 + struct { + BITS FB : 8; // bits 0-7 + }; // F3R4 bitfield + + /// no register reset value + + } F3R4; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F5R4) + union { + + /// bytewise access to F5R4 + uint8_t byte; + + /// bitwise access to register F5R4 + struct { + BITS FB : 8; // bits 0-7 + }; // F5R4 bitfield + + /// no register reset value + + } F5R4; + + + /// Page 5: CAN mailbox data register 6 (CAN_MDAR6), see page 0 + + + /// Page 6: CAN filter configuration register 2 (CAN_FCR2) + union { + + /// bytewise access to FCR2 + uint8_t byte; + + /// bitwise access to register FCR2 + struct { + BITS FACT2 : 1; // bit 0 + BITS FSC2 : 2; // bit 1-2 + BITS : 1; // 1 bit + BITS FACT3 : 1; // bit 4 + BITS FSC3 : 2; // bit 5-6 + BITS : 1; // 1 bit + }; // FCR2 bitfield + + /// register CAN_FCR2 reset value + #define sfr_CAN_FCR2_RESET_VALUE ((uint8_t) 0x00) + + } FCR2; + + + /// Page 7: CAN mailbox data register 6 (CAN_MDAR6), see page 0 + + }; // CAN paged register B + + + /** CAN paged register C (at 0x5434) */ + union { + + /// Page 0: CAN mailbox data register 7 (CAN_MDAR7) + union { + + /// bytewise access to MDAR7 + uint8_t byte; + + /// bitwise access to register MDAR7 + struct { + BITS DATA : 8; // bits 0-7 + }; // MDAR7 bitfield + + /// no register reset value + + } MDAR7; + + + /// Page 1: CAN mailbox data register 7 (CAN_MDAR7), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F1R5) + union { + + /// bytewise access to F1R5 + uint8_t byte; + + /// bitwise access to register F1R5 + struct { + BITS FB : 8; // bits 0-7 + }; // F1R5 bitfield + + /// no register reset value + + } F1R5; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F3R5) + union { + + /// bytewise access to F3R5 + uint8_t byte; + + /// bitwise access to register F3R5 + struct { + BITS FB : 8; // bits 0-7 + }; // F3R5 bitfield + + /// no register reset value + + } F3R5; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F5R5) + union { + + /// bytewise access to F5R5 + uint8_t byte; + + /// bitwise access to register F5R5 + struct { + BITS FB : 8; // bits 0-7 + }; // F5R5 bitfield + + /// no register reset value + + } F5R5; + + + /// Page 5: CAN mailbox data register 7 (CAN_MDAR7), see page 0 + + + /// Page 6: CAN filter configuration register 3 (CAN_FCR3) + union { + + /// bytewise access to FCR3 + uint8_t byte; + + /// bitwise access to register FCR3 + struct { + BITS FACT4 : 1; // bit 0 + BITS FSC4 : 2; // bit 1-2 + BITS : 1; // 1 bit + BITS FACT5 : 1; // bit 4 + BITS FSC5 : 2; // bit 5-6 + BITS : 1; // 1 bit + }; // FCR3 bitfield + + /// register CAN_FCR3 reset value + #define sfr_CAN_FCR3_RESET_VALUE ((uint8_t) 0x00) + + } FCR3; + + + /// Page 7: CAN mailbox data register 7 (CAN_MDAR7), see page 0 + + }; // CAN paged register C + + + /** CAN paged register D (at 0x5435) */ + union { + + /// Page 0: CAN mailbox data register 1 (CAN_MDAR8) + union { + + /// bytewise access to MDAR8 + uint8_t byte; + + /// bitwise access to register MDAR8 + struct { + BITS DATA : 8; // bits 0-7 + }; // MDAR8 bitfield + + /// no register reset value + + } MDAR8; + + + /// Page 1: CAN mailbox data register 8 (CAN_MDAR8), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F1R6) + union { + + /// bytewise access to F1R6 + uint8_t byte; + + /// bitwise access to register F1R6 + struct { + BITS FB : 8; // bits 0-7 + }; // F1R6 bitfield + + /// no register reset value + + } F1R6; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F3R6) + union { + + /// bytewise access to F3R6 + uint8_t byte; + + /// bitwise access to register F3R6 + struct { + BITS FB : 8; // bits 0-7 + }; // F3R6 bitfield + + /// no register reset value + + } F3R6; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F5R6) + union { + + /// bytewise access to F5R6 + uint8_t byte; + + /// bitwise access to register F5R6 + struct { + BITS FB : 8; // bits 0-7 + }; // F5R6 bitfield + + /// no register reset value + + } F5R6; + + + /// Page 5: CAN mailbox data register 8 (CAN_MDAR8), see page 0 + + + /// Page 6: Reserved + + + /// Page 5: CAN mailbox data register 8 (CAN_MDAR8), see page 0 + + }; // CAN paged register D + + + /** CAN paged register E (at 0x5436) */ + union { + + /// Page 0: CAN mailbox time stamp register low (CAN_MTSRL) + union { + + /// bytewise access to MTSRL + uint8_t byte; + + /// bitwise access to register MTSRL + struct { + BITS TIME : 8; // bits 0-7 + }; // MTSRL bitfield + + /// no register reset value + + } MTSRL; + + + /// Page 1: CAN mailbox time stamp register low (CAN_MTSRL), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F1R7) + union { + + /// bytewise access to F1R7 + uint8_t byte; + + /// bitwise access to register F1R7 + struct { + BITS FB : 8; // bits 0-7 + }; // F1R7 bitfield + + /// no register reset value + + } F1R7; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F3R7) + union { + + /// bytewise access to F3R7 + uint8_t byte; + + /// bitwise access to register F3R7 + struct { + BITS FB : 8; // bits 0-7 + }; // F3R7 bitfield + + /// no register reset value + + } F3R7; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F5R7) + union { + + /// bytewise access to F5R7 + uint8_t byte; + + /// bitwise access to register F5R7 + struct { + BITS FB : 8; // bits 0-7 + }; // F5R7 bitfield + + /// no register reset value + + } F5R7; + + + /// Page 5: CAN mailbox time stamp register low (CAN_MTSRL), see page 0 + + + /// Page 6: Reserved + + + /// Page 7: CAN mailbox time stamp register low (CAN_MTSRL), see page 0 + + }; // CAN paged register E + + + /** CAN paged register F (at 0x5437) */ + union { + + /// page REGF + uint8_t byte; + + + /// Page 0: CAN mailbox time stamp register high (CAN_MTSRH) + union { + + /// bytewise access to MTSRH + uint8_t byte; + + /// bitwise access to register MTSRH + struct { + BITS TIME : 8; // bits 0-7 + }; // MTSRH bitfield + + /// no register reset value + + } MTSRH; + + + /// Page 1: CAN mailbox time stamp register high (CAN_MTSRH), see page 0 + + + /// Page 2: CAN filter bank 0 register 2 (CAN_F1R8) + union { + + /// bytewise access to F1R8 + uint8_t byte; + + /// bitwise access to register F1R8 + struct { + BITS FB : 8; // bits 0-7 + }; // F1R8 bitfield + + /// no register reset value + + } F1R8; + + + /// Page 3: CAN filter bank 2 register 2 (CAN_F3R8) + union { + + /// bytewise access to F3R8 + uint8_t byte; + + /// bitwise access to register F3R8 + struct { + BITS FB : 8; // bits 0-7 + }; // F3R8 bitfield + + /// no register reset value + + } F3R8; + + + /// Page 4: CAN filter bank 4 register 1 (CAN_F5R8) + union { + + /// bytewise access to F5R8 + uint8_t byte; + + /// bitwise access to register F5R8 + struct { + BITS FB : 8; // bits 0-7 + }; // F5R8 bitfield + + /// no register reset value + + } F5R8; + + + /// Page 5: CAN mailbox time stamp register high (CAN_MTSRH), see page 0 + + + /// Page 6: Reserved + + + /// Page 7: CAN mailbox time stamp register high (CAN_MTSRH), see page 0 + + }; // CAN paged register F + +} CAN_t; + +/// access to CAN SFR registers +#define sfr_CAN (*((CAN_t*) 0x5420)) +// undefine local macros +#undef BITS + +// required for C++ +#ifdef __cplusplus + } // extern "C" +#endif + +/*------------------------------------------------------------------------- + END OF MODULE DEFINITION FOR MULTIPLE INLUSION +-------------------------------------------------------------------------*/ +#endif // STM8S208RB_H diff --git a/examples/native-blink/src/main.c b/examples/native-blink/src/main.c new file mode 100644 index 0000000..c2c35a0 --- /dev/null +++ b/examples/native-blink/src/main.c @@ -0,0 +1,115 @@ +/********************** + Simple blink project w/o interrupts + + supported hardware: + - STM8S Discovery board (https://www.st.com/en/evaluation-tools/stm8s-discovery.html) + - NUCLEO-8S207K8 (https://www.st.com/en/evaluation-tools/nucleo-8s207k8.html) + - NUCLEO-8S208RB (https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html) + - STM8L Discovery board (https://www.st.com/en/evaluation-tools/stm8l-discovery.html) + - STM8-SO8 Discovery board (https://www.st.com/en/evaluation-tools/stm8-so8-disco.html) + - Sduino Uno (https://github.com/roybaer/sduino_uno) + - muBoard (http://www.cream-tea.de/presentations/160305_PiAndMore.pdf) + + Functionality: + - blink LED w/o ISR. Mainly for testing toolchain + - pass port structure to function +**********************/ + +/*---------------------------------------------------------- + SELECT BOARD +----------------------------------------------------------*/ +//Not needed for PlatformIO since the board definition file +//automatically activates macros by which we can identify it, +//like STM8S_NUCLEO_207K8 etc. + +//#define STM8S_DISCOVERY +//#define NUCLEO_8S207K8 +//#define NUCLEO_8S208RB +//#define STM8L_DISCOVERY +//#define STM8_SO8_DISCO_STM8S001 +//#define SDUINO +//#define MUBOARD + +/*---------------------------------------------------------- + INCLUDE FILES +----------------------------------------------------------*/ +#if defined(STM8S_DISCOVERY) + #include "STM8S105C6.h" + #define LED_PORT sfr_PORTD + #define LED_PIN PIN0 + //print this out as an info during compilation + #warning "[INFO] USING STM8S_DISCOVERY PIN MAP" +#elif defined(STM8S_NUCLEO_207K8) + #include "STM8S207K8.h" + #define LED_PORT sfr_PORTC + #define LED_PIN PIN5 + //print this out as an info during compilation + #warning "[INFO] USING NUCLEO_8S207K8 PIN MAP PORTC PIN5" +#elif defined(STM8S_NUCLEO_208RB) + #include "STM8S208RB.h" + #define LED_PORT sfr_PORTC + #define LED_PIN PIN5 + //print this out as an info during compilation + #warning "[INFO] USING NUCLEO_8S208RB PIN MAP PORTC PIN5" +#elif defined(STM8L_DISCOVERY) + #include "STM8L152C6.h" + #define LED_PORT sfr_PORTC + #define LED_PIN PIN7 +#elif defined(STM8_SO8_DISCO_STM8S001) + #include "STM8S001J3.h" + #define LED_PORT sfr_PORTA + #define LED_PIN PIN3 +#elif defined(SDUINO) + #include "STM8S105K6.h" + #define LED_PORT sfr_PORTC + #define LED_PIN PIN5 +#elif defined(MUBOARD) + #include "STM8S207MB.h" + #define LED_PORT sfr_PORTH + #define LED_PIN PIN2 +#else + #include "STM8S103F3.h" + #define LED_PORT sfr_PORTB + #define LED_PIN PIN5 + #warning "[INFO] USING STM8S103F3 PINMAP PORTB, PIN 5" +#endif + +// toggle specified pin. Pass port struct as pointer +void toggle_pin(PORT_t *port, uint8_t pin) { + + port->ODR.byte ^= pin; + +} // toggle_pin + +///////////////// +// main routine +///////////////// +void main (void) { + + uint32_t i = 0; + + // switch to 16MHz (default is 2MHz) + sfr_CLK.CKDIVR.byte = 0x00; + + // configure LED pin as output + LED_PORT.DDR.byte = LED_PIN; // input(=0) or output(=1) + LED_PORT.CR1.byte = LED_PIN; // input: 0=float, 1=pull-up; output: 0=open-drain, 1=push-pull + LED_PORT.CR2.byte = LED_PIN; // input: 0=no exint, 1=exint; output: 0=2MHz slope, 1=10MHz slope + + // main loop + while(1) { + + // toggle LED. Pass port struct as pointer + toggle_pin(&LED_PORT, LED_PIN); + + // simple wait ~500ms @ 16MHz + for (i=0; i<300000L; i++) + NOP(); + + } // main loop + +} // main + +/*----------------------------------------------------------------------------- + END OF MODULE +-----------------------------------------------------------------------------*/ diff --git a/examples/native-blink/test/README b/examples/native-blink/test/README new file mode 100644 index 0000000..b94d089 --- /dev/null +++ b/examples/native-blink/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PlatformIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PlatformIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html From 02402c7f8ba7df7ac59726ae55e14764986d26a7 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 23 Mar 2021 15:55:03 +0100 Subject: [PATCH 2/6] Switch to ststm8 platform --- examples/native-blink/platformio.ini | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/native-blink/platformio.ini b/examples/native-blink/platformio.ini index c19fae3..ecdfc53 100644 --- a/examples/native-blink/platformio.ini +++ b/examples/native-blink/platformio.ini @@ -9,14 +9,14 @@ ; https://docs.platformio.org/page/projectconf.html [env:stm8sblue] -platform = https://github.com/platformio/platform-ststm8.git +platform = ststm8 board = stm8sblue upload_protocol = stlinkv2 [env:nucleo_8s207k8] -platform = https://github.com/platformio/platform-ststm8.git +platform = ststm8 board = nucleo_8s207k8 [env:nucleo_8s208rb] -platform = https://github.com/platformio/platform-ststm8.git +platform = ststm8 board = nucleo_8s208rb From 745e46c1178b9ff346d2b6789fcf7f4f9b51f456 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 23 Mar 2021 16:00:06 +0100 Subject: [PATCH 3/6] Add example to AppVeyor --- appveyor.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/appveyor.yml b/appveyor.yml index bd0465f..115eb2a 100644 --- a/appveyor.yml +++ b/appveyor.yml @@ -8,6 +8,7 @@ environment: - PLATFORMIO_PROJECT_DIR: "examples/spl-blink" - PLATFORMIO_PROJECT_DIR: "examples/spl-flash" - PLATFORMIO_PROJECT_DIR: "examples/spl-uart" + - PLATFORMIO_PROJECT_DIR: "examples/native-blink" install: - cmd: git submodule update --init --recursive From c14c1c9411e2e09d9ea6e265cb5f4124f924e690 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 23 Mar 2021 16:01:11 +0100 Subject: [PATCH 4/6] Add example to Github Workflows --- .github/workflows/examples.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/examples.yml b/.github/workflows/examples.yml index 6cf7f01..6d5913d 100644 --- a/.github/workflows/examples.yml +++ b/.github/workflows/examples.yml @@ -16,6 +16,7 @@ jobs: - "examples/spl-blink" - "examples/spl-flash" - "examples/spl-uart" + - "examples/native-blink" runs-on: ${{ matrix.os }} steps: - uses: actions/checkout@v2 From 49dee26c0c2cb428fcd67ac5f25a8462a63e5a34 Mon Sep 17 00:00:00 2001 From: unknown Date: Tue, 23 Mar 2021 16:16:08 +0100 Subject: [PATCH 5/6] Correct project name and environment in READEM --- examples/native-blink/README.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/native-blink/README.rst b/examples/native-blink/README.rst index 3632d76..4f3c52a 100644 --- a/examples/native-blink/README.rst +++ b/examples/native-blink/README.rst @@ -20,7 +20,7 @@ How to build PlatformIO based project .. code-block:: bash # Change directory to example - > cd platform-ststm8/examples/spl-blink + > cd platform-ststm8/examples/native-blink # Build project > platformio run @@ -29,10 +29,10 @@ How to build PlatformIO based project > platformio run --target upload # Build specific environment - > platformio run -e stm8sdisco + > platformio run -e stm8sblue # Upload firmware for the specific environment - > platformio run -e stm8sdisco --target upload + > platformio run -e stm8sblue --target upload # Clean build files > platformio run --target clean From d77839ea9a8a706ed76c816387b0370a6507ed91 Mon Sep 17 00:00:00 2001 From: unknown Date: Thu, 25 Mar 2021 11:48:23 +0100 Subject: [PATCH 6/6] Use external reference to STM8_headers Sadly there's no tag that I can reference, and I don't want to assume everyone has git installed to reference a commit, so I use a referenze to the ZIP file of the master branch. --- examples/native-blink/LICENSE_STM8_HEADERS | 21 - examples/native-blink/README.rst | 4 +- examples/native-blink/platformio.ini | 5 + examples/native-blink/src/STM8S103F3.h | 4526 -------------- examples/native-blink/src/STM8S207K8.h | 4648 -------------- examples/native-blink/src/STM8S208RB.h | 6376 -------------------- 6 files changed, 7 insertions(+), 15573 deletions(-) delete mode 100644 examples/native-blink/LICENSE_STM8_HEADERS delete mode 100644 examples/native-blink/src/STM8S103F3.h delete mode 100644 examples/native-blink/src/STM8S207K8.h delete mode 100644 examples/native-blink/src/STM8S208RB.h diff --git a/examples/native-blink/LICENSE_STM8_HEADERS b/examples/native-blink/LICENSE_STM8_HEADERS deleted file mode 100644 index 41ef1a0..0000000 --- a/examples/native-blink/LICENSE_STM8_HEADERS +++ /dev/null @@ -1,21 +0,0 @@ -MIT License - -Copyright (c) 2020 Georg Icking-Konert - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in all -copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -SOFTWARE. diff --git a/examples/native-blink/README.rst b/examples/native-blink/README.rst index 4f3c52a..4dcc8bc 100644 --- a/examples/native-blink/README.rst +++ b/examples/native-blink/README.rst @@ -49,6 +49,6 @@ The pinmapping is such that the built-in LED of those boards is automatically us The project does not any framework like Arduino or SPL for compilation, hence no `framework = ..` line in the `platformio.ini`. Only one `.c` file and the right `.h` device header file is used. -The project uses a copy of the FOSS header files for the three devices from https://github.com/gicking/STM8_headers, which are placed under the MIT license. A copy of the license is included. +The project uses the FOSS header files from https://github.com/gicking/STM8_headers, which are placed under the MIT license. -If you wish to adapt this example for more chips and boards, add the appropriate header file from the referenced repository and include that header. \ No newline at end of file +If you wish to adapt this example for more chips and boards, add a new environment for your chip, find the appropriate header file from the referenced repository and include that header. \ No newline at end of file diff --git a/examples/native-blink/platformio.ini b/examples/native-blink/platformio.ini index ecdfc53..6e682cc 100644 --- a/examples/native-blink/platformio.ini +++ b/examples/native-blink/platformio.ini @@ -8,6 +8,11 @@ ; Please visit documentation for the other options and examples ; https://docs.platformio.org/page/projectconf.html +[env] +; baremetal STM8 device headers library +lib_deps = + https://github.com/gicking/STM8_headers/archive/refs/heads/master.zip + [env:stm8sblue] platform = ststm8 board = stm8sblue diff --git a/examples/native-blink/src/STM8S103F3.h b/examples/native-blink/src/STM8S103F3.h deleted file mode 100644 index c03f385..0000000 --- a/examples/native-blink/src/STM8S103F3.h +++ /dev/null @@ -1,4526 +0,0 @@ -/*------------------------------------------------------------------------- - - STM8S103F3.h - Device Declarations - - STM8S/STM8AF, low density without ROM bootloader - - Copyright (C) 2020, Georg Icking-Konert - - Mainstream Access line 8-bit MCU with 8 Kbytes Flash, 16 MHz CPU, integrated EEPROM - - datasheet: https://www.st.com/resource/en/datasheet/stm8s103f3.pdf - reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf - - MIT License - - Copyright (c) 2020 Georg Icking-Konert - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - SOFTWARE. - --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- - MODULE DEFINITION FOR MULTIPLE INCLUSION --------------------------------------------------------------------------*/ -#ifndef STM8S103F3_H -#define STM8S103F3_H - -// DEVICE NAME -#define DEVICE_STM8S103F3 - -// DEVICE FAMILY -#define FAMILY_STM8S - -// required for C++ -#ifdef __cplusplus - extern "C" { -#endif - - -/*------------------------------------------------------------------------- - INCLUDE FILES --------------------------------------------------------------------------*/ -#include - - -/*------------------------------------------------------------------------- - COMPILER SPECIFIC SETTINGS --------------------------------------------------------------------------*/ - -// Cosmic compiler -#if defined(__CSMC__) - - // macros to unify ISR declaration and implementation - #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine - #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine - - // definition of inline functions - #define INLINE @inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling - #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling - #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt - #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode - #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned int ///< data type in bit structs (follow C90 standard) - - -// IAR Compiler -#elif defined(__ICCSTM8__) - - // include intrinsic functions - #include - - // macros to unify ISR declaration and implementation - #define STRINGVECTOR(x) #x - #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) - #define ISR_HANDLER( a, b ) \ - _Pragma( VECTOR_ID( (b)+2 ) ) \ - __interrupt void (a)( void ) - #define ISR_HANDLER_TRAP(a) \ - _Pragma( VECTOR_ID( 1 ) ) \ - __interrupt void (a) (void) - - // definition of inline functions - #define INLINE static inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling - #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling - #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt - #define ENTER_HALT() __halt() ///< put controller to HALT mode - #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) - - -// SDCC compiler -#elif defined(__SDCC) - - // store SDCC version in preprocessor friendly way - #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ - + __SDCC_VERSION_MINOR * 100 \ - + __SDCC_VERSION_PATCH) - - // unify ISR declaration and implementation - #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine - #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 - #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine - #else - #error traps require SDCC >=3.4.3. Please update! - #endif - - // definition of inline functions - #define INLINE static inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling - #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling - #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt - #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode - #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned int ///< data type in bit structs (follow C90 standard) - -// unsupported compiler -> stop -#else - #error: compiler not supported -#endif - - -/*------------------------------------------------------------------------- - FOR CONVENIENT PIN ACCESS --------------------------------------------------------------------------*/ - -#define PIN0 0x01 -#define PIN1 0x02 -#define PIN2 0x04 -#define PIN3 0x08 -#define PIN4 0x10 -#define PIN5 0x20 -#define PIN6 0x40 -#define PIN7 0x80 - - -/*------------------------------------------------------------------------- - DEVICE MEMORY (size in bytes) --------------------------------------------------------------------------*/ - -// RAM -#define RAM_ADDR_START 0x000000 -#define RAM_ADDR_END 0x0003FF -#define RAM_SIZE 1024 - - -// FLASH -#define FLASH_ADDR_START 0x008000 -#define FLASH_ADDR_END 0x009FFF -#define FLASH_SIZE 8192 - - -// SFR1 -#define SFR1_ADDR_START 0x005000 -#define SFR1_ADDR_END 0x0057FF -#define SFR1_SIZE 2048 - - -// SFR2 -#define SFR2_ADDR_START 0x007F00 -#define SFR2_ADDR_END 0x007FFF -#define SFR2_SIZE 256 - - -// EEPROM -#define EEPROM_ADDR_START 0x004000 -#define EEPROM_ADDR_END 0x00427F -#define EEPROM_SIZE 640 - - -// OPTION -#define OPTION_ADDR_START 0x004800 -#define OPTION_ADDR_END 0x00480A -#define OPTION_SIZE 11 - - -// ID -#define ID_ADDR_START 0x004865 -#define ID_ADDR_END 0x004870 -#define ID_SIZE 12 - - -// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) -#define FLASH_ADDR_WIDTH 16 ///< width of address space -#define FLASH_POINTER_T uint16_t ///< address variable type - - -/*------------------------------------------------------------------------- - UNIQUE IDENTIFIER (size in bytes) --------------------------------------------------------------------------*/ - -#define UID_ADDR_START 0x4865 ///< start address of unique identifier -#define UID_SIZE 12 ///< size of unique identifier [B] -#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N - - -/*------------------------------------------------------------------------- - MISC OPTIONS --------------------------------------------------------------------------*/ - -/// LSI frequency measurement channel -#define LSI_MEASURE_TIM1_IC1 - - -/*------------------------------------------------------------------------- - ISR Vector Table (SDCC, IAR) - Notes: - - IAR has an IRQ offset of +2 compared to datasheet and below numbers - - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' - - different interrupt sources may share the same IRQ --------------------------------------------------------------------------*/ - -// interrupt IRQ -#define _TLI_VECTOR_ 0 -#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR -#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR -#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR -#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR -#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR -#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR -#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR -#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR -#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR -#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR -#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR -#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR -#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR -#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR -#define _TIM1_CAPCOM_BIF_VECTOR_ 11 ///< TIM1_CAPCOM_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_CAPCOM_TIF_VECTOR_ 11 ///< TIM1_CAPCOM_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR -#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR -#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR -#define _UART1_T_TC_VECTOR_ 17 ///< UART1_T_TC interrupt vector: enable: UART1_CR2.TCIEN, pending: UART1_SR.TC, priority: ITC_SPR5.VECT17SPR -#define _UART1_T_TXE_VECTOR_ 17 ///< UART1_T_TXE interrupt vector: enable: UART1_CR2.TIEN, pending: UART1_SR.TXE, priority: ITC_SPR5.VECT17SPR -#define _UART1_R_IDLE_VECTOR_ 18 ///< UART1_R_IDLE interrupt vector: enable: UART1_CR2.ILIEN, pending: UART1_SR.IDLE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_LBDF_VECTOR_ 18 ///< UART1_R_LBDF interrupt vector: enable: UART1_CR4.LBDIEN, pending: UART1_CR4.LBDF, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_OR_VECTOR_ 18 ///< UART1_R_OR interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.OR_LHE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_PE_VECTOR_ 18 ///< UART1_R_PE interrupt vector: enable: UART1_CR1.PIEN, pending: UART1_SR.PE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_RXNE_VECTOR_ 18 ///< UART1_R_RXNE interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.RXNE, priority: ITC_SPR5.VECT18SPR -#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR -#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR -#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR -#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR -#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR -#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR -#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR -#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR -#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR -#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR -#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR -#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR -#define _ADC1_AWDG_VECTOR_ 22 ///< ADC1_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS0_VECTOR_ 22 ///< ADC1_AWS0 interrupt vector: enable: ADC_AWCRL.AWEN0, pending: ADC_AWSRL.AWS0, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS1_VECTOR_ 22 ///< ADC1_AWS1 interrupt vector: enable: ADC_AWCRL.AWEN1, pending: ADC_AWSRL.AWS1, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS2_VECTOR_ 22 ///< ADC1_AWS2 interrupt vector: enable: ADC_AWCRL.AWEN2, pending: ADC_AWSRL.AWS2, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS3_VECTOR_ 22 ///< ADC1_AWS3 interrupt vector: enable: ADC_AWCRL.AWEN3, pending: ADC_AWSRL.AWS3, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS4_VECTOR_ 22 ///< ADC1_AWS4 interrupt vector: enable: ADC_AWCRL.AWEN4, pending: ADC_AWSRL.AWS4, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS5_VECTOR_ 22 ///< ADC1_AWS5 interrupt vector: enable: ADC_AWCRL.AWEN5, pending: ADC_AWSRL.AWS5, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS6_VECTOR_ 22 ///< ADC1_AWS6 interrupt vector: enable: ADC_AWCRL.AWEN6, pending: ADC_AWSRL.AWS6, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS7_VECTOR_ 22 ///< ADC1_AWS7 interrupt vector: enable: ADC_AWCRL.AWEN7, pending: ADC_AWSRL.AWS7, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS8_VECTOR_ 22 ///< ADC1_AWS8 interrupt vector: enable: ADC_AWCRH.AWEN8, pending: ADC_AWSRH.AWS8, priority: ITC_SPR6.VECT22SPR -#define _ADC1_AWS9_VECTOR_ 22 ///< ADC1_AWS9 interrupt vector: enable: ADC_AWCRH.AWEN9, pending: ADC_AWSRH.AWS9, priority: ITC_SPR6.VECT22SPR -#define _ADC1_EOC_VECTOR_ 22 ///< ADC1_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR -#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR -#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR -#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR - - -/*------------------------------------------------------------------------- - DEFINITION OF STM8 PERIPHERAL REGISTERS --------------------------------------------------------------------------*/ - -//------------------------ -// Module ADC1 -//------------------------ - -/** struct containing ADC1 module registers */ -typedef struct { - - /** ADC data buffer registers (DB0RH at 0x53e0) */ - union { - - /// bytewise access to DB0RH - uint8_t byte; - - /// bitwise access to register DB0RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB0RH bitfield - - /// register _ADC1_DB0RH reset value - #define sfr_ADC1_DB0RH_RESET_VALUE ((uint8_t) 0x00) - - } DB0RH; - - - /** ADC data buffer registers (DB0RL at 0x53e1) */ - union { - - /// bytewise access to DB0RL - uint8_t byte; - - /// bitwise access to register DB0RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB0RL bitfield - - /// register _ADC1_DB0RL reset value - #define sfr_ADC1_DB0RL_RESET_VALUE ((uint8_t) 0x00) - - } DB0RL; - - - /** ADC data buffer registers (DB1RH at 0x53e2) */ - union { - - /// bytewise access to DB1RH - uint8_t byte; - - /// bitwise access to register DB1RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB1RH bitfield - - /// register _ADC1_DB1RH reset value - #define sfr_ADC1_DB1RH_RESET_VALUE ((uint8_t) 0x00) - - } DB1RH; - - - /** ADC data buffer registers (DB1RL at 0x53e3) */ - union { - - /// bytewise access to DB1RL - uint8_t byte; - - /// bitwise access to register DB1RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB1RL bitfield - - /// register _ADC1_DB1RL reset value - #define sfr_ADC1_DB1RL_RESET_VALUE ((uint8_t) 0x00) - - } DB1RL; - - - /** ADC data buffer registers (DB2RH at 0x53e4) */ - union { - - /// bytewise access to DB2RH - uint8_t byte; - - /// bitwise access to register DB2RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB2RH bitfield - - /// register _ADC1_DB2RH reset value - #define sfr_ADC1_DB2RH_RESET_VALUE ((uint8_t) 0x00) - - } DB2RH; - - - /** ADC data buffer registers (DB2RL at 0x53e5) */ - union { - - /// bytewise access to DB2RL - uint8_t byte; - - /// bitwise access to register DB2RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB2RL bitfield - - /// register _ADC1_DB2RL reset value - #define sfr_ADC1_DB2RL_RESET_VALUE ((uint8_t) 0x00) - - } DB2RL; - - - /** ADC data buffer registers (DB3RH at 0x53e6) */ - union { - - /// bytewise access to DB3RH - uint8_t byte; - - /// bitwise access to register DB3RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB3RH bitfield - - /// register _ADC1_DB3RH reset value - #define sfr_ADC1_DB3RH_RESET_VALUE ((uint8_t) 0x00) - - } DB3RH; - - - /** ADC data buffer registers (DB3RL at 0x53e7) */ - union { - - /// bytewise access to DB3RL - uint8_t byte; - - /// bitwise access to register DB3RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB3RL bitfield - - /// register _ADC1_DB3RL reset value - #define sfr_ADC1_DB3RL_RESET_VALUE ((uint8_t) 0x00) - - } DB3RL; - - - /** ADC data buffer registers (DB4RH at 0x53e8) */ - union { - - /// bytewise access to DB4RH - uint8_t byte; - - /// bitwise access to register DB4RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB4RH bitfield - - /// register _ADC1_DB4RH reset value - #define sfr_ADC1_DB4RH_RESET_VALUE ((uint8_t) 0x00) - - } DB4RH; - - - /** ADC data buffer registers (DB4RL at 0x53e9) */ - union { - - /// bytewise access to DB4RL - uint8_t byte; - - /// bitwise access to register DB4RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB4RL bitfield - - /// register _ADC1_DB4RL reset value - #define sfr_ADC1_DB4RL_RESET_VALUE ((uint8_t) 0x00) - - } DB4RL; - - - /** ADC data buffer registers (DB5RH at 0x53ea) */ - union { - - /// bytewise access to DB5RH - uint8_t byte; - - /// bitwise access to register DB5RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB5RH bitfield - - /// register _ADC1_DB5RH reset value - #define sfr_ADC1_DB5RH_RESET_VALUE ((uint8_t) 0x00) - - } DB5RH; - - - /** ADC data buffer registers (DB5RL at 0x53eb) */ - union { - - /// bytewise access to DB5RL - uint8_t byte; - - /// bitwise access to register DB5RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB5RL bitfield - - /// register _ADC1_DB5RL reset value - #define sfr_ADC1_DB5RL_RESET_VALUE ((uint8_t) 0x00) - - } DB5RL; - - - /** ADC data buffer registers (DB6RH at 0x53ec) */ - union { - - /// bytewise access to DB6RH - uint8_t byte; - - /// bitwise access to register DB6RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB6RH bitfield - - /// register _ADC1_DB6RH reset value - #define sfr_ADC1_DB6RH_RESET_VALUE ((uint8_t) 0x00) - - } DB6RH; - - - /** ADC data buffer registers (DB6RL at 0x53ed) */ - union { - - /// bytewise access to DB6RL - uint8_t byte; - - /// bitwise access to register DB6RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB6RL bitfield - - /// register _ADC1_DB6RL reset value - #define sfr_ADC1_DB6RL_RESET_VALUE ((uint8_t) 0x00) - - } DB6RL; - - - /** ADC data buffer registers (DB7RH at 0x53ee) */ - union { - - /// bytewise access to DB7RH - uint8_t byte; - - /// bitwise access to register DB7RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB7RH bitfield - - /// register _ADC1_DB7RH reset value - #define sfr_ADC1_DB7RH_RESET_VALUE ((uint8_t) 0x00) - - } DB7RH; - - - /** ADC data buffer registers (DB7RL at 0x53ef) */ - union { - - /// bytewise access to DB7RL - uint8_t byte; - - /// bitwise access to register DB7RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB7RL bitfield - - /// register _ADC1_DB7RL reset value - #define sfr_ADC1_DB7RL_RESET_VALUE ((uint8_t) 0x00) - - } DB7RL; - - - /** ADC data buffer registers (DB8RH at 0x53f0) */ - union { - - /// bytewise access to DB8RH - uint8_t byte; - - /// bitwise access to register DB8RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB8RH bitfield - - /// register _ADC1_DB8RH reset value - #define sfr_ADC1_DB8RH_RESET_VALUE ((uint8_t) 0x00) - - } DB8RH; - - - /** ADC data buffer registers (DB8RL at 0x53f1) */ - union { - - /// bytewise access to DB8RL - uint8_t byte; - - /// bitwise access to register DB8RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB8RL bitfield - - /// register _ADC1_DB8RL reset value - #define sfr_ADC1_DB8RL_RESET_VALUE ((uint8_t) 0x00) - - } DB8RL; - - - /** ADC data buffer registers (DB9RH at 0x53f2) */ - union { - - /// bytewise access to DB9RH - uint8_t byte; - - /// bitwise access to register DB9RH - struct { - BITS DBH : 8; // bits 0-7 - }; // DB9RH bitfield - - /// register _ADC1_DB9RH reset value - #define sfr_ADC1_DB9RH_RESET_VALUE ((uint8_t) 0x00) - - } DB9RH; - - - /** ADC data buffer registers (DB9RL at 0x53f3) */ - union { - - /// bytewise access to DB9RL - uint8_t byte; - - /// bitwise access to register DB9RL - struct { - BITS DL : 8; // bits 0-7 - }; // DB9RL bitfield - - /// register _ADC1_DB9RL reset value - #define sfr_ADC1_DB9RL_RESET_VALUE ((uint8_t) 0x00) - - } DB9RL; - - - /// Reserved register (12B) - uint8_t Reserved_1[12]; - - - /** ADC control/status register (CSR at 0x5400) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// bitwise access to register CSR - struct { - BITS CH : 4; // bits 0-3 - BITS AWDIE : 1; // bit 4 - BITS EOCIE : 1; // bit 5 - BITS AWD : 1; // bit 6 - BITS EOC : 1; // bit 7 - }; // CSR bitfield - - /// register _ADC1_CSR reset value - #define sfr_ADC1_CSR_RESET_VALUE ((uint8_t) 0x00) - - } CSR; - - - /** ADC configuration register 1 (CR1 at 0x5401) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS ADON : 1; // bit 0 - BITS CONT : 1; // bit 1 - BITS : 2; // 2 bits - BITS SPSEL : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CR1 bitfield - - /// register _ADC1_CR1 reset value - #define sfr_ADC1_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** ADC configuration register 2 (CR2 at 0x5402) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS : 1; // 1 bit - BITS SCAN : 1; // bit 1 - BITS : 1; // 1 bit - BITS ALIGN : 1; // bit 3 - BITS EXTSEL : 2; // bits 4-5 - BITS EXTTRIG : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR2 bitfield - - /// register _ADC1_CR2 reset value - #define sfr_ADC1_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** ADC configuration register 3 (CR3 at 0x5403) */ - union { - - /// bytewise access to CR3 - uint8_t byte; - - /// bitwise access to register CR3 - struct { - BITS : 6; // 6 bits - BITS OVR : 1; // bit 6 - BITS DBUF : 1; // bit 7 - }; // CR3 bitfield - - /// register _ADC1_CR3 reset value - #define sfr_ADC1_CR3_RESET_VALUE ((uint8_t) 0x00) - - } CR3; - - - /** ADC data register high (DRH at 0x5404) */ - union { - - /// bytewise access to DRH - uint8_t byte; - - /// bitwise access to register DRH - struct { - BITS DH : 8; // bits 0-7 - }; // DRH bitfield - - /// register _ADC1_DRH reset value - #define sfr_ADC1_DRH_RESET_VALUE ((uint8_t) 0x00) - - } DRH; - - - /** ADC data register low (DRL at 0x5405) */ - union { - - /// bytewise access to DRL - uint8_t byte; - - /// bitwise access to register DRL - struct { - BITS DL : 8; // bits 0-7 - }; // DRL bitfield - - /// register _ADC1_DRL reset value - #define sfr_ADC1_DRL_RESET_VALUE ((uint8_t) 0x00) - - } DRL; - - - /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ - union { - - /// bytewise access to TDRH - uint8_t byte; - - /// bitwise access to register TDRH - struct { - BITS TD : 8; // bits 0-7 - }; // TDRH bitfield - - /// register _ADC1_TDRH reset value - #define sfr_ADC1_TDRH_RESET_VALUE ((uint8_t) 0x00) - - } TDRH; - - - /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ - union { - - /// bytewise access to TDRL - uint8_t byte; - - /// bitwise access to register TDRL - struct { - BITS TL : 8; // bits 0-7 - }; // TDRL bitfield - - /// register _ADC1_TDRL reset value - #define sfr_ADC1_TDRL_RESET_VALUE ((uint8_t) 0x00) - - } TDRL; - - - /** ADC high threshold register high (HTRH at 0x5408) */ - union { - - /// bytewise access to HTRH - uint8_t byte; - - /// bitwise access to register HTRH - struct { - BITS HT : 8; // bits 0-7 - }; // HTRH bitfield - - /// register _ADC1_HTRH reset value - #define sfr_ADC1_HTRH_RESET_VALUE ((uint8_t) 0x03) - - } HTRH; - - - /** ADC high threshold register low (HTRL at 0x5409) */ - union { - - /// bytewise access to HTRL - uint8_t byte; - - /// bitwise access to register HTRL - struct { - BITS HT : 2; // bits 0-1 - BITS : 6; // 6 bits - }; // HTRL bitfield - - /// register _ADC1_HTRL reset value - #define sfr_ADC1_HTRL_RESET_VALUE ((uint8_t) 0xFF) - - } HTRL; - - - /** ADC low threshold register high (LTRH at 0x540a) */ - union { - - /// bytewise access to LTRH - uint8_t byte; - - /// bitwise access to register LTRH - struct { - BITS LT : 8; // bits 0-7 - }; // LTRH bitfield - - /// register _ADC1_LTRH reset value - #define sfr_ADC1_LTRH_RESET_VALUE ((uint8_t) 0x00) - - } LTRH; - - - /** ADC low threshold register low (LTRL at 0x540b) */ - union { - - /// bytewise access to LTRL - uint8_t byte; - - /// bitwise access to register LTRL - struct { - BITS LT : 2; // bits 0-1 - BITS : 6; // 6 bits - }; // LTRL bitfield - - /// register _ADC1_LTRL reset value - #define sfr_ADC1_LTRL_RESET_VALUE ((uint8_t) 0x00) - - } LTRL; - - - /** ADC analog watchdog status register high (AWSRH at 0x540c) */ - union { - - /// bytewise access to AWSRH - uint8_t byte; - - /// bitwise access to register AWSRH - struct { - BITS AWS8 : 1; // bit 0 - BITS AWS9 : 1; // bit 1 - BITS : 6; // 6 bits - }; // AWSRH bitfield - - /// register _ADC1_AWSRH reset value - #define sfr_ADC1_AWSRH_RESET_VALUE ((uint8_t) 0x00) - - } AWSRH; - - - /** ADC analog watchdog status register low (AWSRL at 0x540d) */ - union { - - /// bytewise access to AWSRL - uint8_t byte; - - /// bitwise access to register AWSRL - struct { - BITS AWS0 : 1; // bit 0 - BITS AWS1 : 1; // bit 1 - BITS AWS2 : 1; // bit 2 - BITS AWS3 : 1; // bit 3 - BITS AWS4 : 1; // bit 4 - BITS AWS5 : 1; // bit 5 - BITS AWS6 : 1; // bit 6 - BITS AWS7 : 1; // bit 7 - }; // AWSRL bitfield - - /// register _ADC1_AWSRL reset value - #define sfr_ADC1_AWSRL_RESET_VALUE ((uint8_t) 0x00) - - } AWSRL; - - - /** ADC analog watchdog control register high (AWCRH at 0x540e) */ - union { - - /// bytewise access to AWCRH - uint8_t byte; - - /// bitwise access to register AWCRH - struct { - BITS AWEN8 : 1; // bit 0 - BITS AWEN9 : 1; // bit 1 - BITS : 6; // 6 bits - }; // AWCRH bitfield - - /// register _ADC1_AWCRH reset value - #define sfr_ADC1_AWCRH_RESET_VALUE ((uint8_t) 0x00) - - } AWCRH; - - - /** ADC analog watchdog control register low (AWCRL at 0x540f) */ - union { - - /// bytewise access to AWCRL - uint8_t byte; - - /// bitwise access to register AWCRL - struct { - BITS AWEN0 : 1; // bit 0 - BITS AWEN1 : 1; // bit 1 - BITS AWEN2 : 1; // bit 2 - BITS AWEN3 : 1; // bit 3 - BITS AWEN4 : 1; // bit 4 - BITS AWEN5 : 1; // bit 5 - BITS AWEN6 : 1; // bit 6 - BITS AWEN7 : 1; // bit 7 - }; // AWCRL bitfield - - /// register _ADC1_AWCRL reset value - #define sfr_ADC1_AWCRL_RESET_VALUE ((uint8_t) 0x00) - - } AWCRL; - -} ADC1_t; - -/// access to ADC1 SFR registers -#define sfr_ADC1 (*((ADC1_t*) 0x53e0)) - - -//------------------------ -// Module AWU -//------------------------ - -/** struct containing AWU module registers */ -typedef struct { - - /** AWU control/status register 1 (CSR1 at 0x50f0) */ - union { - - /// bytewise access to CSR1 - uint8_t byte; - - /// bitwise access to register CSR1 - struct { - BITS MSR : 1; // bit 0 - BITS : 3; // 3 bits - BITS AWUEN : 1; // bit 4 - BITS AWUF : 1; // bit 5 - BITS : 2; // 2 bits - }; // CSR1 bitfield - - /// register _AWU_CSR1 reset value - #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) - - } CSR1; - - - /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ - union { - - /// bytewise access to APR - uint8_t byte; - - /// bitwise access to register APR - struct { - BITS APR : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // APR bitfield - - /// register _AWU_APR reset value - #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) - - } APR; - - - /** AWU timebase selection register (TBR at 0x50f2) */ - union { - - /// bytewise access to TBR - uint8_t byte; - - /// bitwise access to register TBR - struct { - BITS AWUTB : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // TBR bitfield - - /// register _AWU_TBR reset value - #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) - - } TBR; - -} AWU_t; - -/// access to AWU SFR registers -#define sfr_AWU (*((AWU_t*) 0x50f0)) - - -//------------------------ -// Module BEEP -//------------------------ - -/** struct containing BEEP module registers */ -typedef struct { - - /** BEEP control/status register (CSR at 0x50f3) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// bitwise access to register CSR - struct { - BITS BEEPDIV : 5; // bits 0-4 - BITS BEEPEN : 1; // bit 5 - BITS BEEPSEL : 2; // bits 6-7 - }; // CSR bitfield - - /// register _BEEP_CSR reset value - #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) - - } CSR; - -} BEEP_t; - -/// access to BEEP SFR registers -#define sfr_BEEP (*((BEEP_t*) 0x50f3)) - - -//------------------------ -// Module CLK -//------------------------ - -/** struct containing CLK module registers */ -typedef struct { - - /** Internal clock control register (ICKR at 0x50c0) */ - union { - - /// bytewise access to ICKR - uint8_t byte; - - /// bitwise access to register ICKR - struct { - BITS HSIEN : 1; // bit 0 - BITS HSIRDY : 1; // bit 1 - BITS FHW : 1; // bit 2 - BITS LSIEN : 1; // bit 3 - BITS LSIRDY : 1; // bit 4 - BITS REGAH : 1; // bit 5 - BITS : 2; // 2 bits - }; // ICKR bitfield - - /// register _CLK_ICKR reset value - #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) - - } ICKR; - - - /** External clock control register (ECKR at 0x50c1) */ - union { - - /// bytewise access to ECKR - uint8_t byte; - - /// bitwise access to register ECKR - struct { - BITS HSEEN : 1; // bit 0 - BITS HSERDY : 1; // bit 1 - BITS : 6; // 6 bits - }; // ECKR bitfield - - /// register _CLK_ECKR reset value - #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) - - } ECKR; - - - /// Reserved register (1B) - uint8_t Reserved_1[1]; - - - /** Clock master status register (CMSR at 0x50c3) */ - union { - - /// bytewise access to CMSR - uint8_t byte; - - /// bitwise access to register CMSR - struct { - BITS CKM : 8; // bits 0-7 - }; // CMSR bitfield - - /// register _CLK_CMSR reset value - #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) - - } CMSR; - - - /** Clock master switch register (SWR at 0x50c4) */ - union { - - /// bytewise access to SWR - uint8_t byte; - - /// bitwise access to register SWR - struct { - BITS SWI : 8; // bits 0-7 - }; // SWR bitfield - - /// register _CLK_SWR reset value - #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) - - } SWR; - - - /** Clock switch control register (SWCR at 0x50c5) */ - union { - - /// bytewise access to SWCR - uint8_t byte; - - /// bitwise access to register SWCR - struct { - BITS SWBSY : 1; // bit 0 - BITS SWEN : 1; // bit 1 - BITS SWIEN : 1; // bit 2 - BITS SWIF : 1; // bit 3 - BITS : 4; // 4 bits - }; // SWCR bitfield - - /// register _CLK_SWCR reset value - #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) - - } SWCR; - - - /** Clock divider register (CKDIVR at 0x50c6) */ - union { - - /// bytewise access to CKDIVR - uint8_t byte; - - /// bitwise access to register CKDIVR - struct { - BITS CPUDIV : 3; // bits 0-2 - BITS HSIDIV : 2; // bits 3-4 - BITS : 3; // 3 bits - }; // CKDIVR bitfield - - /// register _CLK_CKDIVR reset value - #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) - - } CKDIVR; - - - /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ - union { - - /// bytewise access to PCKENR1 - uint8_t byte; - - /// bitwise access to register PCKENR1 - struct { - BITS PCKEN : 8; // bits 0-7 - }; // PCKENR1 bitfield - - /// register _CLK_PCKENR1 reset value - #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) - - } PCKENR1; - - - /** Clock security system register (CSSR at 0x50c8) */ - union { - - /// bytewise access to CSSR - uint8_t byte; - - /// bitwise access to register CSSR - struct { - BITS CSSEN : 1; // bit 0 - BITS AUX : 1; // bit 1 - BITS CSSDIE : 1; // bit 2 - BITS CSSD : 1; // bit 3 - BITS : 4; // 4 bits - }; // CSSR bitfield - - /// register _CLK_CSSR reset value - #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) - - } CSSR; - - - /** Configurable clock control register (CCOR at 0x50c9) */ - union { - - /// bytewise access to CCOR - uint8_t byte; - - /// bitwise access to register CCOR - struct { - BITS CCOEN : 1; // bit 0 - BITS CCOSEL : 4; // bits 1-4 - BITS CCORDY : 1; // bit 5 - BITS CC0BSY : 1; // bit 6 - BITS : 1; // 1 bit - }; // CCOR bitfield - - /// register _CLK_CCOR reset value - #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) - - } CCOR; - - - /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ - union { - - /// bytewise access to PCKENR2 - uint8_t byte; - - /// bitwise access to register PCKENR2 - struct { - BITS PCKEN2 : 8; // bits 0-7 - }; // PCKENR2 bitfield - - /// register _CLK_PCKENR2 reset value - #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) - - } PCKENR2; - - - /** CAN clock control register (CANCCR at 0x50cb) */ - union { - - /// bytewise access to CANCCR - uint8_t byte; - - /// bitwise access to register CANCCR - struct { - BITS CANDIV : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // CANCCR bitfield - - /// register _CLK_CANCCR reset value - #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) - - } CANCCR; - - - /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ - union { - - /// bytewise access to HSITRIMR - uint8_t byte; - - /// bitwise access to register HSITRIMR - struct { - BITS HSITRIM : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // HSITRIMR bitfield - - /// register _CLK_HSITRIMR reset value - #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) - - } HSITRIMR; - - - /** SWIM clock control register (SWIMCCR at 0x50cd) */ - union { - - /// bytewise access to SWIMCCR - uint8_t byte; - - /// bitwise access to register SWIMCCR - struct { - BITS SWIMCLK : 1; // bit 0 - BITS : 7; // 7 bits - }; // SWIMCCR bitfield - - /// register _CLK_SWIMCCR reset value - #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) - - } SWIMCCR; - -} CLK_t; - -/// access to CLK SFR registers -#define sfr_CLK (*((CLK_t*) 0x50c0)) - - -//------------------------ -// Module CPU -//------------------------ - -/** struct containing CPU module registers */ -typedef struct { - - /** Accumulator (A at 0x7f00) */ - union { - - /// bytewise access to A - uint8_t byte; - - /// skip bitwise access to register A - - /// register _CPU_A reset value - #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) - - } A; - - - /** Program counter extended (PCE at 0x7f01) */ - union { - - /// bytewise access to PCE - uint8_t byte; - - /// skip bitwise access to register PCE - - /// register _CPU_PCE reset value - #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) - - } PCE; - - - /** Program counter high (PCH at 0x7f02) */ - union { - - /// bytewise access to PCH - uint8_t byte; - - /// skip bitwise access to register PCH - - /// register _CPU_PCH reset value - #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) - - } PCH; - - - /** Program counter low (PCL at 0x7f03) */ - union { - - /// bytewise access to PCL - uint8_t byte; - - /// skip bitwise access to register PCL - - /// register _CPU_PCL reset value - #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) - - } PCL; - - - /** X index register high (XH at 0x7f04) */ - union { - - /// bytewise access to XH - uint8_t byte; - - /// skip bitwise access to register XH - - /// register _CPU_XH reset value - #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) - - } XH; - - - /** X index register low (XL at 0x7f05) */ - union { - - /// bytewise access to XL - uint8_t byte; - - /// skip bitwise access to register XL - - /// register _CPU_XL reset value - #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) - - } XL; - - - /** Y index register high (YH at 0x7f06) */ - union { - - /// bytewise access to YH - uint8_t byte; - - /// skip bitwise access to register YH - - /// register _CPU_YH reset value - #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) - - } YH; - - - /** Y index register low (YL at 0x7f07) */ - union { - - /// bytewise access to YL - uint8_t byte; - - /// skip bitwise access to register YL - - /// register _CPU_YL reset value - #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) - - } YL; - - - /** Stack pointer high (SPH at 0x7f08) */ - union { - - /// bytewise access to SPH - uint8_t byte; - - /// skip bitwise access to register SPH - - /// register _CPU_SPH reset value - #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x03) - - } SPH; - - - /** Stack pointer low (SPL at 0x7f09) */ - union { - - /// bytewise access to SPL - uint8_t byte; - - /// skip bitwise access to register SPL - - /// register _CPU_SPL reset value - #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) - - } SPL; - - - /** Condition code register (CCR at 0x7f0a) */ - union { - - /// bytewise access to CCR - uint8_t byte; - - /// bitwise access to register CCR - struct { - BITS C : 1; // bit 0 - BITS Z : 1; // bit 1 - BITS NF : 1; // bit 2 - BITS I0 : 1; // bit 3 - BITS H : 1; // bit 4 - BITS I1 : 1; // bit 5 - BITS : 1; // 1 bit - BITS V : 1; // bit 7 - }; // CCR bitfield - - /// register _CPU_CCR reset value - #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) - - } CCR; - - - /// Reserved register (85B) - uint8_t Reserved_1[85]; - - - /** Global configuration register (CFG_GCR at 0x7f60) */ - union { - - /// bytewise access to CFG_GCR - uint8_t byte; - - /// bitwise access to register CFG_GCR - struct { - BITS SWO : 1; // bit 0 - BITS AL : 1; // bit 1 - BITS : 6; // 6 bits - }; // CFG_GCR bitfield - - /// register _CPU_CFG_GCR reset value - #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) - - } CFG_GCR; - -} CPU_t; - -/// access to CPU SFR registers -#define sfr_CPU (*((CPU_t*) 0x7f00)) - - -//------------------------ -// Module DM -//------------------------ - -/** struct containing DM module registers */ -typedef struct { - - /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ - union { - - /// bytewise access to BK1RE - uint8_t byte; - - /// skip bitwise access to register BK1RE - - /// register _DM_BK1RE reset value - #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RE; - - - /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ - union { - - /// bytewise access to BK1RH - uint8_t byte; - - /// skip bitwise access to register BK1RH - - /// register _DM_BK1RH reset value - #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RH; - - - /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ - union { - - /// bytewise access to BK1RL - uint8_t byte; - - /// skip bitwise access to register BK1RL - - /// register _DM_BK1RL reset value - #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RL; - - - /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ - union { - - /// bytewise access to BK2RE - uint8_t byte; - - /// skip bitwise access to register BK2RE - - /// register _DM_BK2RE reset value - #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RE; - - - /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ - union { - - /// bytewise access to BK2RH - uint8_t byte; - - /// skip bitwise access to register BK2RH - - /// register _DM_BK2RH reset value - #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RH; - - - /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ - union { - - /// bytewise access to BK2RL - uint8_t byte; - - /// skip bitwise access to register BK2RL - - /// register _DM_BK2RL reset value - #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RL; - - - /** DM debug module control register 1 (CR1 at 0x7f96) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// skip bitwise access to register CR1 - - /// register _DM_CR1 reset value - #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** DM debug module control register 2 (CR2 at 0x7f97) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// skip bitwise access to register CR2 - - /// register _DM_CR2 reset value - #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ - union { - - /// bytewise access to CSR1 - uint8_t byte; - - /// skip bitwise access to register CSR1 - - /// register _DM_CSR1 reset value - #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) - - } CSR1; - - - /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ - union { - - /// bytewise access to CSR2 - uint8_t byte; - - /// skip bitwise access to register CSR2 - - /// register _DM_CSR2 reset value - #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) - - } CSR2; - - - /** DM enable function register (ENFCTR at 0x7f9a) */ - union { - - /// bytewise access to ENFCTR - uint8_t byte; - - /// skip bitwise access to register ENFCTR - - /// register _DM_ENFCTR reset value - #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) - - } ENFCTR; - -} DM_t; - -/// access to DM SFR registers -#define sfr_DM (*((DM_t*) 0x7f90)) - - -//------------------------ -// Module FLASH -//------------------------ - -/** struct containing FLASH module registers */ -typedef struct { - - /** Flash control register 1 (CR1 at 0x505a) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS FIX : 1; // bit 0 - BITS IE : 1; // bit 1 - BITS AHALT : 1; // bit 2 - BITS HALT : 1; // bit 3 - BITS : 4; // 4 bits - }; // CR1 bitfield - - /// register _FLASH_CR1 reset value - #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** Flash control register 2 (CR2 at 0x505b) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS PRG : 1; // bit 0 - BITS : 3; // 3 bits - BITS FPRG : 1; // bit 4 - BITS ERASE : 1; // bit 5 - BITS WPRG : 1; // bit 6 - BITS OPT : 1; // bit 7 - }; // CR2 bitfield - - /// register _FLASH_CR2 reset value - #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** Flash complementary control register 2 (NCR2 at 0x505c) */ - union { - - /// bytewise access to NCR2 - uint8_t byte; - - /// bitwise access to register NCR2 - struct { - BITS NPRG : 1; // bit 0 - BITS : 3; // 3 bits - BITS NFPRG : 1; // bit 4 - BITS NERASE : 1; // bit 5 - BITS NWPRG : 1; // bit 6 - BITS NOPT : 1; // bit 7 - }; // NCR2 bitfield - - /// register _FLASH_NCR2 reset value - #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) - - } NCR2; - - - /** Flash protection register (FPR at 0x505d) */ - union { - - /// bytewise access to FPR - uint8_t byte; - - /// bitwise access to register FPR - struct { - BITS WPB0 : 1; // bit 0 - BITS WPB1 : 1; // bit 1 - BITS WPB2 : 1; // bit 2 - BITS WPB3 : 1; // bit 3 - BITS WPB4 : 1; // bit 4 - BITS WPB5 : 1; // bit 5 - BITS : 2; // 2 bits - }; // FPR bitfield - - /// register _FLASH_FPR reset value - #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) - - } FPR; - - - /** Flash complementary protection register (NFPR at 0x505e) */ - union { - - /// bytewise access to NFPR - uint8_t byte; - - /// bitwise access to register NFPR - struct { - BITS NWPB0 : 1; // bit 0 - BITS NWPB1 : 1; // bit 1 - BITS NWPB2 : 1; // bit 2 - BITS NWPB3 : 1; // bit 3 - BITS NWPB4 : 1; // bit 4 - BITS NWPB5 : 1; // bit 5 - BITS : 2; // 2 bits - }; // NFPR bitfield - - /// register _FLASH_NFPR reset value - #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) - - } NFPR; - - - /** Flash in-application programming status register (IAPSR at 0x505f) */ - union { - - /// bytewise access to IAPSR - uint8_t byte; - - /// bitwise access to register IAPSR - struct { - BITS WR_PG_DIS : 1; // bit 0 - BITS PUL : 1; // bit 1 - BITS EOP : 1; // bit 2 - BITS DUL : 1; // bit 3 - BITS : 2; // 2 bits - BITS HVOFF : 1; // bit 6 - BITS : 1; // 1 bit - }; // IAPSR bitfield - - /// register _FLASH_IAPSR reset value - #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) - - } IAPSR; - - - /// Reserved register (2B) - uint8_t Reserved_1[2]; - - - /** Flash program memory unprotection register (PUKR at 0x5062) */ - union { - - /// bytewise access to PUKR - uint8_t byte; - - /// bitwise access to register PUKR - struct { - BITS MASS_PRG : 8; // bits 0-7 - }; // PUKR bitfield - - /// register _FLASH_PUKR reset value - #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) - - } PUKR; - - - /// Reserved register (1B) - uint8_t Reserved_2[1]; - - - /** Data EEPROM unprotection register (DUKR at 0x5064) */ - union { - - /// bytewise access to DUKR - uint8_t byte; - - /// bitwise access to register DUKR - struct { - BITS MASS_DATA : 8; // bits 0-7 - }; // DUKR bitfield - - /// register _FLASH_DUKR reset value - #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) - - } DUKR; - -} FLASH_t; - -/// access to FLASH SFR registers -#define sfr_FLASH (*((FLASH_t*) 0x505a)) - - -//------------------------ -// Module I2C -//------------------------ - -/** struct containing I2C module registers */ -typedef struct { - - /** I2C control register 1 (CR1 at 0x5210) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PE : 1; // bit 0 - BITS : 5; // 5 bits - BITS ENGC : 1; // bit 6 - BITS NOSTRETCH : 1; // bit 7 - }; // CR1 bitfield - - /// register _I2C_CR1 reset value - #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** I2C control register 2 (CR2 at 0x5211) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS START : 1; // bit 0 - BITS STOP : 1; // bit 1 - BITS ACK : 1; // bit 2 - BITS POS : 1; // bit 3 - BITS : 3; // 3 bits - BITS SWRST : 1; // bit 7 - }; // CR2 bitfield - - /// register _I2C_CR2 reset value - #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** I2C frequency register (FREQR at 0x5212) */ - union { - - /// bytewise access to FREQR - uint8_t byte; - - /// bitwise access to register FREQR - struct { - BITS FREQ : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // FREQR bitfield - - /// register _I2C_FREQR reset value - #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) - - } FREQR; - - - /** I2C Own address register low (OARL at 0x5213) */ - union { - - /// bytewise access to OARL - uint8_t byte; - - /// bitwise access to register OARL - struct { - BITS ADD0 : 1; // bit 0 - BITS ADD : 7; // bits 1-7 - }; // OARL bitfield - - /// register _I2C_OARL reset value - #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) - - } OARL; - - - /** I2C Own address register high (OARH at 0x5214) */ - union { - - /// bytewise access to OARH - uint8_t byte; - - /// bitwise access to register OARH - struct { - BITS : 1; // 1 bit - BITS ADD : 2; // bits 1-2 - BITS : 3; // 3 bits - BITS ADDCONF : 1; // bit 6 - BITS ADDMODE : 1; // bit 7 - }; // OARH bitfield - - /// register _I2C_OARH reset value - #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) - - } OARH; - - - /// Reserved register (1B) - uint8_t Reserved_1[1]; - - - /** I2C data register (DR at 0x5216) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _I2C_DR reset value - #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** I2C status register 1 (SR1 at 0x5217) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS SB : 1; // bit 0 - BITS ADDR : 1; // bit 1 - BITS BTF : 1; // bit 2 - BITS ADD10 : 1; // bit 3 - BITS STOPF : 1; // bit 4 - BITS : 1; // 1 bit - BITS RXNE : 1; // bit 6 - BITS TXE : 1; // bit 7 - }; // SR1 bitfield - - /// register _I2C_SR1 reset value - #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** I2C status register 2 (SR2 at 0x5218) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS BERR : 1; // bit 0 - BITS ARLO : 1; // bit 1 - BITS AF : 1; // bit 2 - BITS OVR : 1; // bit 3 - BITS : 1; // 1 bit - BITS WUFH : 1; // bit 5 - BITS : 2; // 2 bits - }; // SR2 bitfield - - /// register _I2C_SR2 reset value - #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** I2C status register 3 (SR3 at 0x5219) */ - union { - - /// bytewise access to SR3 - uint8_t byte; - - /// bitwise access to register SR3 - struct { - BITS MSL : 1; // bit 0 - BITS BUSY : 1; // bit 1 - BITS TRA : 1; // bit 2 - BITS : 1; // 1 bit - BITS GENCALL : 1; // bit 4 - BITS : 3; // 3 bits - }; // SR3 bitfield - - /// register _I2C_SR3 reset value - #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) - - } SR3; - - - /** I2C interrupt control register (ITR at 0x521a) */ - union { - - /// bytewise access to ITR - uint8_t byte; - - /// bitwise access to register ITR - struct { - BITS ITERREN : 1; // bit 0 - BITS ITEVTEN : 1; // bit 1 - BITS ITBUFEN : 1; // bit 2 - BITS : 5; // 5 bits - }; // ITR bitfield - - /// register _I2C_ITR reset value - #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) - - } ITR; - - - /** I2C Clock control register low (CCRL at 0x521b) */ - union { - - /// bytewise access to CCRL - uint8_t byte; - - /// bitwise access to register CCRL - struct { - BITS CCR : 8; // bits 0-7 - }; // CCRL bitfield - - /// register _I2C_CCRL reset value - #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) - - } CCRL; - - - /** I2C Clock control register high (CCRH at 0x521c) */ - union { - - /// bytewise access to CCRH - uint8_t byte; - - /// bitwise access to register CCRH - struct { - BITS CCR : 4; // bits 0-3 - BITS : 2; // 2 bits - BITS DUTY : 1; // bit 6 - BITS F_S : 1; // bit 7 - }; // CCRH bitfield - - /// register _I2C_CCRH reset value - #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) - - } CCRH; - - - /** I2C TRISE register (TRISER at 0x521d) */ - union { - - /// bytewise access to TRISER - uint8_t byte; - - /// bitwise access to register TRISER - struct { - BITS TRISE : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // TRISER bitfield - - /// register _I2C_TRISER reset value - #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) - - } TRISER; - - - /** I2C packet error checking register (PECR at 0x521e) */ - union { - - /// bytewise access to PECR - uint8_t byte; - - /// bitwise access to register PECR - struct { - BITS PEC : 8; // bits 0-7 - }; // PECR bitfield - - /// register _I2C_PECR reset value - #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) - - } PECR; - -} I2C_t; - -/// access to I2C SFR registers -#define sfr_I2C (*((I2C_t*) 0x5210)) - - -//------------------------ -// Module ITC -//------------------------ - -/** struct containing ITC module registers */ -typedef struct { - - /** External interrupt control register 1 (CR1 at 0x50a0) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PAIS : 2; // bits 0-1 - BITS PBIS : 2; // bits 2-3 - BITS PCIS : 2; // bits 4-5 - BITS PDIS : 2; // bits 6-7 - }; // CR1 bitfield - - /// register _ITC_CR1 reset value - #define sfr_ITC_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** External interrupt control register 2 (CR2 at 0x50a1) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS PEIS : 2; // bits 0-1 - BITS TLIS : 1; // bit 2 - BITS : 5; // 5 bits - }; // CR2 bitfield - - /// register _ITC_CR2 reset value - #define sfr_ITC_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /// Reserved register (17B) - uint8_t Reserved_1[17]; - - - /** Reset status register (RST_SR at 0x50b3) */ - union { - - /// bytewise access to RST_SR - uint8_t byte; - - /// bitwise access to register RST_SR - struct { - BITS WWDGF : 1; // bit 0 - BITS IWDGF : 1; // bit 1 - BITS ILLOPF : 1; // bit 2 - BITS SWIMF : 1; // bit 3 - BITS EMCF : 1; // bit 4 - BITS : 3; // 3 bits - }; // RST_SR bitfield - - /// register _ITC_RST_SR reset value - #define sfr_ITC_RST_SR_RESET_VALUE ((uint8_t) 0x00) - - } RST_SR; - - - /// Reserved register (11964B) - uint8_t Reserved_2[11964]; - - - /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ - union { - - /// bytewise access to SPR1 - uint8_t byte; - - /// bitwise access to register SPR1 - struct { - BITS VECT0SPR : 2; // bits 0-1 - BITS VECT1SPR : 2; // bits 2-3 - BITS VECT2SPR : 2; // bits 4-5 - BITS VECT3SPR : 2; // bits 6-7 - }; // SPR1 bitfield - - /// register _ITC_SPR1 reset value - #define sfr_ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF) - - } SPR1; - - - /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ - union { - - /// bytewise access to SPR2 - uint8_t byte; - - /// bitwise access to register SPR2 - struct { - BITS VECT4SPR : 2; // bits 0-1 - BITS VECT5SPR : 2; // bits 2-3 - BITS VECT6SPR : 2; // bits 4-5 - BITS VECT7SPR : 2; // bits 6-7 - }; // SPR2 bitfield - - /// register _ITC_SPR2 reset value - #define sfr_ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF) - - } SPR2; - - - /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ - union { - - /// bytewise access to SPR3 - uint8_t byte; - - /// bitwise access to register SPR3 - struct { - BITS VECT8SPR : 2; // bits 0-1 - BITS VECT9SPR : 2; // bits 2-3 - BITS VECT10SPR : 2; // bits 4-5 - BITS VECT11SPR : 2; // bits 6-7 - }; // SPR3 bitfield - - /// register _ITC_SPR3 reset value - #define sfr_ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF) - - } SPR3; - - - /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ - union { - - /// bytewise access to SPR4 - uint8_t byte; - - /// bitwise access to register SPR4 - struct { - BITS VECT12SPR : 2; // bits 0-1 - BITS VECT13SPR : 2; // bits 2-3 - BITS VECT14SPR : 2; // bits 4-5 - BITS VECT15SPR : 2; // bits 6-7 - }; // SPR4 bitfield - - /// register _ITC_SPR4 reset value - #define sfr_ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF) - - } SPR4; - - - /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ - union { - - /// bytewise access to SPR5 - uint8_t byte; - - /// bitwise access to register SPR5 - struct { - BITS VECT16SPR : 2; // bits 0-1 - BITS VECT17SPR : 2; // bits 2-3 - BITS VECT18SPR : 2; // bits 4-5 - BITS VECT19SPR : 2; // bits 6-7 - }; // SPR5 bitfield - - /// register _ITC_SPR5 reset value - #define sfr_ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF) - - } SPR5; - - - /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ - union { - - /// bytewise access to SPR6 - uint8_t byte; - - /// bitwise access to register SPR6 - struct { - BITS VECT20SPR : 2; // bits 0-1 - BITS VECT21SPR : 2; // bits 2-3 - BITS VECT22SPR : 2; // bits 4-5 - BITS VECT23SPR : 2; // bits 6-7 - }; // SPR6 bitfield - - /// register _ITC_SPR6 reset value - #define sfr_ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF) - - } SPR6; - - - /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ - union { - - /// bytewise access to SPR7 - uint8_t byte; - - /// bitwise access to register SPR7 - struct { - BITS VECT24SPR : 2; // bits 0-1 - BITS VECT25SPR : 2; // bits 2-3 - BITS VECT26SPR : 2; // bits 4-5 - BITS VECT27SPR : 2; // bits 6-7 - }; // SPR7 bitfield - - /// register _ITC_SPR7 reset value - #define sfr_ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF) - - } SPR7; - - - /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ - union { - - /// bytewise access to SPR8 - uint8_t byte; - - /// bitwise access to register SPR8 - struct { - BITS VECT28SPR : 2; // bits 0-1 - BITS VECT29SPR : 2; // bits 2-3 - BITS : 4; // 4 bits - }; // SPR8 bitfield - - /// register _ITC_SPR8 reset value - #define sfr_ITC_SPR8_RESET_VALUE ((uint8_t) 0xFF) - - } SPR8; - -} ITC_t; - -/// access to ITC SFR registers -#define sfr_ITC (*((ITC_t*) 0x50a0)) - - -//------------------------ -// Module IWDG -//------------------------ - -/** struct containing IWDG module registers */ -typedef struct { - - /** IWDG key register (KR at 0x50e0) */ - union { - - /// bytewise access to KR - uint8_t byte; - - /// bitwise access to register KR - struct { - BITS KEY : 8; // bits 0-7 - }; // KR bitfield - - /// register _IWDG_KR reset value - #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) - - } KR; - - - /** IWDG prescaler register (PR at 0x50e1) */ - union { - - /// bytewise access to PR - uint8_t byte; - - /// bitwise access to register PR - struct { - BITS PR : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // PR bitfield - - /// register _IWDG_PR reset value - #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) - - } PR; - - - /** IWDG reload register (RLR at 0x50e2) */ - union { - - /// bytewise access to RLR - uint8_t byte; - - /// bitwise access to register RLR - struct { - BITS RL : 8; // bits 0-7 - }; // RLR bitfield - - /// register _IWDG_RLR reset value - #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) - - } RLR; - -} IWDG_t; - -/// access to IWDG SFR registers -#define sfr_IWDG (*((IWDG_t*) 0x50e0)) - - -//------------------------ -// Module OPT -//------------------------ - -/** struct containing OPT module registers */ -typedef struct { - - /** Read-out protection (ROP) (OPT0 at 0x4800) */ - union { - - /// bytewise access to OPT0 - uint8_t byte; - - /// skip bitwise access to register OPT0 - - /// register _OPT_OPT0 reset value - #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) - - } OPT0; - - - /** User boot code (UBC) (OPT1 at 0x4801) */ - union { - - /// bytewise access to OPT1 - uint8_t byte; - - /// skip bitwise access to register OPT1 - - /// register _OPT_OPT1 reset value - #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) - - } OPT1; - - - /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ - union { - - /// bytewise access to NOPT1 - uint8_t byte; - - /// skip bitwise access to register NOPT1 - - /// register _OPT_NOPT1 reset value - #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT1; - - - /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ - union { - - /// bytewise access to OPT2 - uint8_t byte; - - /// skip bitwise access to register OPT2 - - /// register _OPT_OPT2 reset value - #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) - - } OPT2; - - - /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ - union { - - /// bytewise access to NOPT2 - uint8_t byte; - - /// skip bitwise access to register NOPT2 - - /// register _OPT_NOPT2 reset value - #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT2; - - - /** Misc. option (OPT3 at 0x4805) */ - union { - - /// bytewise access to OPT3 - uint8_t byte; - - /// skip bitwise access to register OPT3 - - /// register _OPT_OPT3 reset value - #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) - - } OPT3; - - - /** Misc. option (complementary byte) (NOPT3 at 0x4806) */ - union { - - /// bytewise access to NOPT3 - uint8_t byte; - - /// skip bitwise access to register NOPT3 - - /// register _OPT_NOPT3 reset value - #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT3; - - - /** Clock option (OPT4 at 0x4807) */ - union { - - /// bytewise access to OPT4 - uint8_t byte; - - /// skip bitwise access to register OPT4 - - /// register _OPT_OPT4 reset value - #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) - - } OPT4; - - - /** Clock option (complementary byte) (NOPT4 at 0x4808) */ - union { - - /// bytewise access to NOPT4 - uint8_t byte; - - /// skip bitwise access to register NOPT4 - - /// register _OPT_NOPT4 reset value - #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT4; - - - /** HSE clock startup (OPT5 at 0x4809) */ - union { - - /// bytewise access to OPT5 - uint8_t byte; - - /// skip bitwise access to register OPT5 - - /// register _OPT_OPT5 reset value - #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) - - } OPT5; - - - /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ - union { - - /// bytewise access to NOPT5 - uint8_t byte; - - /// skip bitwise access to register NOPT5 - - /// register _OPT_NOPT5 reset value - #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT5; - -} OPT_t; - -/// access to OPT SFR registers -#define sfr_OPT (*((OPT_t*) 0x4800)) - - -//------------------------ -// Module PORT -//------------------------ - -/** struct containing PORTA module registers */ -typedef struct { - - /** Port A data output latch register (ODR at 0x5000) */ - union { - - /// bytewise access to ODR - uint8_t byte; - - /// bitwise access to register ODR - struct { - BITS ODR0 : 1; // bit 0 - BITS ODR1 : 1; // bit 1 - BITS ODR2 : 1; // bit 2 - BITS ODR3 : 1; // bit 3 - BITS ODR4 : 1; // bit 4 - BITS ODR5 : 1; // bit 5 - BITS ODR6 : 1; // bit 6 - BITS ODR7 : 1; // bit 7 - }; // ODR bitfield - - /// register _PORT_ODR reset value - #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) - - } ODR; - - - /** Port A input pin value register (IDR at 0x5001) */ - union { - - /// bytewise access to IDR - uint8_t byte; - - /// bitwise access to register IDR - struct { - BITS IDR0 : 1; // bit 0 - BITS IDR1 : 1; // bit 1 - BITS IDR2 : 1; // bit 2 - BITS IDR3 : 1; // bit 3 - BITS IDR4 : 1; // bit 4 - BITS IDR5 : 1; // bit 5 - BITS IDR6 : 1; // bit 6 - BITS IDR7 : 1; // bit 7 - }; // IDR bitfield - - /// register _PORT_IDR reset value - #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) - - } IDR; - - - /** Port A data direction register (DDR at 0x5002) */ - union { - - /// bytewise access to DDR - uint8_t byte; - - /// bitwise access to register DDR - struct { - BITS DDR0 : 1; // bit 0 - BITS DDR1 : 1; // bit 1 - BITS DDR2 : 1; // bit 2 - BITS DDR3 : 1; // bit 3 - BITS DDR4 : 1; // bit 4 - BITS DDR5 : 1; // bit 5 - BITS DDR6 : 1; // bit 6 - BITS DDR7 : 1; // bit 7 - }; // DDR bitfield - - /// register _PORT_DDR reset value - #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) - - } DDR; - - - /** Port A control register 1 (CR1 at 0x5003) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS C10 : 1; // bit 0 - BITS C11 : 1; // bit 1 - BITS C12 : 1; // bit 2 - BITS C13 : 1; // bit 3 - BITS C14 : 1; // bit 4 - BITS C15 : 1; // bit 5 - BITS C16 : 1; // bit 6 - BITS C17 : 1; // bit 7 - }; // CR1 bitfield - - /// register _PORT_CR1 reset value - #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** Port A control register 2 (CR2 at 0x5004) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS C20 : 1; // bit 0 - BITS C21 : 1; // bit 1 - BITS C22 : 1; // bit 2 - BITS C23 : 1; // bit 3 - BITS C24 : 1; // bit 4 - BITS C25 : 1; // bit 5 - BITS C26 : 1; // bit 6 - BITS C27 : 1; // bit 7 - }; // CR2 bitfield - - /// register _PORT_CR2 reset value - #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - -} PORT_t; - -/// access to PORTA SFR registers -#define sfr_PORTA (*((PORT_t*) 0x5000)) - - -/// access to PORTB SFR registers -#define sfr_PORTB (*((PORT_t*) 0x5005)) - - -/// access to PORTC SFR registers -#define sfr_PORTC (*((PORT_t*) 0x500a)) - - -/// access to PORTD SFR registers -#define sfr_PORTD (*((PORT_t*) 0x500f)) - - -/// access to PORTE SFR registers -#define sfr_PORTE (*((PORT_t*) 0x5014)) - - -/// access to PORTF SFR registers -#define sfr_PORTF (*((PORT_t*) 0x5019)) - - -//------------------------ -// Module SPI -//------------------------ - -/** struct containing SPI module registers */ -typedef struct { - - /** SPI control register 1 (CR1 at 0x5200) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CPHA : 1; // bit 0 - BITS CPOL : 1; // bit 1 - BITS MSTR : 1; // bit 2 - BITS BR : 3; // bits 3-5 - BITS SPE : 1; // bit 6 - BITS LSBFIRST : 1; // bit 7 - }; // CR1 bitfield - - /// register _SPI_CR1 reset value - #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** SPI control register 2 (CR2 at 0x5201) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS SSI : 1; // bit 0 - BITS SSM : 1; // bit 1 - BITS RXONLY : 1; // bit 2 - BITS : 1; // 1 bit - BITS CRCNEXT : 1; // bit 4 - BITS CECEN : 1; // bit 5 - BITS BDOE : 1; // bit 6 - BITS BDM : 1; // bit 7 - }; // CR2 bitfield - - /// register _SPI_CR2 reset value - #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** SPI interrupt control register (ICR at 0x5202) */ - union { - - /// bytewise access to ICR - uint8_t byte; - - /// bitwise access to register ICR - struct { - BITS : 4; // 4 bits - BITS WKIE : 1; // bit 4 - BITS ERRIE : 1; // bit 5 - BITS RXIE : 1; // bit 6 - BITS TXIE : 1; // bit 7 - }; // ICR bitfield - - /// register _SPI_ICR reset value - #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) - - } ICR; - - - /** SPI status register (SR at 0x5203) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS RXNE : 1; // bit 0 - BITS TXE : 1; // bit 1 - BITS : 1; // 1 bit - BITS WKUP : 1; // bit 3 - BITS CRCERR : 1; // bit 4 - BITS MODF : 1; // bit 5 - BITS OVR : 1; // bit 6 - BITS BSY : 1; // bit 7 - }; // SR bitfield - - /// register _SPI_SR reset value - #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) - - } SR; - - - /** SPI data register (DR at 0x5204) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _SPI_DR reset value - #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** SPI CRC polynomial register (CRCPR at 0x5205) */ - union { - - /// bytewise access to CRCPR - uint8_t byte; - - /// bitwise access to register CRCPR - struct { - BITS CRCPOLY : 8; // bits 0-7 - }; // CRCPR bitfield - - /// register _SPI_CRCPR reset value - #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) - - } CRCPR; - - - /** SPI Rx CRC register (RXCRCR at 0x5206) */ - union { - - /// bytewise access to RXCRCR - uint8_t byte; - - /// bitwise access to register RXCRCR - struct { - BITS RXCRC : 8; // bits 0-7 - }; // RXCRCR bitfield - - /// register _SPI_RXCRCR reset value - #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) - - } RXCRCR; - - - /** SPI Tx CRC register (TXCRCR at 0x5207) */ - union { - - /// bytewise access to TXCRCR - uint8_t byte; - - /// bitwise access to register TXCRCR - struct { - BITS TXCRC : 8; // bits 0-7 - }; // TXCRCR bitfield - - /// register _SPI_TXCRCR reset value - #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) - - } TXCRCR; - -} SPI_t; - -/// access to SPI SFR registers -#define sfr_SPI (*((SPI_t*) 0x5200)) - - -//------------------------ -// Module SWIM -//------------------------ - -/** struct containing SWIM module registers */ -typedef struct { - - /** SWIM control status register (CSR at 0x7f80) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// skip bitwise access to register CSR - - /// register _SWIM_CSR reset value - #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) - - } CSR; - -} SWIM_t; - -/// access to SWIM SFR registers -#define sfr_SWIM (*((SWIM_t*) 0x7f80)) - - -//------------------------ -// Module TIM1 -//------------------------ - -/** struct containing TIM1 module registers */ -typedef struct { - - /** TIM1 control register 1 (CR1 at 0x5250) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS DIR : 1; // bit 4 - BITS CMS : 2; // bits 5-6 - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM1_CR1 reset value - #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM1 control register 2 (CR2 at 0x5251) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS CCPG : 1; // bit 0 - BITS : 1; // 1 bit - BITS COMS : 1; // bit 2 - BITS : 1; // 1 bit - BITS MMS : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CR2 bitfield - - /// register _TIM1_CR2 reset value - #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** TIM1 slave mode control register (SMCR at 0x5252) */ - union { - - /// bytewise access to SMCR - uint8_t byte; - - /// bitwise access to register SMCR - struct { - BITS SMS : 3; // bits 0-2 - BITS : 1; // 1 bit - BITS TS : 3; // bits 4-6 - BITS MSM : 1; // bit 7 - }; // SMCR bitfield - - /// register _TIM1_SMCR reset value - #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) - - } SMCR; - - - /** TIM1 external trigger register (ETR at 0x5253) */ - union { - - /// bytewise access to ETR - uint8_t byte; - - /// bitwise access to register ETR - struct { - BITS ETF : 4; // bits 0-3 - BITS ETPS : 2; // bits 4-5 - BITS ECE : 1; // bit 6 - BITS ETP : 1; // bit 7 - }; // ETR bitfield - - /// register _TIM1_ETR reset value - #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) - - } ETR; - - - /** TIM1 interrupt enable register (IER at 0x5254) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS CC1IE : 1; // bit 1 - BITS CC2IE : 1; // bit 2 - BITS CC3IE : 1; // bit 3 - BITS CC4IE : 1; // bit 4 - BITS COMIE : 1; // bit 5 - BITS TIE : 1; // bit 6 - BITS BIE : 1; // bit 7 - }; // IER bitfield - - /// register _TIM1_IER reset value - #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM1 status register 1 (SR1 at 0x5255) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS UIF : 1; // bit 0 - BITS CC1IF : 1; // bit 1 - BITS CC2IF : 1; // bit 2 - BITS CC3IF : 1; // bit 3 - BITS CC4IF : 1; // bit 4 - BITS COMIF : 1; // bit 5 - BITS TIF : 1; // bit 6 - BITS BIF : 1; // bit 7 - }; // SR1 bitfield - - /// register _TIM1_SR1 reset value - #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** TIM1 status register 2 (SR2 at 0x5256) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS : 1; // 1 bit - BITS CC1OF : 1; // bit 1 - BITS CC2OF : 1; // bit 2 - BITS CC3OF : 1; // bit 3 - BITS CC4OF : 1; // bit 4 - BITS : 3; // 3 bits - }; // SR2 bitfield - - /// register _TIM1_SR2 reset value - #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** TIM1 event generation register (EGR at 0x5257) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS CC1G : 1; // bit 1 - BITS CC2G : 1; // bit 2 - BITS CC3G : 1; // bit 3 - BITS CC4G : 1; // bit 4 - BITS COMG : 1; // bit 5 - BITS TG : 1; // bit 6 - BITS BG : 1; // bit 7 - }; // EGR bitfield - - /// register _TIM1_EGR reset value - #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ - union { - - /// bytewise access to CCMR1 - uint8_t byte; - - /// bitwise access to register CCMR1 - struct { - BITS CC1S : 2; // bits 0-1 - BITS OC1FE : 1; // bit 2 - BITS OC1PE : 1; // bit 3 - BITS OC1M : 3; // bits 4-6 - BITS OC1CE : 1; // bit 7 - }; // CCMR1 bitfield - - /// register _TIM1_CCMR1 reset value - #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) - - } CCMR1; - - - /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ - union { - - /// bytewise access to CCMR2 - uint8_t byte; - - /// bitwise access to register CCMR2 - struct { - BITS CC2S : 2; // bits 0-1 - BITS OC2FE : 1; // bit 2 - BITS OC2PE : 1; // bit 3 - BITS OC2M : 3; // bits 4-6 - BITS OC2CE : 1; // bit 7 - }; // CCMR2 bitfield - - /// register _TIM1_CCMR2 reset value - #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) - - } CCMR2; - - - /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ - union { - - /// bytewise access to CCMR3 - uint8_t byte; - - /// bitwise access to register CCMR3 - struct { - BITS CC3S : 2; // bits 0-1 - BITS OC3FE : 1; // bit 2 - BITS OC3PE : 1; // bit 3 - BITS OC3M : 3; // bits 4-6 - BITS OC3CE : 1; // bit 7 - }; // CCMR3 bitfield - - /// register _TIM1_CCMR3 reset value - #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) - - } CCMR3; - - - /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ - union { - - /// bytewise access to CCMR4 - uint8_t byte; - - /// bitwise access to register CCMR4 - struct { - BITS CC4S : 2; // bits 0-1 - BITS OC4FE : 1; // bit 2 - BITS OC4PE : 1; // bit 3 - BITS OC4M : 3; // bits 4-6 - BITS OC4CE : 1; // bit 7 - }; // CCMR4 bitfield - - /// register _TIM1_CCMR4 reset value - #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) - - } CCMR4; - - - /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ - union { - - /// bytewise access to CCER1 - uint8_t byte; - - /// bitwise access to register CCER1 - struct { - BITS CC1E : 1; // bit 0 - BITS CC1P : 1; // bit 1 - BITS CC1NE : 1; // bit 2 - BITS CC1NP : 1; // bit 3 - BITS CC2E : 1; // bit 4 - BITS CC2P : 1; // bit 5 - BITS CC2NE : 1; // bit 6 - BITS CC2NP : 1; // bit 7 - }; // CCER1 bitfield - - /// register _TIM1_CCER1 reset value - #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) - - } CCER1; - - - /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ - union { - - /// bytewise access to CCER2 - uint8_t byte; - - /// bitwise access to register CCER2 - struct { - BITS CC3E : 1; // bit 0 - BITS CC3P : 1; // bit 1 - BITS CC3NE : 1; // bit 2 - BITS CC3NP : 1; // bit 3 - BITS CC4E : 1; // bit 4 - BITS CC4P : 1; // bit 5 - BITS : 2; // 2 bits - }; // CCER2 bitfield - - /// register _TIM1_CCER2 reset value - #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) - - } CCER2; - - - /** TIM1 counter high (CNTRH at 0x525e) */ - union { - - /// bytewise access to CNTRH - uint8_t byte; - - /// bitwise access to register CNTRH - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRH bitfield - - /// register _TIM1_CNTRH reset value - #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) - - } CNTRH; - - - /** TIM1 counter low (CNTRL at 0x525f) */ - union { - - /// bytewise access to CNTRL - uint8_t byte; - - /// bitwise access to register CNTRL - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRL bitfield - - /// register _TIM1_CNTRL reset value - #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) - - } CNTRL; - - - /** TIM1 prescaler register high (PSCRH at 0x5260) */ - union { - - /// bytewise access to PSCRH - uint8_t byte; - - /// bitwise access to register PSCRH - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCRH bitfield - - /// register _TIM1_PSCRH reset value - #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) - - } PSCRH; - - - /** TIM1 prescaler register low (PSCRL at 0x5261) */ - union { - - /// bytewise access to PSCRL - uint8_t byte; - - /// bitwise access to register PSCRL - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCRL bitfield - - /// register _TIM1_PSCRL reset value - #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) - - } PSCRL; - - - /** TIM1 auto-reload register high (ARRH at 0x5262) */ - union { - - /// bytewise access to ARRH - uint8_t byte; - - /// bitwise access to register ARRH - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRH bitfield - - /// register _TIM1_ARRH reset value - #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) - - } ARRH; - - - /** TIM1 auto-reload register low (ARRL at 0x5263) */ - union { - - /// bytewise access to ARRL - uint8_t byte; - - /// bitwise access to register ARRL - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRL bitfield - - /// register _TIM1_ARRL reset value - #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) - - } ARRL; - - - /** TIM1 repetition counter register (RCR at 0x5264) */ - union { - - /// bytewise access to RCR - uint8_t byte; - - /// bitwise access to register RCR - struct { - BITS REP : 8; // bits 0-7 - }; // RCR bitfield - - /// register _TIM1_RCR reset value - #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) - - } RCR; - - - /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ - union { - - /// bytewise access to CCR1H - uint8_t byte; - - /// bitwise access to register CCR1H - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1H bitfield - - /// register _TIM1_CCR1H reset value - #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) - - } CCR1H; - - - /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ - union { - - /// bytewise access to CCR1L - uint8_t byte; - - /// bitwise access to register CCR1L - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1L bitfield - - /// register _TIM1_CCR1L reset value - #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) - - } CCR1L; - - - /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ - union { - - /// bytewise access to CCR2H - uint8_t byte; - - /// bitwise access to register CCR2H - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2H bitfield - - /// register _TIM1_CCR2H reset value - #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) - - } CCR2H; - - - /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ - union { - - /// bytewise access to CCR2L - uint8_t byte; - - /// bitwise access to register CCR2L - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2L bitfield - - /// register _TIM1_CCR2L reset value - #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) - - } CCR2L; - - - /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ - union { - - /// bytewise access to CCR3H - uint8_t byte; - - /// bitwise access to register CCR3H - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3H bitfield - - /// register _TIM1_CCR3H reset value - #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) - - } CCR3H; - - - /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ - union { - - /// bytewise access to CCR3L - uint8_t byte; - - /// bitwise access to register CCR3L - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3L bitfield - - /// register _TIM1_CCR3L reset value - #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) - - } CCR3L; - - - /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ - union { - - /// bytewise access to CCR4H - uint8_t byte; - - /// bitwise access to register CCR4H - struct { - BITS CCR4 : 8; // bits 0-7 - }; // CCR4H bitfield - - /// register _TIM1_CCR4H reset value - #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) - - } CCR4H; - - - /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ - union { - - /// bytewise access to CCR4L - uint8_t byte; - - /// bitwise access to register CCR4L - struct { - BITS CCR4 : 8; // bits 0-7 - }; // CCR4L bitfield - - /// register _TIM1_CCR4L reset value - #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) - - } CCR4L; - - - /** TIM1 break register (BKR at 0x526d) */ - union { - - /// bytewise access to BKR - uint8_t byte; - - /// bitwise access to register BKR - struct { - BITS LOCK : 2; // bits 0-1 - BITS OSSI : 1; // bit 2 - BITS OSSR : 1; // bit 3 - BITS BKE : 1; // bit 4 - BITS BKP : 1; // bit 5 - BITS AOE : 1; // bit 6 - BITS MOE : 1; // bit 7 - }; // BKR bitfield - - /// register _TIM1_BKR reset value - #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) - - } BKR; - - - /** TIM1 dead-time register (DTR at 0x526e) */ - union { - - /// bytewise access to DTR - uint8_t byte; - - /// bitwise access to register DTR - struct { - BITS DTG : 8; // bits 0-7 - }; // DTR bitfield - - /// register _TIM1_DTR reset value - #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) - - } DTR; - - - /** TIM1 output idle state register (OISR at 0x526f) */ - union { - - /// bytewise access to OISR - uint8_t byte; - - /// bitwise access to register OISR - struct { - BITS OIS1 : 1; // bit 0 - BITS OIS1N : 1; // bit 1 - BITS OIS2 : 1; // bit 2 - BITS OIS2N : 1; // bit 3 - BITS OIS3 : 1; // bit 4 - BITS OIS3N : 1; // bit 5 - BITS OIS4 : 1; // bit 6 - BITS : 1; // 1 bit - }; // OISR bitfield - - /// register _TIM1_OISR reset value - #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) - - } OISR; - -} TIM1_t; - -/// access to TIM1 SFR registers -#define sfr_TIM1 (*((TIM1_t*) 0x5250)) - - -//------------------------ -// Module TIM2 -//------------------------ - -/** struct containing TIM2 module registers */ -typedef struct { - - /** TIM2 control register 1 (CR1 at 0x5300) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS : 3; // 3 bits - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM2_CR1 reset value - #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /// Reserved register (2B) - uint8_t Reserved_1[2]; - - - /** TIM2 Interrupt enable register (IER at 0x5303) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS CC1IE : 1; // bit 1 - BITS CC2IE : 1; // bit 2 - BITS CC3IE : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIE : 1; // bit 6 - BITS : 1; // 1 bit - }; // IER bitfield - - /// register _TIM2_IER reset value - #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM2 status register 1 (SR1 at 0x5304) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS UIF : 1; // bit 0 - BITS CC1IF : 1; // bit 1 - BITS CC2IF : 1; // bit 2 - BITS CC3IF : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIF : 1; // bit 6 - BITS : 1; // 1 bit - }; // SR1 bitfield - - /// register _TIM2_SR1 reset value - #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** TIM2 status register 2 (SR2 at 0x5305) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS : 1; // 1 bit - BITS CC1OF : 1; // bit 1 - BITS CC2OF : 1; // bit 2 - BITS CC3OF : 1; // bit 3 - BITS : 4; // 4 bits - }; // SR2 bitfield - - /// register _TIM2_SR2 reset value - #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** TIM2 event generation register (EGR at 0x5306) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS CC1G : 1; // bit 1 - BITS CC2G : 1; // bit 2 - BITS CC3G : 1; // bit 3 - BITS : 2; // 2 bits - BITS TG : 1; // bit 6 - BITS : 1; // 1 bit - }; // EGR bitfield - - /// register _TIM2_EGR reset value - #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5307) */ - union { - - /// bytewise access to CCMR1 - uint8_t byte; - - /// bitwise access to register CCMR1 - struct { - BITS CC1S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC1PE : 1; // bit 3 - BITS OC1M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR1 bitfield - - /// register _TIM2_CCMR1 reset value - #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) - - } CCMR1; - - - /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5308) */ - union { - - /// bytewise access to CCMR2 - uint8_t byte; - - /// bitwise access to register CCMR2 - struct { - BITS CC2S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC2PE : 1; // bit 3 - BITS OC2M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR2 bitfield - - /// register _TIM2_CCMR2 reset value - #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) - - } CCMR2; - - - /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5309) */ - union { - - /// bytewise access to CCMR3 - uint8_t byte; - - /// bitwise access to register CCMR3 - struct { - BITS CC3S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC3PE : 1; // bit 3 - BITS OC3M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR3 bitfield - - /// register _TIM2_CCMR3 reset value - #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) - - } CCMR3; - - - /** TIM2 capture/compare enable register 1 (CCER1 at 0x530a) */ - union { - - /// bytewise access to CCER1 - uint8_t byte; - - /// bitwise access to register CCER1 - struct { - BITS CC1E : 1; // bit 0 - BITS CC1P : 1; // bit 1 - BITS : 2; // 2 bits - BITS CC2E : 1; // bit 4 - BITS CC2P : 1; // bit 5 - BITS : 2; // 2 bits - }; // CCER1 bitfield - - /// register _TIM2_CCER1 reset value - #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) - - } CCER1; - - - /** TIM2 capture/compare enable register 2 (CCER2 at 0x530b) */ - union { - - /// bytewise access to CCER2 - uint8_t byte; - - /// bitwise access to register CCER2 - struct { - BITS CC3E : 1; // bit 0 - BITS CC3P : 1; // bit 1 - BITS : 6; // 6 bits - }; // CCER2 bitfield - - /// register _TIM2_CCER2 reset value - #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) - - } CCER2; - - - /** TIM2 counter high (CNTRH at 0x530c) */ - union { - - /// bytewise access to CNTRH - uint8_t byte; - - /// bitwise access to register CNTRH - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRH bitfield - - /// register _TIM2_CNTRH reset value - #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) - - } CNTRH; - - - /** TIM2 counter low (CNTRL at 0x530d) */ - union { - - /// bytewise access to CNTRL - uint8_t byte; - - /// bitwise access to register CNTRL - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRL bitfield - - /// register _TIM2_CNTRL reset value - #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) - - } CNTRL; - - - /** TIM2 prescaler register (PSCR at 0x530e) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // PSCR bitfield - - /// register _TIM2_PSCR reset value - #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - - - /** TIM2 auto-reload register high (ARRH at 0x530f) */ - union { - - /// bytewise access to ARRH - uint8_t byte; - - /// bitwise access to register ARRH - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRH bitfield - - /// register _TIM2_ARRH reset value - #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) - - } ARRH; - - - /** TIM2 auto-reload register low (ARRL at 0x5310) */ - union { - - /// bytewise access to ARRL - uint8_t byte; - - /// bitwise access to register ARRL - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRL bitfield - - /// register _TIM2_ARRL reset value - #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) - - } ARRL; - - - /** TIM2 capture/compare register 1 high (CCR1H at 0x5311) */ - union { - - /// bytewise access to CCR1H - uint8_t byte; - - /// bitwise access to register CCR1H - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1H bitfield - - /// register _TIM2_CCR1H reset value - #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) - - } CCR1H; - - - /** TIM2 capture/compare register 1 low (CCR1L at 0x5312) */ - union { - - /// bytewise access to CCR1L - uint8_t byte; - - /// bitwise access to register CCR1L - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1L bitfield - - /// register _TIM2_CCR1L reset value - #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) - - } CCR1L; - - - /** TIM2 capture/compare reg (CCR2H at 0x5313) */ - union { - - /// bytewise access to CCR2H - uint8_t byte; - - /// bitwise access to register CCR2H - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2H bitfield - - /// register _TIM2_CCR2H reset value - #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) - - } CCR2H; - - - /** TIM2 capture/compare register 2 low (CCR2L at 0x5314) */ - union { - - /// bytewise access to CCR2L - uint8_t byte; - - /// bitwise access to register CCR2L - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2L bitfield - - /// register _TIM2_CCR2L reset value - #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) - - } CCR2L; - - - /** TIM2 capture/compare register 3 high (CCR3H at 0x5315) */ - union { - - /// bytewise access to CCR3H - uint8_t byte; - - /// bitwise access to register CCR3H - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3H bitfield - - /// register _TIM2_CCR3H reset value - #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) - - } CCR3H; - - - /** TIM2 capture/compare register 3 low (CCR3L at 0x5316) */ - union { - - /// bytewise access to CCR3L - uint8_t byte; - - /// bitwise access to register CCR3L - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3L bitfield - - /// register _TIM2_CCR3L reset value - #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) - - } CCR3L; - -} TIM2_t; - -/// access to TIM2 SFR registers -#define sfr_TIM2 (*((TIM2_t*) 0x5300)) - - -//------------------------ -// Module TIM4 -//------------------------ - -/** struct containing TIM4 module registers */ -typedef struct { - - /** TIM4 control register 1 (CR1 at 0x5340) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS : 3; // 3 bits - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM4_CR1 reset value - #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /// Reserved register (2B) - uint8_t Reserved_1[2]; - - - /** TIM4 interrupt enable register (IER at 0x5343) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS : 5; // 5 bits - BITS TIE : 1; // bit 6 - BITS : 1; // 1 bit - }; // IER bitfield - - /// register _TIM4_IER reset value - #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM4 status register (SR at 0x5344) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS UIF : 1; // bit 0 - BITS : 5; // 5 bits - BITS TIF : 1; // bit 6 - BITS : 1; // 1 bit - }; // SR bitfield - - /// register _TIM4_SR reset value - #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) - - } SR; - - - /** TIM4 event generation register (EGR at 0x5345) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS : 5; // 5 bits - BITS TG : 1; // bit 6 - BITS : 1; // 1 bit - }; // EGR bitfield - - /// register _TIM4_EGR reset value - #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM4 counter (CNTR at 0x5346) */ - union { - - /// bytewise access to CNTR - uint8_t byte; - - /// bitwise access to register CNTR - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTR bitfield - - /// register _TIM4_CNTR reset value - #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) - - } CNTR; - - - /** TIM4 prescaler register (PSCR at 0x5347) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // PSCR bitfield - - /// register _TIM4_PSCR reset value - #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - - - /** TIM4 auto-reload register (ARR at 0x5348) */ - union { - - /// bytewise access to ARR - uint8_t byte; - - /// bitwise access to register ARR - struct { - BITS ARR : 8; // bits 0-7 - }; // ARR bitfield - - /// register _TIM4_ARR reset value - #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) - - } ARR; - -} TIM4_t; - -/// access to TIM4 SFR registers -#define sfr_TIM4 (*((TIM4_t*) 0x5340)) - - -//------------------------ -// Module UART1 -//------------------------ - -/** struct containing UART1 module registers */ -typedef struct { - - /** UART1 status register (SR at 0x5230) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS PE : 1; // bit 0 - BITS FE : 1; // bit 1 - BITS NF : 1; // bit 2 - BITS OR_LHE : 1; // bit 3 - BITS IDLE : 1; // bit 4 - BITS RXNE : 1; // bit 5 - BITS TC : 1; // bit 6 - BITS TXE : 1; // bit 7 - }; // SR bitfield - - /// register _UART1_SR reset value - #define sfr_UART1_SR_RESET_VALUE ((uint8_t) 0xC0) - - } SR; - - - /** UART1 data register (DR at 0x5231) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _UART1_DR reset value - #define sfr_UART1_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** UART1 baud rate register 1 (BRR1 at 0x5232) */ - union { - - /// bytewise access to BRR1 - uint8_t byte; - - /// bitwise access to register BRR1 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR1 bitfield - - /// register _UART1_BRR1 reset value - #define sfr_UART1_BRR1_RESET_VALUE ((uint8_t) 0x00) - - } BRR1; - - - /** UART1 baud rate register 2 (BRR2 at 0x5233) */ - union { - - /// bytewise access to BRR2 - uint8_t byte; - - /// bitwise access to register BRR2 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR2 bitfield - - /// register _UART1_BRR2 reset value - #define sfr_UART1_BRR2_RESET_VALUE ((uint8_t) 0x00) - - } BRR2; - - - /** UART1 control register 1 (CR1 at 0x5234) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PIEN : 1; // bit 0 - BITS PS : 1; // bit 1 - BITS PCEN : 1; // bit 2 - BITS WAKE : 1; // bit 3 - BITS M : 1; // bit 4 - BITS UART0 : 1; // bit 5 - BITS T8 : 1; // bit 6 - BITS R8 : 1; // bit 7 - }; // CR1 bitfield - - /// register _UART1_CR1 reset value - #define sfr_UART1_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** UART1 control register 2 (CR2 at 0x5235) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS SBK : 1; // bit 0 - BITS RWU : 1; // bit 1 - BITS REN : 1; // bit 2 - BITS TEN : 1; // bit 3 - BITS ILIEN : 1; // bit 4 - BITS RIEN : 1; // bit 5 - BITS TCIEN : 1; // bit 6 - BITS TIEN : 1; // bit 7 - }; // CR2 bitfield - - /// register _UART1_CR2 reset value - #define sfr_UART1_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** UART1 control register 3 (CR3 at 0x5236) */ - union { - - /// bytewise access to CR3 - uint8_t byte; - - /// bitwise access to register CR3 - struct { - BITS LBCL : 1; // bit 0 - BITS CPHA : 1; // bit 1 - BITS CPOL : 1; // bit 2 - BITS CKEN : 1; // bit 3 - BITS STOP : 2; // bits 4-5 - BITS : 1; // 1 bit - BITS LINEN : 1; // bit 7 - }; // CR3 bitfield - - /// register _UART1_CR3 reset value - #define sfr_UART1_CR3_RESET_VALUE ((uint8_t) 0x00) - - } CR3; - - - /** UART1 control register 4 (CR4 at 0x5237) */ - union { - - /// bytewise access to CR4 - uint8_t byte; - - /// bitwise access to register CR4 - struct { - BITS ADD : 4; // bits 0-3 - BITS LBDF : 1; // bit 4 - BITS LBDL : 1; // bit 5 - BITS LBDIEN : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR4 bitfield - - /// register _UART1_CR4 reset value - #define sfr_UART1_CR4_RESET_VALUE ((uint8_t) 0x00) - - } CR4; - - - /** UART1 control register 5 (CR5 at 0x5238) */ - union { - - /// bytewise access to CR5 - uint8_t byte; - - /// bitwise access to register CR5 - struct { - BITS : 1; // 1 bit - BITS IREN : 1; // bit 1 - BITS IRLP : 1; // bit 2 - BITS HDSEL : 1; // bit 3 - BITS NACK : 1; // bit 4 - BITS SCEN : 1; // bit 5 - BITS : 2; // 2 bits - }; // CR5 bitfield - - /// register _UART1_CR5 reset value - #define sfr_UART1_CR5_RESET_VALUE ((uint8_t) 0x00) - - } CR5; - - - /** UART1 guard time register (GTR at 0x5239) */ - union { - - /// bytewise access to GTR - uint8_t byte; - - /// bitwise access to register GTR - struct { - BITS GT : 8; // bits 0-7 - }; // GTR bitfield - - /// register _UART1_GTR reset value - #define sfr_UART1_GTR_RESET_VALUE ((uint8_t) 0x00) - - } GTR; - - - /** UART1 prescaler register (PSCR at 0x523a) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCR bitfield - - /// register _UART1_PSCR reset value - #define sfr_UART1_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - -} UART1_t; - -/// access to UART1 SFR registers -#define sfr_UART1 (*((UART1_t*) 0x5230)) - - -//------------------------ -// Module WWDG -//------------------------ - -/** struct containing WWDG module registers */ -typedef struct { - - /** WWDG control register (CR at 0x50d1) */ - union { - - /// bytewise access to CR - uint8_t byte; - - /// bitwise access to register CR - struct { - BITS T0 : 1; // bit 0 - BITS T1 : 1; // bit 1 - BITS T2 : 1; // bit 2 - BITS T3 : 1; // bit 3 - BITS T4 : 1; // bit 4 - BITS T5 : 1; // bit 5 - BITS T6 : 1; // bit 6 - BITS WDGA : 1; // bit 7 - }; // CR bitfield - - /// register _WWDG_CR reset value - #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) - - } CR; - - - /** WWDR window register (WR at 0x50d2) */ - union { - - /// bytewise access to WR - uint8_t byte; - - /// bitwise access to register WR - struct { - BITS W0 : 1; // bit 0 - BITS W1 : 1; // bit 1 - BITS W2 : 1; // bit 2 - BITS W3 : 1; // bit 3 - BITS W4 : 1; // bit 4 - BITS W5 : 1; // bit 5 - BITS W6 : 1; // bit 6 - BITS : 1; // 1 bit - }; // WR bitfield - - /// register _WWDG_WR reset value - #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) - - } WR; - -} WWDG_t; - -/// access to WWDG SFR registers -#define sfr_WWDG (*((WWDG_t*) 0x50d1)) - - -// undefine local macros -#undef BITS - -// required for C++ -#ifdef __cplusplus - } // extern "C" -#endif - -/*------------------------------------------------------------------------- - END OF MODULE DEFINITION FOR MULTIPLE INLUSION --------------------------------------------------------------------------*/ -#endif // STM8S103F3_H diff --git a/examples/native-blink/src/STM8S207K8.h b/examples/native-blink/src/STM8S207K8.h deleted file mode 100644 index 574a48a..0000000 --- a/examples/native-blink/src/STM8S207K8.h +++ /dev/null @@ -1,4648 +0,0 @@ -/*------------------------------------------------------------------------- - - STM8S207K8.h - Device Declarations - - STM8S/STM8AF, high density with ROM bootloader - - Copyright (C) 2020, Georg Icking-Konert - - Mainstream Performance line 8-bit MCU with 64 Kbytes Flash, 24 MHz CPU, integrated EEPROM - - datasheet: https://www.st.com/resource/en/datasheet/stm8s207k8.pdf - reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf - - MIT License - - Copyright (c) 2020 Georg Icking-Konert - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - SOFTWARE. - --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- - MODULE DEFINITION FOR MULTIPLE INCLUSION --------------------------------------------------------------------------*/ -#ifndef STM8S207K8_H -#define STM8S207K8_H - -// DEVICE NAME -#define DEVICE_STM8S207K8 - -// DEVICE FAMILY -#define FAMILY_STM8S - -// required for C++ -#ifdef __cplusplus - extern "C" { -#endif - - -/*------------------------------------------------------------------------- - INCLUDE FILES --------------------------------------------------------------------------*/ -#include - - -/*------------------------------------------------------------------------- - COMPILER SPECIFIC SETTINGS --------------------------------------------------------------------------*/ - -// Cosmic compiler -#if defined(__CSMC__) - - // macros to unify ISR declaration and implementation - #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine - #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine - - // definition of inline functions - #define INLINE @inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling - #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling - #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt - #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode - #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned int ///< data type in bit structs (follow C90 standard) - - -// IAR Compiler -#elif defined(__ICCSTM8__) - - // include intrinsic functions - #include - - // macros to unify ISR declaration and implementation - #define STRINGVECTOR(x) #x - #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) - #define ISR_HANDLER( a, b ) \ - _Pragma( VECTOR_ID( (b)+2 ) ) \ - __interrupt void (a)( void ) - #define ISR_HANDLER_TRAP(a) \ - _Pragma( VECTOR_ID( 1 ) ) \ - __interrupt void (a) (void) - - // definition of inline functions - #define INLINE static inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling - #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling - #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt - #define ENTER_HALT() __halt() ///< put controller to HALT mode - #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) - - -// SDCC compiler -#elif defined(__SDCC) - - // store SDCC version in preprocessor friendly way - #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ - + __SDCC_VERSION_MINOR * 100 \ - + __SDCC_VERSION_PATCH) - - // unify ISR declaration and implementation - #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine - #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 - #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine - #else - #error traps require SDCC >=3.4.3. Please update! - #endif - - // definition of inline functions - #define INLINE static inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling - #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling - #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt - #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode - #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned int ///< data type in bit structs (follow C90 standard) - -// unsupported compiler -> stop -#else - #error: compiler not supported -#endif - - -/*------------------------------------------------------------------------- - FOR CONVENIENT PIN ACCESS --------------------------------------------------------------------------*/ - -#define PIN0 0x01 -#define PIN1 0x02 -#define PIN2 0x04 -#define PIN3 0x08 -#define PIN4 0x10 -#define PIN5 0x20 -#define PIN6 0x40 -#define PIN7 0x80 - - -/*------------------------------------------------------------------------- - DEVICE MEMORY (size in bytes) --------------------------------------------------------------------------*/ - -// RAM -#define RAM_ADDR_START 0x000000 -#define RAM_ADDR_END 0x0017FF -#define RAM_SIZE 6144 - - -// FLASH -#define FLASH_ADDR_START 0x008000 -#define FLASH_ADDR_END 0x017FFF -#define FLASH_SIZE 65536 - - -// SFR1 -#define SFR1_ADDR_START 0x005000 -#define SFR1_ADDR_END 0x0057FF -#define SFR1_SIZE 2048 - - -// SFR2 -#define SFR2_ADDR_START 0x007F00 -#define SFR2_ADDR_END 0x007FFF -#define SFR2_SIZE 256 - - -// BOOTROM -#define BOOTROM_ADDR_START 0x006000 -#define BOOTROM_ADDR_END 0x0067FF -#define BOOTROM_SIZE 2048 - - -// EEPROM -#define EEPROM_ADDR_START 0x004000 -#define EEPROM_ADDR_END 0x0043FF -#define EEPROM_SIZE 1024 - - -// OPTION -#define OPTION_ADDR_START 0x004800 -#define OPTION_ADDR_END 0x00487F -#define OPTION_SIZE 128 - - -// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) -#define FLASH_ADDR_WIDTH 32 ///< width of address space -#define FLASH_POINTER_T uint32_t ///< address variable type - - -/*------------------------------------------------------------------------- - UNIQUE IDENTIFIER (size in bytes) --------------------------------------------------------------------------*/ - -#define UID_ADDR_START 0x48CD ///< start address of unique identifier -#define UID_SIZE 12 ///< size of unique identifier [B] -#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N - - -/*------------------------------------------------------------------------- - MISC OPTIONS --------------------------------------------------------------------------*/ - -/// LSI frequency measurement channel -#define LSI_MEASURE_TIM3_IC1 - - -/*------------------------------------------------------------------------- - ISR Vector Table (SDCC, IAR) - Notes: - - IAR has an IRQ offset of +2 compared to datasheet and below numbers - - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' - - different interrupt sources may share the same IRQ --------------------------------------------------------------------------*/ - -// interrupt IRQ -#define _TLI_VECTOR_ 0 -#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR -#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR -#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR -#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR -#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR -#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR -#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR -#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR -#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR -#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR -#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR -#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR -#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR -#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR -#define _TIM1_CAPCOM_BIF_VECTOR_ 11 ///< TIM1_CAPCOM_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_CAPCOM_TIF_VECTOR_ 11 ///< TIM1_CAPCOM_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR -#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR -#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR -#define _TIM3_OVR_UIF_VECTOR_ 15 ///< TIM3_OVR_UIF interrupt vector: enable: TIM3_IER.UIE, pending: TIM3_SR1.UIF, priority: ITC_SPR4.VECT15SPR -#define _TIM3_CAPCOM_CC1IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC1IF interrupt vector: enable: TIM3_IER.CC1IE, pending: TIM3_SR1.CC1IF, priority: ITC_SPR5.VECT16SPR -#define _TIM3_CAPCOM_CC2IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC2IF interrupt vector: enable: TIM3_IER.CC2IE, pending: TIM3_SR1.CC2IF, priority: ITC_SPR5.VECT16SPR -#define _TIM3_CAPCOM_CC3IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC3IF interrupt vector: enable: TIM3_IER.CC3IE, pending: TIM3_SR1.CC3IF, priority: ITC_SPR5.VECT16SPR -#define _TIM3_CAPCOM_TIF_VECTOR_ 16 ///< TIM3_CAPCOM_TIF interrupt vector: enable: TIM3_IER.TIE, pending: TIM3_SR1.TIF, priority: ITC_SPR5.VECT16SPR -#define _UART1_T_TC_VECTOR_ 17 ///< UART1_T_TC interrupt vector: enable: UART1_CR2.TCIEN, pending: UART1_SR.TC, priority: ITC_SPR5.VECT17SPR -#define _UART1_T_TXE_VECTOR_ 17 ///< UART1_T_TXE interrupt vector: enable: UART1_CR2.TIEN, pending: UART1_SR.TXE, priority: ITC_SPR5.VECT17SPR -#define _UART1_R_IDLE_VECTOR_ 18 ///< UART1_R_IDLE interrupt vector: enable: UART1_CR2.ILIEN, pending: UART1_SR.IDLE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_LBDF_VECTOR_ 18 ///< UART1_R_LBDF interrupt vector: enable: UART1_CR4.LBDIEN, pending: UART1_CR4.LBDF, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_OR_VECTOR_ 18 ///< UART1_R_OR interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.OR_LHE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_PE_VECTOR_ 18 ///< UART1_R_PE interrupt vector: enable: UART1_CR1.PIEN, pending: UART1_SR.PE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_RXNE_VECTOR_ 18 ///< UART1_R_RXNE interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.RXNE, priority: ITC_SPR5.VECT18SPR -#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR -#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR -#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR -#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR -#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR -#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR -#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR -#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR -#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR -#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR -#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR -#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR -#define _UART3_T_TC_VECTOR_ 20 ///< UART3_T_TC interrupt vector: enable: UART3_CR2.TCIEN, pending: UART3_SR.TC, priority: ITC_SPR6.VECT20SPR -#define _UART3_T_TXE_VECTOR_ 20 ///< UART3_T_TXE interrupt vector: enable: UART3_CR2.TIEN, pending: UART3_SR.TXE, priority: ITC_SPR6.VECT20SPR -#define _UART3_R_IDLE_VECTOR_ 21 ///< UART3_R_IDLE interrupt vector: enable: UART3_CR2.ILIEN, pending: UART3_SR.IDLE, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_LBDF_VECTOR_ 21 ///< UART3_R_LBDF interrupt vector: enable: UART3_CR4.LBDIEN, pending: UART3_CR4.LBDF, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_LHDF_VECTOR_ 21 ///< UART3_R_LHDF interrupt vector: enable: UART3_CR6.LHDIEN, pending: UART3_CR6.LHDF, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_OR_VECTOR_ 21 ///< UART3_R_OR interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.OR, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_PE_VECTOR_ 21 ///< UART3_R_PE interrupt vector: enable: UART3_CR1.PIEN, pending: UART3_SR.PE, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_RXNE_VECTOR_ 21 ///< UART3_R_RXNE interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.RXNE, priority: ITC_SPR6.VECT21SPR -#define _ADC2_AWDG_VECTOR_ 22 ///< ADC2_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR -#define _ADC2_EOC_VECTOR_ 22 ///< ADC2_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR -#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR -#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR -#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR - - -/*------------------------------------------------------------------------- - DEFINITION OF STM8 PERIPHERAL REGISTERS --------------------------------------------------------------------------*/ - -//------------------------ -// Module ADC2 -//------------------------ - -/** struct containing ADC2 module registers */ -typedef struct { - - /** ADC control/status register (CSR at 0x5400) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// bitwise access to register CSR - struct { - BITS CH : 4; // bits 0-3 - BITS AWDIE : 1; // bit 4 - BITS EOCIE : 1; // bit 5 - BITS AWD : 1; // bit 6 - BITS EOC : 1; // bit 7 - }; // CSR bitfield - - /// register _ADC2_CSR reset value - #define sfr_ADC2_CSR_RESET_VALUE ((uint8_t) 0x00) - - } CSR; - - - /** ADC configuration register 1 (CR1 at 0x5401) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS ADON : 1; // bit 0 - BITS CONT : 1; // bit 1 - BITS : 2; // 2 bits - BITS SPSEL : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CR1 bitfield - - /// register _ADC2_CR1 reset value - #define sfr_ADC2_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** ADC configuration register 2 (CR2 at 0x5402) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS : 1; // 1 bit - BITS SCAN : 1; // bit 1 - BITS : 1; // 1 bit - BITS ALIGN : 1; // bit 3 - BITS EXTSEL : 2; // bits 4-5 - BITS EXTTRIG : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR2 bitfield - - /// register _ADC2_CR2 reset value - #define sfr_ADC2_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** ADC configuration register 3 (CR3 at 0x5403) */ - union { - - /// bytewise access to CR3 - uint8_t byte; - - /// bitwise access to register CR3 - struct { - BITS : 6; // 6 bits - BITS OVR : 1; // bit 6 - BITS DBUF : 1; // bit 7 - }; // CR3 bitfield - - /// register _ADC2_CR3 reset value - #define sfr_ADC2_CR3_RESET_VALUE ((uint8_t) 0x00) - - } CR3; - - - /** ADC data register high (DRH at 0x5404) */ - union { - - /// bytewise access to DRH - uint8_t byte; - - /// bitwise access to register DRH - struct { - BITS DH : 8; // bits 0-7 - }; // DRH bitfield - - /// register _ADC2_DRH reset value - #define sfr_ADC2_DRH_RESET_VALUE ((uint8_t) 0x00) - - } DRH; - - - /** ADC data register low (DRL at 0x5405) */ - union { - - /// bytewise access to DRL - uint8_t byte; - - /// bitwise access to register DRL - struct { - BITS DL : 8; // bits 0-7 - }; // DRL bitfield - - /// register _ADC2_DRL reset value - #define sfr_ADC2_DRL_RESET_VALUE ((uint8_t) 0x00) - - } DRL; - - - /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ - union { - - /// bytewise access to TDRH - uint8_t byte; - - /// bitwise access to register TDRH - struct { - BITS TD : 8; // bits 0-7 - }; // TDRH bitfield - - /// register _ADC2_TDRH reset value - #define sfr_ADC2_TDRH_RESET_VALUE ((uint8_t) 0x00) - - } TDRH; - - - /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ - union { - - /// bytewise access to TDRL - uint8_t byte; - - /// bitwise access to register TDRL - struct { - BITS TL : 8; // bits 0-7 - }; // TDRL bitfield - - /// register _ADC2_TDRL reset value - #define sfr_ADC2_TDRL_RESET_VALUE ((uint8_t) 0x00) - - } TDRL; - -} ADC2_t; - -/// access to ADC2 SFR registers -#define sfr_ADC2 (*((ADC2_t*) 0x5400)) - - -//------------------------ -// Module AWU -//------------------------ - -/** struct containing AWU module registers */ -typedef struct { - - /** AWU control/status register 1 (CSR1 at 0x50f0) */ - union { - - /// bytewise access to CSR1 - uint8_t byte; - - /// bitwise access to register CSR1 - struct { - BITS MSR : 1; // bit 0 - BITS : 3; // 3 bits - BITS AWUEN : 1; // bit 4 - BITS AWUF : 1; // bit 5 - BITS : 2; // 2 bits - }; // CSR1 bitfield - - /// register _AWU_CSR1 reset value - #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) - - } CSR1; - - - /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ - union { - - /// bytewise access to APR - uint8_t byte; - - /// bitwise access to register APR - struct { - BITS APR : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // APR bitfield - - /// register _AWU_APR reset value - #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) - - } APR; - - - /** AWU timebase selection register (TBR at 0x50f2) */ - union { - - /// bytewise access to TBR - uint8_t byte; - - /// bitwise access to register TBR - struct { - BITS AWUTB : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // TBR bitfield - - /// register _AWU_TBR reset value - #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) - - } TBR; - -} AWU_t; - -/// access to AWU SFR registers -#define sfr_AWU (*((AWU_t*) 0x50f0)) - - -//------------------------ -// Module BEEP -//------------------------ - -/** struct containing BEEP module registers */ -typedef struct { - - /** BEEP control/status register (CSR at 0x50f3) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// bitwise access to register CSR - struct { - BITS BEEPDIV : 5; // bits 0-4 - BITS BEEPEN : 1; // bit 5 - BITS BEEPSEL : 2; // bits 6-7 - }; // CSR bitfield - - /// register _BEEP_CSR reset value - #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) - - } CSR; - -} BEEP_t; - -/// access to BEEP SFR registers -#define sfr_BEEP (*((BEEP_t*) 0x50f3)) - - -//------------------------ -// Module CLK -//------------------------ - -/** struct containing CLK module registers */ -typedef struct { - - /** Internal clock control register (ICKR at 0x50c0) */ - union { - - /// bytewise access to ICKR - uint8_t byte; - - /// bitwise access to register ICKR - struct { - BITS HSIEN : 1; // bit 0 - BITS HSIRDY : 1; // bit 1 - BITS FHW : 1; // bit 2 - BITS LSIEN : 1; // bit 3 - BITS LSIRDY : 1; // bit 4 - BITS REGAH : 1; // bit 5 - BITS : 2; // 2 bits - }; // ICKR bitfield - - /// register _CLK_ICKR reset value - #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) - - } ICKR; - - - /** External clock control register (ECKR at 0x50c1) */ - union { - - /// bytewise access to ECKR - uint8_t byte; - - /// bitwise access to register ECKR - struct { - BITS HSEEN : 1; // bit 0 - BITS HSERDY : 1; // bit 1 - BITS : 6; // 6 bits - }; // ECKR bitfield - - /// register _CLK_ECKR reset value - #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) - - } ECKR; - - - /// Reserved register (1B) - uint8_t Reserved_1[1]; - - - /** Clock master status register (CMSR at 0x50c3) */ - union { - - /// bytewise access to CMSR - uint8_t byte; - - /// bitwise access to register CMSR - struct { - BITS CKM : 8; // bits 0-7 - }; // CMSR bitfield - - /// register _CLK_CMSR reset value - #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) - - } CMSR; - - - /** Clock master switch register (SWR at 0x50c4) */ - union { - - /// bytewise access to SWR - uint8_t byte; - - /// bitwise access to register SWR - struct { - BITS SWI : 8; // bits 0-7 - }; // SWR bitfield - - /// register _CLK_SWR reset value - #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) - - } SWR; - - - /** Clock switch control register (SWCR at 0x50c5) */ - union { - - /// bytewise access to SWCR - uint8_t byte; - - /// bitwise access to register SWCR - struct { - BITS SWBSY : 1; // bit 0 - BITS SWEN : 1; // bit 1 - BITS SWIEN : 1; // bit 2 - BITS SWIF : 1; // bit 3 - BITS : 4; // 4 bits - }; // SWCR bitfield - - /// register _CLK_SWCR reset value - #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) - - } SWCR; - - - /** Clock divider register (CKDIVR at 0x50c6) */ - union { - - /// bytewise access to CKDIVR - uint8_t byte; - - /// bitwise access to register CKDIVR - struct { - BITS CPUDIV : 3; // bits 0-2 - BITS HSIDIV : 2; // bits 3-4 - BITS : 3; // 3 bits - }; // CKDIVR bitfield - - /// register _CLK_CKDIVR reset value - #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) - - } CKDIVR; - - - /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ - union { - - /// bytewise access to PCKENR1 - uint8_t byte; - - /// bitwise access to register PCKENR1 - struct { - BITS PCKEN : 8; // bits 0-7 - }; // PCKENR1 bitfield - - /// register _CLK_PCKENR1 reset value - #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) - - } PCKENR1; - - - /** Clock security system register (CSSR at 0x50c8) */ - union { - - /// bytewise access to CSSR - uint8_t byte; - - /// bitwise access to register CSSR - struct { - BITS CSSEN : 1; // bit 0 - BITS AUX : 1; // bit 1 - BITS CSSDIE : 1; // bit 2 - BITS CSSD : 1; // bit 3 - BITS : 4; // 4 bits - }; // CSSR bitfield - - /// register _CLK_CSSR reset value - #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) - - } CSSR; - - - /** Configurable clock control register (CCOR at 0x50c9) */ - union { - - /// bytewise access to CCOR - uint8_t byte; - - /// bitwise access to register CCOR - struct { - BITS CCOEN : 1; // bit 0 - BITS CCOSEL : 4; // bits 1-4 - BITS CCORDY : 1; // bit 5 - BITS CC0BSY : 1; // bit 6 - BITS : 1; // 1 bit - }; // CCOR bitfield - - /// register _CLK_CCOR reset value - #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) - - } CCOR; - - - /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ - union { - - /// bytewise access to PCKENR2 - uint8_t byte; - - /// bitwise access to register PCKENR2 - struct { - BITS PCKEN2 : 8; // bits 0-7 - }; // PCKENR2 bitfield - - /// register _CLK_PCKENR2 reset value - #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) - - } PCKENR2; - - - /** CAN clock control register (CANCCR at 0x50cb) */ - union { - - /// bytewise access to CANCCR - uint8_t byte; - - /// bitwise access to register CANCCR - struct { - BITS CANDIV : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // CANCCR bitfield - - /// register _CLK_CANCCR reset value - #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) - - } CANCCR; - - - /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ - union { - - /// bytewise access to HSITRIMR - uint8_t byte; - - /// bitwise access to register HSITRIMR - struct { - BITS HSITRIM : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // HSITRIMR bitfield - - /// register _CLK_HSITRIMR reset value - #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) - - } HSITRIMR; - - - /** SWIM clock control register (SWIMCCR at 0x50cd) */ - union { - - /// bytewise access to SWIMCCR - uint8_t byte; - - /// bitwise access to register SWIMCCR - struct { - BITS SWIMCLK : 1; // bit 0 - BITS : 7; // 7 bits - }; // SWIMCCR bitfield - - /// register _CLK_SWIMCCR reset value - #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) - - } SWIMCCR; - -} CLK_t; - -/// access to CLK SFR registers -#define sfr_CLK (*((CLK_t*) 0x50c0)) - - -//------------------------ -// Module CPU -//------------------------ - -/** struct containing CPU module registers */ -typedef struct { - - /** Accumulator (A at 0x7f00) */ - union { - - /// bytewise access to A - uint8_t byte; - - /// skip bitwise access to register A - - /// register _CPU_A reset value - #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) - - } A; - - - /** Program counter extended (PCE at 0x7f01) */ - union { - - /// bytewise access to PCE - uint8_t byte; - - /// skip bitwise access to register PCE - - /// register _CPU_PCE reset value - #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) - - } PCE; - - - /** Program counter high (PCH at 0x7f02) */ - union { - - /// bytewise access to PCH - uint8_t byte; - - /// skip bitwise access to register PCH - - /// register _CPU_PCH reset value - #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) - - } PCH; - - - /** Program counter low (PCL at 0x7f03) */ - union { - - /// bytewise access to PCL - uint8_t byte; - - /// skip bitwise access to register PCL - - /// register _CPU_PCL reset value - #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) - - } PCL; - - - /** X index register high (XH at 0x7f04) */ - union { - - /// bytewise access to XH - uint8_t byte; - - /// skip bitwise access to register XH - - /// register _CPU_XH reset value - #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) - - } XH; - - - /** X index register low (XL at 0x7f05) */ - union { - - /// bytewise access to XL - uint8_t byte; - - /// skip bitwise access to register XL - - /// register _CPU_XL reset value - #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) - - } XL; - - - /** Y index register high (YH at 0x7f06) */ - union { - - /// bytewise access to YH - uint8_t byte; - - /// skip bitwise access to register YH - - /// register _CPU_YH reset value - #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) - - } YH; - - - /** Y index register low (YL at 0x7f07) */ - union { - - /// bytewise access to YL - uint8_t byte; - - /// skip bitwise access to register YL - - /// register _CPU_YL reset value - #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) - - } YL; - - - /** Stack pointer high (SPH at 0x7f08) */ - union { - - /// bytewise access to SPH - uint8_t byte; - - /// skip bitwise access to register SPH - - /// register _CPU_SPH reset value - #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x17) - - } SPH; - - - /** Stack pointer low (SPL at 0x7f09) */ - union { - - /// bytewise access to SPL - uint8_t byte; - - /// skip bitwise access to register SPL - - /// register _CPU_SPL reset value - #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) - - } SPL; - - - /** Condition code register (CCR at 0x7f0a) */ - union { - - /// bytewise access to CCR - uint8_t byte; - - /// bitwise access to register CCR - struct { - BITS C : 1; // bit 0 - BITS Z : 1; // bit 1 - BITS NF : 1; // bit 2 - BITS I0 : 1; // bit 3 - BITS H : 1; // bit 4 - BITS I1 : 1; // bit 5 - BITS : 1; // 1 bit - BITS V : 1; // bit 7 - }; // CCR bitfield - - /// register _CPU_CCR reset value - #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) - - } CCR; - - - /// Reserved register (85B) - uint8_t Reserved_1[85]; - - - /** Global configuration register (CFG_GCR at 0x7f60) */ - union { - - /// bytewise access to CFG_GCR - uint8_t byte; - - /// bitwise access to register CFG_GCR - struct { - BITS SWO : 1; // bit 0 - BITS AL : 1; // bit 1 - BITS : 6; // 6 bits - }; // CFG_GCR bitfield - - /// register _CPU_CFG_GCR reset value - #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) - - } CFG_GCR; - -} CPU_t; - -/// access to CPU SFR registers -#define sfr_CPU (*((CPU_t*) 0x7f00)) - - -//------------------------ -// Module DM -//------------------------ - -/** struct containing DM module registers */ -typedef struct { - - /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ - union { - - /// bytewise access to BK1RE - uint8_t byte; - - /// skip bitwise access to register BK1RE - - /// register _DM_BK1RE reset value - #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RE; - - - /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ - union { - - /// bytewise access to BK1RH - uint8_t byte; - - /// skip bitwise access to register BK1RH - - /// register _DM_BK1RH reset value - #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RH; - - - /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ - union { - - /// bytewise access to BK1RL - uint8_t byte; - - /// skip bitwise access to register BK1RL - - /// register _DM_BK1RL reset value - #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RL; - - - /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ - union { - - /// bytewise access to BK2RE - uint8_t byte; - - /// skip bitwise access to register BK2RE - - /// register _DM_BK2RE reset value - #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RE; - - - /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ - union { - - /// bytewise access to BK2RH - uint8_t byte; - - /// skip bitwise access to register BK2RH - - /// register _DM_BK2RH reset value - #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RH; - - - /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ - union { - - /// bytewise access to BK2RL - uint8_t byte; - - /// skip bitwise access to register BK2RL - - /// register _DM_BK2RL reset value - #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RL; - - - /** DM debug module control register 1 (CR1 at 0x7f96) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// skip bitwise access to register CR1 - - /// register _DM_CR1 reset value - #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** DM debug module control register 2 (CR2 at 0x7f97) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// skip bitwise access to register CR2 - - /// register _DM_CR2 reset value - #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ - union { - - /// bytewise access to CSR1 - uint8_t byte; - - /// skip bitwise access to register CSR1 - - /// register _DM_CSR1 reset value - #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) - - } CSR1; - - - /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ - union { - - /// bytewise access to CSR2 - uint8_t byte; - - /// skip bitwise access to register CSR2 - - /// register _DM_CSR2 reset value - #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) - - } CSR2; - - - /** DM enable function register (ENFCTR at 0x7f9a) */ - union { - - /// bytewise access to ENFCTR - uint8_t byte; - - /// skip bitwise access to register ENFCTR - - /// register _DM_ENFCTR reset value - #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) - - } ENFCTR; - -} DM_t; - -/// access to DM SFR registers -#define sfr_DM (*((DM_t*) 0x7f90)) - - -//------------------------ -// Module FLASH -//------------------------ - -/** struct containing FLASH module registers */ -typedef struct { - - /** Flash control register 1 (CR1 at 0x505a) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS FIX : 1; // bit 0 - BITS IE : 1; // bit 1 - BITS AHALT : 1; // bit 2 - BITS HALT : 1; // bit 3 - BITS : 4; // 4 bits - }; // CR1 bitfield - - /// register _FLASH_CR1 reset value - #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** Flash control register 2 (CR2 at 0x505b) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS PRG : 1; // bit 0 - BITS : 3; // 3 bits - BITS FPRG : 1; // bit 4 - BITS ERASE : 1; // bit 5 - BITS WPRG : 1; // bit 6 - BITS OPT : 1; // bit 7 - }; // CR2 bitfield - - /// register _FLASH_CR2 reset value - #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** Flash complementary control register 2 (NCR2 at 0x505c) */ - union { - - /// bytewise access to NCR2 - uint8_t byte; - - /// bitwise access to register NCR2 - struct { - BITS NPRG : 1; // bit 0 - BITS : 3; // 3 bits - BITS NFPRG : 1; // bit 4 - BITS NERASE : 1; // bit 5 - BITS NWPRG : 1; // bit 6 - BITS NOPT : 1; // bit 7 - }; // NCR2 bitfield - - /// register _FLASH_NCR2 reset value - #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) - - } NCR2; - - - /** Flash protection register (FPR at 0x505d) */ - union { - - /// bytewise access to FPR - uint8_t byte; - - /// bitwise access to register FPR - struct { - BITS WPB0 : 1; // bit 0 - BITS WPB1 : 1; // bit 1 - BITS WPB2 : 1; // bit 2 - BITS WPB3 : 1; // bit 3 - BITS WPB4 : 1; // bit 4 - BITS WPB5 : 1; // bit 5 - BITS : 2; // 2 bits - }; // FPR bitfield - - /// register _FLASH_FPR reset value - #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) - - } FPR; - - - /** Flash complementary protection register (NFPR at 0x505e) */ - union { - - /// bytewise access to NFPR - uint8_t byte; - - /// bitwise access to register NFPR - struct { - BITS NWPB0 : 1; // bit 0 - BITS NWPB1 : 1; // bit 1 - BITS NWPB2 : 1; // bit 2 - BITS NWPB3 : 1; // bit 3 - BITS NWPB4 : 1; // bit 4 - BITS NWPB5 : 1; // bit 5 - BITS : 2; // 2 bits - }; // NFPR bitfield - - /// register _FLASH_NFPR reset value - #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) - - } NFPR; - - - /** Flash in-application programming status register (IAPSR at 0x505f) */ - union { - - /// bytewise access to IAPSR - uint8_t byte; - - /// bitwise access to register IAPSR - struct { - BITS WR_PG_DIS : 1; // bit 0 - BITS PUL : 1; // bit 1 - BITS EOP : 1; // bit 2 - BITS DUL : 1; // bit 3 - BITS : 2; // 2 bits - BITS HVOFF : 1; // bit 6 - BITS : 1; // 1 bit - }; // IAPSR bitfield - - /// register _FLASH_IAPSR reset value - #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) - - } IAPSR; - - - /// Reserved register (2B) - uint8_t Reserved_1[2]; - - - /** Flash Program memory unprotection register (PUKR at 0x5062) */ - union { - - /// bytewise access to PUKR - uint8_t byte; - - /// bitwise access to register PUKR - struct { - BITS MASS_PRG : 8; // bits 0-7 - }; // PUKR bitfield - - /// register _FLASH_PUKR reset value - #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) - - } PUKR; - - - /// Reserved register (1B) - uint8_t Reserved_2[1]; - - - /** Data EEPROM unprotection register (DUKR at 0x5064) */ - union { - - /// bytewise access to DUKR - uint8_t byte; - - /// bitwise access to register DUKR - struct { - BITS MASS_DATA : 8; // bits 0-7 - }; // DUKR bitfield - - /// register _FLASH_DUKR reset value - #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) - - } DUKR; - -} FLASH_t; - -/// access to FLASH SFR registers -#define sfr_FLASH (*((FLASH_t*) 0x505a)) - - -//------------------------ -// Module I2C -//------------------------ - -/** struct containing I2C module registers */ -typedef struct { - - /** I2C control register 1 (CR1 at 0x5210) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PE : 1; // bit 0 - BITS : 5; // 5 bits - BITS ENGC : 1; // bit 6 - BITS NOSTRETCH : 1; // bit 7 - }; // CR1 bitfield - - /// register _I2C_CR1 reset value - #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** I2C control register 2 (CR2 at 0x5211) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS START : 1; // bit 0 - BITS STOP : 1; // bit 1 - BITS ACK : 1; // bit 2 - BITS POS : 1; // bit 3 - BITS : 3; // 3 bits - BITS SWRST : 1; // bit 7 - }; // CR2 bitfield - - /// register _I2C_CR2 reset value - #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** I2C frequency register (FREQR at 0x5212) */ - union { - - /// bytewise access to FREQR - uint8_t byte; - - /// bitwise access to register FREQR - struct { - BITS FREQ : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // FREQR bitfield - - /// register _I2C_FREQR reset value - #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) - - } FREQR; - - - /** I2C own address register low (OARL at 0x5213) */ - union { - - /// bytewise access to OARL - uint8_t byte; - - /// bitwise access to register OARL - struct { - BITS ADD0 : 1; // bit 0 - BITS ADD : 7; // bits 1-7 - }; // OARL bitfield - - /// register _I2C_OARL reset value - #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) - - } OARL; - - - /** I2C own address register high (OARH at 0x5214) */ - union { - - /// bytewise access to OARH - uint8_t byte; - - /// bitwise access to register OARH - struct { - BITS : 1; // 1 bit - BITS ADD : 2; // bits 1-2 - BITS : 3; // 3 bits - BITS ADDCONF : 1; // bit 6 - BITS ADDMODE : 1; // bit 7 - }; // OARH bitfield - - /// register _I2C_OARH reset value - #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) - - } OARH; - - - /// Reserved register (1B) - uint8_t Reserved_1[1]; - - - /** I2C data register (DR at 0x5216) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _I2C_DR reset value - #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** I2C status register 1 (SR1 at 0x5217) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS SB : 1; // bit 0 - BITS ADDR : 1; // bit 1 - BITS BTF : 1; // bit 2 - BITS ADD10 : 1; // bit 3 - BITS STOPF : 1; // bit 4 - BITS : 1; // 1 bit - BITS RXNE : 1; // bit 6 - BITS TXE : 1; // bit 7 - }; // SR1 bitfield - - /// register _I2C_SR1 reset value - #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** I2C status register 2 (SR2 at 0x5218) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS BERR : 1; // bit 0 - BITS ARLO : 1; // bit 1 - BITS AF : 1; // bit 2 - BITS OVR : 1; // bit 3 - BITS : 1; // 1 bit - BITS WUFH : 1; // bit 5 - BITS : 2; // 2 bits - }; // SR2 bitfield - - /// register _I2C_SR2 reset value - #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** I2C status register 3 (SR3 at 0x5219) */ - union { - - /// bytewise access to SR3 - uint8_t byte; - - /// bitwise access to register SR3 - struct { - BITS MSL : 1; // bit 0 - BITS BUSY : 1; // bit 1 - BITS TRA : 1; // bit 2 - BITS : 1; // 1 bit - BITS GENCALL : 1; // bit 4 - BITS : 3; // 3 bits - }; // SR3 bitfield - - /// register _I2C_SR3 reset value - #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) - - } SR3; - - - /** I2C interrupt control register (ITR at 0x521a) */ - union { - - /// bytewise access to ITR - uint8_t byte; - - /// bitwise access to register ITR - struct { - BITS ITERREN : 1; // bit 0 - BITS ITEVTEN : 1; // bit 1 - BITS ITBUFEN : 1; // bit 2 - BITS : 5; // 5 bits - }; // ITR bitfield - - /// register _I2C_ITR reset value - #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) - - } ITR; - - - /** I2C clock control register low (CCRL at 0x521b) */ - union { - - /// bytewise access to CCRL - uint8_t byte; - - /// bitwise access to register CCRL - struct { - BITS CCR : 8; // bits 0-7 - }; // CCRL bitfield - - /// register _I2C_CCRL reset value - #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) - - } CCRL; - - - /** I2C clock control register high (CCRH at 0x521c) */ - union { - - /// bytewise access to CCRH - uint8_t byte; - - /// bitwise access to register CCRH - struct { - BITS CCR : 4; // bits 0-3 - BITS : 2; // 2 bits - BITS DUTY : 1; // bit 6 - BITS F_S : 1; // bit 7 - }; // CCRH bitfield - - /// register _I2C_CCRH reset value - #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) - - } CCRH; - - - /** I2C TRISE register (TRISER at 0x521d) */ - union { - - /// bytewise access to TRISER - uint8_t byte; - - /// bitwise access to register TRISER - struct { - BITS TRISE : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // TRISER bitfield - - /// register _I2C_TRISER reset value - #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) - - } TRISER; - - - /** I2C packet error checking register (PECR at 0x521e) */ - union { - - /// bytewise access to PECR - uint8_t byte; - - /// skip bitwise access to register PECR - - /// register _I2C_PECR reset value - #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) - - } PECR; - -} I2C_t; - -/// access to I2C SFR registers -#define sfr_I2C (*((I2C_t*) 0x5210)) - - -//------------------------ -// Module ITC -//------------------------ - -/** struct containing ITC module registers */ -typedef struct { - - /** External interrupt control register 1 (CR1 at 0x50a0) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PAIS : 2; // bits 0-1 - BITS PBIS : 2; // bits 2-3 - BITS PCIS : 2; // bits 4-5 - BITS PDIS : 2; // bits 6-7 - }; // CR1 bitfield - - /// register _ITC_CR1 reset value - #define sfr_ITC_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** External interrupt control register 2 (CR2 at 0x50a1) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS PEIS : 2; // bits 0-1 - BITS TLIS : 1; // bit 2 - BITS : 5; // 5 bits - }; // CR2 bitfield - - /// register _ITC_CR2 reset value - #define sfr_ITC_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /// Reserved register (11982B) - uint8_t Reserved_1[11982]; - - - /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ - union { - - /// bytewise access to SPR1 - uint8_t byte; - - /// bitwise access to register SPR1 - struct { - BITS VECT0SPR : 2; // bits 0-1 - BITS VECT1SPR : 2; // bits 2-3 - BITS VECT2SPR : 2; // bits 4-5 - BITS VECT3SPR : 2; // bits 6-7 - }; // SPR1 bitfield - - /// register _ITC_SPR1 reset value - #define sfr_ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF) - - } SPR1; - - - /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ - union { - - /// bytewise access to SPR2 - uint8_t byte; - - /// bitwise access to register SPR2 - struct { - BITS VECT4SPR : 2; // bits 0-1 - BITS VECT5SPR : 2; // bits 2-3 - BITS VECT6SPR : 2; // bits 4-5 - BITS VECT7SPR : 2; // bits 6-7 - }; // SPR2 bitfield - - /// register _ITC_SPR2 reset value - #define sfr_ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF) - - } SPR2; - - - /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ - union { - - /// bytewise access to SPR3 - uint8_t byte; - - /// bitwise access to register SPR3 - struct { - BITS VECT8SPR : 2; // bits 0-1 - BITS VECT9SPR : 2; // bits 2-3 - BITS VECT10SPR : 2; // bits 4-5 - BITS VECT11SPR : 2; // bits 6-7 - }; // SPR3 bitfield - - /// register _ITC_SPR3 reset value - #define sfr_ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF) - - } SPR3; - - - /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ - union { - - /// bytewise access to SPR4 - uint8_t byte; - - /// bitwise access to register SPR4 - struct { - BITS VECT12SPR : 2; // bits 0-1 - BITS VECT13SPR : 2; // bits 2-3 - BITS VECT14SPR : 2; // bits 4-5 - BITS VECT15SPR : 2; // bits 6-7 - }; // SPR4 bitfield - - /// register _ITC_SPR4 reset value - #define sfr_ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF) - - } SPR4; - - - /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ - union { - - /// bytewise access to SPR5 - uint8_t byte; - - /// bitwise access to register SPR5 - struct { - BITS VECT16SPR : 2; // bits 0-1 - BITS VECT17SPR : 2; // bits 2-3 - BITS VECT18SPR : 2; // bits 4-5 - BITS VECT19SPR : 2; // bits 6-7 - }; // SPR5 bitfield - - /// register _ITC_SPR5 reset value - #define sfr_ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF) - - } SPR5; - - - /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ - union { - - /// bytewise access to SPR6 - uint8_t byte; - - /// bitwise access to register SPR6 - struct { - BITS VECT20SPR : 2; // bits 0-1 - BITS VECT21SPR : 2; // bits 2-3 - BITS VECT22SPR : 2; // bits 4-5 - BITS VECT23SPR : 2; // bits 6-7 - }; // SPR6 bitfield - - /// register _ITC_SPR6 reset value - #define sfr_ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF) - - } SPR6; - - - /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ - union { - - /// bytewise access to SPR7 - uint8_t byte; - - /// bitwise access to register SPR7 - struct { - BITS VECT24SPR : 2; // bits 0-1 - BITS VECT25SPR : 2; // bits 2-3 - BITS VECT26SPR : 2; // bits 4-5 - BITS VECT27SPR : 2; // bits 6-7 - }; // SPR7 bitfield - - /// register _ITC_SPR7 reset value - #define sfr_ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF) - - } SPR7; - - - /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ - union { - - /// bytewise access to SPR8 - uint8_t byte; - - /// bitwise access to register SPR8 - struct { - BITS VECT28SPR : 2; // bits 0-1 - BITS VECT29SPR : 2; // bits 2-3 - BITS : 4; // 4 bits - }; // SPR8 bitfield - - /// register _ITC_SPR8 reset value - #define sfr_ITC_SPR8_RESET_VALUE ((uint8_t) 0xFF) - - } SPR8; - -} ITC_t; - -/// access to ITC SFR registers -#define sfr_ITC (*((ITC_t*) 0x50a0)) - - -//------------------------ -// Module IWDG -//------------------------ - -/** struct containing IWDG module registers */ -typedef struct { - - /** IWDG key register (KR at 0x50e0) */ - union { - - /// bytewise access to KR - uint8_t byte; - - /// bitwise access to register KR - struct { - BITS KEY : 8; // bits 0-7 - }; // KR bitfield - - /// register _IWDG_KR reset value - #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) - - } KR; - - - /** IWDG prescaler register (PR at 0x50e1) */ - union { - - /// bytewise access to PR - uint8_t byte; - - /// bitwise access to register PR - struct { - BITS PR : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // PR bitfield - - /// register _IWDG_PR reset value - #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) - - } PR; - - - /** IWDG reload register (RLR at 0x50e2) */ - union { - - /// bytewise access to RLR - uint8_t byte; - - /// bitwise access to register RLR - struct { - BITS RL : 8; // bits 0-7 - }; // RLR bitfield - - /// register _IWDG_RLR reset value - #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) - - } RLR; - -} IWDG_t; - -/// access to IWDG SFR registers -#define sfr_IWDG (*((IWDG_t*) 0x50e0)) - - -//------------------------ -// Module OPT -//------------------------ - -/** struct containing OPT module registers */ -typedef struct { - - /** Read-out protection (ROP) (OPT0 at 0x4800) */ - union { - - /// bytewise access to OPT0 - uint8_t byte; - - /// skip bitwise access to register OPT0 - - /// register _OPT_OPT0 reset value - #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) - - } OPT0; - - - /** User boot code (UBC) (OPT1 at 0x4801) */ - union { - - /// bytewise access to OPT1 - uint8_t byte; - - /// skip bitwise access to register OPT1 - - /// register _OPT_OPT1 reset value - #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) - - } OPT1; - - - /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ - union { - - /// bytewise access to NOPT1 - uint8_t byte; - - /// skip bitwise access to register NOPT1 - - /// register _OPT_NOPT1 reset value - #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT1; - - - /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ - union { - - /// bytewise access to OPT2 - uint8_t byte; - - /// skip bitwise access to register OPT2 - - /// register _OPT_OPT2 reset value - #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) - - } OPT2; - - - /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ - union { - - /// bytewise access to NOPT2 - uint8_t byte; - - /// skip bitwise access to register NOPT2 - - /// register _OPT_NOPT2 reset value - #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT2; - - - /** Watchdog option (OPT3 at 0x4805) */ - union { - - /// bytewise access to OPT3 - uint8_t byte; - - /// skip bitwise access to register OPT3 - - /// register _OPT_OPT3 reset value - #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) - - } OPT3; - - - /** Watchdog option (complementary byte) (NOPT3 at 0x4806) */ - union { - - /// bytewise access to NOPT3 - uint8_t byte; - - /// skip bitwise access to register NOPT3 - - /// register _OPT_NOPT3 reset value - #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT3; - - - /** Clock option (OPT4 at 0x4807) */ - union { - - /// bytewise access to OPT4 - uint8_t byte; - - /// skip bitwise access to register OPT4 - - /// register _OPT_OPT4 reset value - #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) - - } OPT4; - - - /** Clock option (complementary byte) (NOPT4 at 0x4808) */ - union { - - /// bytewise access to NOPT4 - uint8_t byte; - - /// skip bitwise access to register NOPT4 - - /// register _OPT_NOPT4 reset value - #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT4; - - - /** HSE clock startup (OPT5 at 0x4809) */ - union { - - /// bytewise access to OPT5 - uint8_t byte; - - /// skip bitwise access to register OPT5 - - /// register _OPT_OPT5 reset value - #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) - - } OPT5; - - - /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ - union { - - /// bytewise access to NOPT5 - uint8_t byte; - - /// skip bitwise access to register NOPT5 - - /// register _OPT_NOPT5 reset value - #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT5; - - - /// Reserved register (2B) - uint8_t Reserved_1[2]; - - - /** Flash wait states (OPT7 at 0x480d) */ - union { - - /// bytewise access to OPT7 - uint8_t byte; - - /// skip bitwise access to register OPT7 - - /// register _OPT_OPT7 reset value - #define sfr_OPT_OPT7_RESET_VALUE ((uint8_t) 0x00) - - } OPT7; - - - /** Flash wait states (complementary byte) (NOPT7 at 0x480e) */ - union { - - /// bytewise access to NOPT7 - uint8_t byte; - - /// skip bitwise access to register NOPT7 - - /// register _OPT_NOPT7 reset value - #define sfr_OPT_NOPT7_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT7; - - - /// Reserved register (111B) - uint8_t Reserved_2[111]; - - - /** Bootloader (OPTBL at 0x487e) */ - union { - - /// bytewise access to OPTBL - uint8_t byte; - - /// skip bitwise access to register OPTBL - - /// register _OPT_OPTBL reset value - #define sfr_OPT_OPTBL_RESET_VALUE ((uint8_t) 0x00) - - } OPTBL; - - - /** Bootloader (complementary byte) (NOPTBL at 0x487f) */ - union { - - /// bytewise access to NOPTBL - uint8_t byte; - - /// skip bitwise access to register NOPTBL - - /// register _OPT_NOPTBL reset value - #define sfr_OPT_NOPTBL_RESET_VALUE ((uint8_t) 0xFF) - - } NOPTBL; - -} OPT_t; - -/// access to OPT SFR registers -#define sfr_OPT (*((OPT_t*) 0x4800)) - - -//------------------------ -// Module PORT -//------------------------ - -/** struct containing PORTA module registers */ -typedef struct { - - /** Port A data output latch register (ODR at 0x5000) */ - union { - - /// bytewise access to ODR - uint8_t byte; - - /// bitwise access to register ODR - struct { - BITS ODR0 : 1; // bit 0 - BITS ODR1 : 1; // bit 1 - BITS ODR2 : 1; // bit 2 - BITS ODR3 : 1; // bit 3 - BITS ODR4 : 1; // bit 4 - BITS ODR5 : 1; // bit 5 - BITS ODR6 : 1; // bit 6 - BITS ODR7 : 1; // bit 7 - }; // ODR bitfield - - /// register _PORT_ODR reset value - #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) - - } ODR; - - - /** Port A input pin value register (IDR at 0x5001) */ - union { - - /// bytewise access to IDR - uint8_t byte; - - /// bitwise access to register IDR - struct { - BITS IDR0 : 1; // bit 0 - BITS IDR1 : 1; // bit 1 - BITS IDR2 : 1; // bit 2 - BITS IDR3 : 1; // bit 3 - BITS IDR4 : 1; // bit 4 - BITS IDR5 : 1; // bit 5 - BITS IDR6 : 1; // bit 6 - BITS IDR7 : 1; // bit 7 - }; // IDR bitfield - - /// register _PORT_IDR reset value - #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) - - } IDR; - - - /** Port A data direction register (DDR at 0x5002) */ - union { - - /// bytewise access to DDR - uint8_t byte; - - /// bitwise access to register DDR - struct { - BITS DDR0 : 1; // bit 0 - BITS DDR1 : 1; // bit 1 - BITS DDR2 : 1; // bit 2 - BITS DDR3 : 1; // bit 3 - BITS DDR4 : 1; // bit 4 - BITS DDR5 : 1; // bit 5 - BITS DDR6 : 1; // bit 6 - BITS DDR7 : 1; // bit 7 - }; // DDR bitfield - - /// register _PORT_DDR reset value - #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) - - } DDR; - - - /** Port A control register 1 (CR1 at 0x5003) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS C10 : 1; // bit 0 - BITS C11 : 1; // bit 1 - BITS C12 : 1; // bit 2 - BITS C13 : 1; // bit 3 - BITS C14 : 1; // bit 4 - BITS C15 : 1; // bit 5 - BITS C16 : 1; // bit 6 - BITS C17 : 1; // bit 7 - }; // CR1 bitfield - - /// register _PORT_CR1 reset value - #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** Port A control register 2 (CR2 at 0x5004) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS C20 : 1; // bit 0 - BITS C21 : 1; // bit 1 - BITS C22 : 1; // bit 2 - BITS C23 : 1; // bit 3 - BITS C24 : 1; // bit 4 - BITS C25 : 1; // bit 5 - BITS C26 : 1; // bit 6 - BITS C27 : 1; // bit 7 - }; // CR2 bitfield - - /// register _PORT_CR2 reset value - #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - -} PORT_t; - -/// access to PORTA SFR registers -#define sfr_PORTA (*((PORT_t*) 0x5000)) - - -/// access to PORTB SFR registers -#define sfr_PORTB (*((PORT_t*) 0x5005)) - - -/// access to PORTC SFR registers -#define sfr_PORTC (*((PORT_t*) 0x500a)) - - -/// access to PORTD SFR registers -#define sfr_PORTD (*((PORT_t*) 0x500f)) - - -/// access to PORTE SFR registers -#define sfr_PORTE (*((PORT_t*) 0x5014)) - - -/// access to PORTF SFR registers -#define sfr_PORTF (*((PORT_t*) 0x5019)) - - -/// access to PORTG SFR registers -#define sfr_PORTG (*((PORT_t*) 0x501e)) - - -/// access to PORTH SFR registers -#define sfr_PORTH (*((PORT_t*) 0x5023)) - - -/// access to PORTI SFR registers -#define sfr_PORTI (*((PORT_t*) 0x5028)) - - -//------------------------ -// Module RST -//------------------------ - -/** struct containing RST module registers */ -typedef struct { - - /** Reset status register (SR at 0x50b3) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS WWDGF : 1; // bit 0 - BITS IWDGF : 1; // bit 1 - BITS ILLOPF : 1; // bit 2 - BITS SWIMF : 1; // bit 3 - BITS EMCF : 1; // bit 4 - BITS : 3; // 3 bits - }; // SR bitfield - - /// register _RST_SR reset value - #define sfr_RST_SR_RESET_VALUE ((uint8_t) 0x00) - - } SR; - -} RST_t; - -/// access to RST SFR registers -#define sfr_RST (*((RST_t*) 0x50b3)) - - -//------------------------ -// Module SPI -//------------------------ - -/** struct containing SPI module registers */ -typedef struct { - - /** SPI control register 1 (CR1 at 0x5200) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CPHA : 1; // bit 0 - BITS CPOL : 1; // bit 1 - BITS MSTR : 1; // bit 2 - BITS BR : 3; // bits 3-5 - BITS SPE : 1; // bit 6 - BITS LSBFIRST : 1; // bit 7 - }; // CR1 bitfield - - /// register _SPI_CR1 reset value - #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** SPI control register 2 (CR2 at 0x5201) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS SSI : 1; // bit 0 - BITS SSM : 1; // bit 1 - BITS RXONLY : 1; // bit 2 - BITS : 1; // 1 bit - BITS CRCNEXT : 1; // bit 4 - BITS CECEN : 1; // bit 5 - BITS BDOE : 1; // bit 6 - BITS BDM : 1; // bit 7 - }; // CR2 bitfield - - /// register _SPI_CR2 reset value - #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** SPI interrupt control register (ICR at 0x5202) */ - union { - - /// bytewise access to ICR - uint8_t byte; - - /// bitwise access to register ICR - struct { - BITS : 4; // 4 bits - BITS WKIE : 1; // bit 4 - BITS ERRIE : 1; // bit 5 - BITS RXIE : 1; // bit 6 - BITS TXIE : 1; // bit 7 - }; // ICR bitfield - - /// register _SPI_ICR reset value - #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) - - } ICR; - - - /** SPI status register (SR at 0x5203) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS RXNE : 1; // bit 0 - BITS TXE : 1; // bit 1 - BITS : 1; // 1 bit - BITS WKUP : 1; // bit 3 - BITS CRCERR : 1; // bit 4 - BITS MODF : 1; // bit 5 - BITS OVR : 1; // bit 6 - BITS BSY : 1; // bit 7 - }; // SR bitfield - - /// register _SPI_SR reset value - #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) - - } SR; - - - /** SPI data register (DR at 0x5204) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _SPI_DR reset value - #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** SPI CRC polynomial register (CRCPR at 0x5205) */ - union { - - /// bytewise access to CRCPR - uint8_t byte; - - /// bitwise access to register CRCPR - struct { - BITS CRCPOLY : 8; // bits 0-7 - }; // CRCPR bitfield - - /// register _SPI_CRCPR reset value - #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) - - } CRCPR; - - - /** SPI Rx CRC register (RXCRCR at 0x5206) */ - union { - - /// bytewise access to RXCRCR - uint8_t byte; - - /// bitwise access to register RXCRCR - struct { - BITS RXCRC : 8; // bits 0-7 - }; // RXCRCR bitfield - - /// register _SPI_RXCRCR reset value - #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) - - } RXCRCR; - - - /** SPI Tx CRC register (TXCRCR at 0x5207) */ - union { - - /// bytewise access to TXCRCR - uint8_t byte; - - /// bitwise access to register TXCRCR - struct { - BITS TXCRC : 8; // bits 0-7 - }; // TXCRCR bitfield - - /// register _SPI_TXCRCR reset value - #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) - - } TXCRCR; - -} SPI_t; - -/// access to SPI SFR registers -#define sfr_SPI (*((SPI_t*) 0x5200)) - - -//------------------------ -// Module SWIM -//------------------------ - -/** struct containing SWIM module registers */ -typedef struct { - - /** SWIM control status register (CSR at 0x7f80) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// skip bitwise access to register CSR - - /// register _SWIM_CSR reset value - #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) - - } CSR; - -} SWIM_t; - -/// access to SWIM SFR registers -#define sfr_SWIM (*((SWIM_t*) 0x7f80)) - - -//------------------------ -// Module TIM1 -//------------------------ - -/** struct containing TIM1 module registers */ -typedef struct { - - /** TIM1 control register 1 (CR1 at 0x5250) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS DIR : 1; // bit 4 - BITS CMS : 2; // bits 5-6 - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM1_CR1 reset value - #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM1 control register 2 (CR2 at 0x5251) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS CCPG : 1; // bit 0 - BITS : 1; // 1 bit - BITS COMS : 1; // bit 2 - BITS : 1; // 1 bit - BITS MMS : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CR2 bitfield - - /// register _TIM1_CR2 reset value - #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** TIM1 slave mode control register (SMCR at 0x5252) */ - union { - - /// bytewise access to SMCR - uint8_t byte; - - /// bitwise access to register SMCR - struct { - BITS SMS : 3; // bits 0-2 - BITS : 1; // 1 bit - BITS TS : 3; // bits 4-6 - BITS MSM : 1; // bit 7 - }; // SMCR bitfield - - /// register _TIM1_SMCR reset value - #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) - - } SMCR; - - - /** TIM1 external trigger register (ETR at 0x5253) */ - union { - - /// bytewise access to ETR - uint8_t byte; - - /// bitwise access to register ETR - struct { - BITS ETF : 4; // bits 0-3 - BITS ETPS : 2; // bits 4-5 - BITS ECE : 1; // bit 6 - BITS ETP : 1; // bit 7 - }; // ETR bitfield - - /// register _TIM1_ETR reset value - #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) - - } ETR; - - - /** TIM1 Interrupt enable register (IER at 0x5254) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS CC1IE : 1; // bit 1 - BITS CC2IE : 1; // bit 2 - BITS CC3IE : 1; // bit 3 - BITS CC4IE : 1; // bit 4 - BITS COMIE : 1; // bit 5 - BITS TIE : 1; // bit 6 - BITS BIE : 1; // bit 7 - }; // IER bitfield - - /// register _TIM1_IER reset value - #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM1 status register 1 (SR1 at 0x5255) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS UIF : 1; // bit 0 - BITS CC1IF : 1; // bit 1 - BITS CC2IF : 1; // bit 2 - BITS CC3IF : 1; // bit 3 - BITS CC4IF : 1; // bit 4 - BITS COMIF : 1; // bit 5 - BITS TIF : 1; // bit 6 - BITS BIF : 1; // bit 7 - }; // SR1 bitfield - - /// register _TIM1_SR1 reset value - #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** TIM1 status register 2 (SR2 at 0x5256) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS : 1; // 1 bit - BITS CC1OF : 1; // bit 1 - BITS CC2OF : 1; // bit 2 - BITS CC3OF : 1; // bit 3 - BITS CC4OF : 1; // bit 4 - BITS : 3; // 3 bits - }; // SR2 bitfield - - /// register _TIM1_SR2 reset value - #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** TIM1 event generation register (EGR at 0x5257) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS CC1G : 1; // bit 1 - BITS CC2G : 1; // bit 2 - BITS CC3G : 1; // bit 3 - BITS CC4G : 1; // bit 4 - BITS COMG : 1; // bit 5 - BITS TG : 1; // bit 6 - BITS BG : 1; // bit 7 - }; // EGR bitfield - - /// register _TIM1_EGR reset value - #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ - union { - - /// bytewise access to CCMR1 - uint8_t byte; - - /// bitwise access to register CCMR1 - struct { - BITS CC1S : 2; // bits 0-1 - BITS OC1FE : 1; // bit 2 - BITS OC1PE : 1; // bit 3 - BITS OC1M : 3; // bits 4-6 - BITS OC1CE : 1; // bit 7 - }; // CCMR1 bitfield - - /// register _TIM1_CCMR1 reset value - #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) - - } CCMR1; - - - /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ - union { - - /// bytewise access to CCMR2 - uint8_t byte; - - /// bitwise access to register CCMR2 - struct { - BITS CC2S : 2; // bits 0-1 - BITS OC2FE : 1; // bit 2 - BITS OC2PE : 1; // bit 3 - BITS OC2M : 3; // bits 4-6 - BITS OC2CE : 1; // bit 7 - }; // CCMR2 bitfield - - /// register _TIM1_CCMR2 reset value - #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) - - } CCMR2; - - - /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ - union { - - /// bytewise access to CCMR3 - uint8_t byte; - - /// bitwise access to register CCMR3 - struct { - BITS CC3S : 2; // bits 0-1 - BITS OC3FE : 1; // bit 2 - BITS OC3PE : 1; // bit 3 - BITS OC3M : 3; // bits 4-6 - BITS OC3CE : 1; // bit 7 - }; // CCMR3 bitfield - - /// register _TIM1_CCMR3 reset value - #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) - - } CCMR3; - - - /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ - union { - - /// bytewise access to CCMR4 - uint8_t byte; - - /// bitwise access to register CCMR4 - struct { - BITS CC4S : 2; // bits 0-1 - BITS OC4FE : 1; // bit 2 - BITS OC4PE : 1; // bit 3 - BITS OC4M : 3; // bits 4-6 - BITS OC4CE : 1; // bit 7 - }; // CCMR4 bitfield - - /// register _TIM1_CCMR4 reset value - #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) - - } CCMR4; - - - /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ - union { - - /// bytewise access to CCER1 - uint8_t byte; - - /// bitwise access to register CCER1 - struct { - BITS CC1E : 1; // bit 0 - BITS CC1P : 1; // bit 1 - BITS CC1NE : 1; // bit 2 - BITS CC1NP : 1; // bit 3 - BITS CC2E : 1; // bit 4 - BITS CC2P : 1; // bit 5 - BITS CC2NE : 1; // bit 6 - BITS CC2NP : 1; // bit 7 - }; // CCER1 bitfield - - /// register _TIM1_CCER1 reset value - #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) - - } CCER1; - - - /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ - union { - - /// bytewise access to CCER2 - uint8_t byte; - - /// bitwise access to register CCER2 - struct { - BITS CC3E : 1; // bit 0 - BITS CC3P : 1; // bit 1 - BITS CC3NE : 1; // bit 2 - BITS CC3NP : 1; // bit 3 - BITS CC4E : 1; // bit 4 - BITS CC4P : 1; // bit 5 - BITS : 2; // 2 bits - }; // CCER2 bitfield - - /// register _TIM1_CCER2 reset value - #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) - - } CCER2; - - - /** TIM1 counter high (CNTRH at 0x525e) */ - union { - - /// bytewise access to CNTRH - uint8_t byte; - - /// bitwise access to register CNTRH - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRH bitfield - - /// register _TIM1_CNTRH reset value - #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) - - } CNTRH; - - - /** TIM1 counter low (CNTRL at 0x525f) */ - union { - - /// bytewise access to CNTRL - uint8_t byte; - - /// bitwise access to register CNTRL - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRL bitfield - - /// register _TIM1_CNTRL reset value - #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) - - } CNTRL; - - - /** TIM1 prescaler register high (PSCRH at 0x5260) */ - union { - - /// bytewise access to PSCRH - uint8_t byte; - - /// bitwise access to register PSCRH - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCRH bitfield - - /// register _TIM1_PSCRH reset value - #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) - - } PSCRH; - - - /** TIM1 prescaler register low (PSCRL at 0x5261) */ - union { - - /// bytewise access to PSCRL - uint8_t byte; - - /// bitwise access to register PSCRL - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCRL bitfield - - /// register _TIM1_PSCRL reset value - #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) - - } PSCRL; - - - /** TIM1 auto-reload register high (ARRH at 0x5262) */ - union { - - /// bytewise access to ARRH - uint8_t byte; - - /// bitwise access to register ARRH - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRH bitfield - - /// register _TIM1_ARRH reset value - #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) - - } ARRH; - - - /** TIM1 auto-reload register low (ARRL at 0x5263) */ - union { - - /// bytewise access to ARRL - uint8_t byte; - - /// bitwise access to register ARRL - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRL bitfield - - /// register _TIM1_ARRL reset value - #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) - - } ARRL; - - - /** TIM1 repetition counter register (RCR at 0x5264) */ - union { - - /// bytewise access to RCR - uint8_t byte; - - /// bitwise access to register RCR - struct { - BITS REP : 8; // bits 0-7 - }; // RCR bitfield - - /// register _TIM1_RCR reset value - #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) - - } RCR; - - - /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ - union { - - /// bytewise access to CCR1H - uint8_t byte; - - /// bitwise access to register CCR1H - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1H bitfield - - /// register _TIM1_CCR1H reset value - #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) - - } CCR1H; - - - /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ - union { - - /// bytewise access to CCR1L - uint8_t byte; - - /// bitwise access to register CCR1L - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1L bitfield - - /// register _TIM1_CCR1L reset value - #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) - - } CCR1L; - - - /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ - union { - - /// bytewise access to CCR2H - uint8_t byte; - - /// bitwise access to register CCR2H - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2H bitfield - - /// register _TIM1_CCR2H reset value - #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) - - } CCR2H; - - - /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ - union { - - /// bytewise access to CCR2L - uint8_t byte; - - /// bitwise access to register CCR2L - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2L bitfield - - /// register _TIM1_CCR2L reset value - #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) - - } CCR2L; - - - /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ - union { - - /// bytewise access to CCR3H - uint8_t byte; - - /// bitwise access to register CCR3H - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3H bitfield - - /// register _TIM1_CCR3H reset value - #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) - - } CCR3H; - - - /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ - union { - - /// bytewise access to CCR3L - uint8_t byte; - - /// bitwise access to register CCR3L - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3L bitfield - - /// register _TIM1_CCR3L reset value - #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) - - } CCR3L; - - - /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ - union { - - /// bytewise access to CCR4H - uint8_t byte; - - /// bitwise access to register CCR4H - struct { - BITS CCR4 : 8; // bits 0-7 - }; // CCR4H bitfield - - /// register _TIM1_CCR4H reset value - #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) - - } CCR4H; - - - /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ - union { - - /// bytewise access to CCR4L - uint8_t byte; - - /// bitwise access to register CCR4L - struct { - BITS CCR4 : 8; // bits 0-7 - }; // CCR4L bitfield - - /// register _TIM1_CCR4L reset value - #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) - - } CCR4L; - - - /** TIM1 break register (BKR at 0x526d) */ - union { - - /// bytewise access to BKR - uint8_t byte; - - /// bitwise access to register BKR - struct { - BITS LOCK : 2; // bits 0-1 - BITS OSSI : 1; // bit 2 - BITS OSSR : 1; // bit 3 - BITS BKE : 1; // bit 4 - BITS BKP : 1; // bit 5 - BITS AOE : 1; // bit 6 - BITS MOE : 1; // bit 7 - }; // BKR bitfield - - /// register _TIM1_BKR reset value - #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) - - } BKR; - - - /** TIM1 dead-time register (DTR at 0x526e) */ - union { - - /// bytewise access to DTR - uint8_t byte; - - /// bitwise access to register DTR - struct { - BITS DTG : 8; // bits 0-7 - }; // DTR bitfield - - /// register _TIM1_DTR reset value - #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) - - } DTR; - - - /** TIM1 output idle state register (OISR at 0x526f) */ - union { - - /// bytewise access to OISR - uint8_t byte; - - /// bitwise access to register OISR - struct { - BITS OIS1 : 1; // bit 0 - BITS OIS1N : 1; // bit 1 - BITS OIS2 : 1; // bit 2 - BITS OIS2N : 1; // bit 3 - BITS OIS3 : 1; // bit 4 - BITS OIS3N : 1; // bit 5 - BITS OIS4 : 1; // bit 6 - BITS : 1; // 1 bit - }; // OISR bitfield - - /// register _TIM1_OISR reset value - #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) - - } OISR; - -} TIM1_t; - -/// access to TIM1 SFR registers -#define sfr_TIM1 (*((TIM1_t*) 0x5250)) - - -//------------------------ -// Module TIM2 -//------------------------ - -/** struct containing TIM2 module registers */ -typedef struct { - - /** TIM2 control register 1 (CR1 at 0x5300) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS : 3; // 3 bits - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM2_CR1 reset value - #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM2 interrupt enable register (IER at 0x5301) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS CC1IE : 1; // bit 1 - BITS CC2IE : 1; // bit 2 - BITS CC3IE : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIE : 1; // bit 6 - BITS : 1; // 1 bit - }; // IER bitfield - - /// register _TIM2_IER reset value - #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM2 status register 1 (SR1 at 0x5302) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS UIF : 1; // bit 0 - BITS CC1IF : 1; // bit 1 - BITS CC2IF : 1; // bit 2 - BITS CC3IF : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIF : 1; // bit 6 - BITS : 1; // 1 bit - }; // SR1 bitfield - - /// register _TIM2_SR1 reset value - #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** TIM2 status register 2 (SR2 at 0x5303) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS : 1; // 1 bit - BITS CC1OF : 1; // bit 1 - BITS CC2OF : 1; // bit 2 - BITS CC3OF : 1; // bit 3 - BITS : 4; // 4 bits - }; // SR2 bitfield - - /// register _TIM2_SR2 reset value - #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** TIM2 event generation register (EGR at 0x5304) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS CC1G : 1; // bit 1 - BITS CC2G : 1; // bit 2 - BITS CC3G : 1; // bit 3 - BITS : 2; // 2 bits - BITS TG : 1; // bit 6 - BITS : 1; // 1 bit - }; // EGR bitfield - - /// register _TIM2_EGR reset value - #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5305) */ - union { - - /// bytewise access to CCMR1 - uint8_t byte; - - /// bitwise access to register CCMR1 - struct { - BITS CC1S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC1PE : 1; // bit 3 - BITS OC1M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR1 bitfield - - /// register _TIM2_CCMR1 reset value - #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) - - } CCMR1; - - - /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5306) */ - union { - - /// bytewise access to CCMR2 - uint8_t byte; - - /// bitwise access to register CCMR2 - struct { - BITS CC2S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC2PE : 1; // bit 3 - BITS OC2M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR2 bitfield - - /// register _TIM2_CCMR2 reset value - #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) - - } CCMR2; - - - /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5307) */ - union { - - /// bytewise access to CCMR3 - uint8_t byte; - - /// bitwise access to register CCMR3 - struct { - BITS CC3S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC3PE : 1; // bit 3 - BITS OC3M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR3 bitfield - - /// register _TIM2_CCMR3 reset value - #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) - - } CCMR3; - - - /** TIM2 capture/compare enable register 1 (CCER1 at 0x5308) */ - union { - - /// bytewise access to CCER1 - uint8_t byte; - - /// bitwise access to register CCER1 - struct { - BITS CC1E : 1; // bit 0 - BITS CC1P : 1; // bit 1 - BITS : 2; // 2 bits - BITS CC2E : 1; // bit 4 - BITS CC2P : 1; // bit 5 - BITS : 2; // 2 bits - }; // CCER1 bitfield - - /// register _TIM2_CCER1 reset value - #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) - - } CCER1; - - - /** TIM2 capture/compare enable register 2 (CCER2 at 0x5309) */ - union { - - /// bytewise access to CCER2 - uint8_t byte; - - /// bitwise access to register CCER2 - struct { - BITS CC3E : 1; // bit 0 - BITS CC3P : 1; // bit 1 - BITS : 6; // 6 bits - }; // CCER2 bitfield - - /// register _TIM2_CCER2 reset value - #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) - - } CCER2; - - - /** TIM2 counter high (CNTRH at 0x530a) */ - union { - - /// bytewise access to CNTRH - uint8_t byte; - - /// bitwise access to register CNTRH - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRH bitfield - - /// register _TIM2_CNTRH reset value - #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) - - } CNTRH; - - - /** TIM2 counter low (CNTRL at 0x530b) */ - union { - - /// bytewise access to CNTRL - uint8_t byte; - - /// bitwise access to register CNTRL - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRL bitfield - - /// register _TIM2_CNTRL reset value - #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) - - } CNTRL; - - - /** TIM2 prescaler register (PSCR at 0x530c) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // PSCR bitfield - - /// register _TIM2_PSCR reset value - #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - - - /** TIM2 auto-reload register high (ARRH at 0x530d) */ - union { - - /// bytewise access to ARRH - uint8_t byte; - - /// bitwise access to register ARRH - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRH bitfield - - /// register _TIM2_ARRH reset value - #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) - - } ARRH; - - - /** TIM2 auto-reload register low (ARRL at 0x530e) */ - union { - - /// bytewise access to ARRL - uint8_t byte; - - /// bitwise access to register ARRL - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRL bitfield - - /// register _TIM2_ARRL reset value - #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) - - } ARRL; - - - /** TIM2 capture/compare register 1 high (CCR1H at 0x530f) */ - union { - - /// bytewise access to CCR1H - uint8_t byte; - - /// bitwise access to register CCR1H - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1H bitfield - - /// register _TIM2_CCR1H reset value - #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) - - } CCR1H; - - - /** TIM2 capture/compare register 1 low (CCR1L at 0x5310) */ - union { - - /// bytewise access to CCR1L - uint8_t byte; - - /// bitwise access to register CCR1L - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1L bitfield - - /// register _TIM2_CCR1L reset value - #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) - - } CCR1L; - - - /** TIM2 capture/compare reg (CCR2H at 0x5311) */ - union { - - /// bytewise access to CCR2H - uint8_t byte; - - /// bitwise access to register CCR2H - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2H bitfield - - /// register _TIM2_CCR2H reset value - #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) - - } CCR2H; - - - /** TIM2 capture/compare register 2 low (CCR2L at 0x5312) */ - union { - - /// bytewise access to CCR2L - uint8_t byte; - - /// bitwise access to register CCR2L - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2L bitfield - - /// register _TIM2_CCR2L reset value - #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) - - } CCR2L; - - - /** TIM2 capture/compare register 3 high (CCR3H at 0x5313) */ - union { - - /// bytewise access to CCR3H - uint8_t byte; - - /// bitwise access to register CCR3H - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3H bitfield - - /// register _TIM2_CCR3H reset value - #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) - - } CCR3H; - - - /** TIM2 capture/compare register 3 low (CCR3L at 0x5314) */ - union { - - /// bytewise access to CCR3L - uint8_t byte; - - /// bitwise access to register CCR3L - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3L bitfield - - /// register _TIM2_CCR3L reset value - #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) - - } CCR3L; - -} TIM2_t; - -/// access to TIM2 SFR registers -#define sfr_TIM2 (*((TIM2_t*) 0x5300)) - - -//------------------------ -// Module TIM3 -//------------------------ - -/** struct containing TIM3 module registers */ -typedef struct { - - /** TIM3 control register 1 (CR1 at 0x5320) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS : 3; // 3 bits - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM3_CR1 reset value - #define sfr_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM3 interrupt enable register (IER at 0x5321) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS CC1IE : 1; // bit 1 - BITS CC2IE : 1; // bit 2 - BITS CC3IE : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIE : 1; // bit 6 - BITS : 1; // 1 bit - }; // IER bitfield - - /// register _TIM3_IER reset value - #define sfr_TIM3_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM3 status register 1 (SR1 at 0x5322) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS UIF : 1; // bit 0 - BITS CC1IF : 1; // bit 1 - BITS CC2IF : 1; // bit 2 - BITS CC3IF : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIF : 1; // bit 6 - BITS : 1; // 1 bit - }; // SR1 bitfield - - /// register _TIM3_SR1 reset value - #define sfr_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** TIM3 status register 2 (SR2 at 0x5323) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS : 1; // 1 bit - BITS CC1OF : 1; // bit 1 - BITS CC2OF : 1; // bit 2 - BITS CC3OF : 1; // bit 3 - BITS : 4; // 4 bits - }; // SR2 bitfield - - /// register _TIM3_SR2 reset value - #define sfr_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** TIM3 event generation register (EGR at 0x5324) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS CC1G : 1; // bit 1 - BITS CC2G : 1; // bit 2 - BITS CC3G : 1; // bit 3 - BITS : 2; // 2 bits - BITS TG : 1; // bit 6 - BITS : 1; // 1 bit - }; // EGR bitfield - - /// register _TIM3_EGR reset value - #define sfr_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM3 capture/compare mode register 1 (CCMR1 at 0x5325) */ - union { - - /// bytewise access to CCMR1 - uint8_t byte; - - /// bitwise access to register CCMR1 - struct { - BITS CC1S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC1PE : 1; // bit 3 - BITS OC1M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR1 bitfield - - /// register _TIM3_CCMR1 reset value - #define sfr_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00) - - } CCMR1; - - - /** TIM3 capture/compare mode register 2 (CCMR2 at 0x5326) */ - union { - - /// bytewise access to CCMR2 - uint8_t byte; - - /// bitwise access to register CCMR2 - struct { - BITS CC2S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC2PE : 1; // bit 3 - BITS OC2M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR2 bitfield - - /// register _TIM3_CCMR2 reset value - #define sfr_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00) - - } CCMR2; - - - /** TIM3 capture/compare enable register 1 (CCER1 at 0x5327) */ - union { - - /// bytewise access to CCER1 - uint8_t byte; - - /// bitwise access to register CCER1 - struct { - BITS CC1E : 1; // bit 0 - BITS CC1P : 1; // bit 1 - BITS : 2; // 2 bits - BITS CC2E : 1; // bit 4 - BITS CC2P : 1; // bit 5 - BITS : 2; // 2 bits - }; // CCER1 bitfield - - /// register _TIM3_CCER1 reset value - #define sfr_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00) - - } CCER1; - - - /** TIM3 counter high (CNTRH at 0x5328) */ - union { - - /// bytewise access to CNTRH - uint8_t byte; - - /// bitwise access to register CNTRH - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRH bitfield - - /// register _TIM3_CNTRH reset value - #define sfr_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00) - - } CNTRH; - - - /** TIM3 counter low (CNTRL at 0x5329) */ - union { - - /// bytewise access to CNTRL - uint8_t byte; - - /// bitwise access to register CNTRL - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRL bitfield - - /// register _TIM3_CNTRL reset value - #define sfr_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00) - - } CNTRL; - - - /** TIM3 prescaler register (PSCR at 0x532a) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // PSCR bitfield - - /// register _TIM3_PSCR reset value - #define sfr_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - - - /** TIM3 auto-reload register high (ARRH at 0x532b) */ - union { - - /// bytewise access to ARRH - uint8_t byte; - - /// bitwise access to register ARRH - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRH bitfield - - /// register _TIM3_ARRH reset value - #define sfr_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF) - - } ARRH; - - - /** TIM3 auto-reload register low (ARRL at 0x532c) */ - union { - - /// bytewise access to ARRL - uint8_t byte; - - /// bitwise access to register ARRL - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRL bitfield - - /// register _TIM3_ARRL reset value - #define sfr_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF) - - } ARRL; - - - /** TIM3 capture/compare register 1 high (CCR1H at 0x532d) */ - union { - - /// bytewise access to CCR1H - uint8_t byte; - - /// bitwise access to register CCR1H - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1H bitfield - - /// register _TIM3_CCR1H reset value - #define sfr_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00) - - } CCR1H; - - - /** TIM3 capture/compare register 1 low (CCR1L at 0x532e) */ - union { - - /// bytewise access to CCR1L - uint8_t byte; - - /// bitwise access to register CCR1L - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1L bitfield - - /// register _TIM3_CCR1L reset value - #define sfr_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00) - - } CCR1L; - - - /** TIM3 capture/compare register 2 high (CCR2H at 0x532f) */ - union { - - /// bytewise access to CCR2H - uint8_t byte; - - /// bitwise access to register CCR2H - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2H bitfield - - /// register _TIM3_CCR2H reset value - #define sfr_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00) - - } CCR2H; - - - /** TIM3 capture/compare register 2 low (CCR2L at 0x5330) */ - union { - - /// bytewise access to CCR2L - uint8_t byte; - - /// bitwise access to register CCR2L - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2L bitfield - - /// register _TIM3_CCR2L reset value - #define sfr_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00) - - } CCR2L; - -} TIM3_t; - -/// access to TIM3 SFR registers -#define sfr_TIM3 (*((TIM3_t*) 0x5320)) - - -//------------------------ -// Module TIM4 -//------------------------ - -/** struct containing TIM4 module registers */ -typedef struct { - - /** TIM4 control register 1 (CR1 at 0x5340) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS : 3; // 3 bits - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM4_CR1 reset value - #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM4 interrupt enable register (IER at 0x5341) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS : 5; // 5 bits - BITS TIE : 1; // bit 6 - BITS : 1; // 1 bit - }; // IER bitfield - - /// register _TIM4_IER reset value - #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM4 status register (SR at 0x5342) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS UIF : 1; // bit 0 - BITS : 5; // 5 bits - BITS TIF : 1; // bit 6 - BITS : 1; // 1 bit - }; // SR bitfield - - /// register _TIM4_SR reset value - #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) - - } SR; - - - /** TIM4 event generation register (EGR at 0x5343) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS : 5; // 5 bits - BITS TG : 1; // bit 6 - BITS : 1; // 1 bit - }; // EGR bitfield - - /// register _TIM4_EGR reset value - #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM4 counter (CNTR at 0x5344) */ - union { - - /// bytewise access to CNTR - uint8_t byte; - - /// bitwise access to register CNTR - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTR bitfield - - /// register _TIM4_CNTR reset value - #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) - - } CNTR; - - - /** TIM4 prescaler register (PSCR at 0x5345) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // PSCR bitfield - - /// register _TIM4_PSCR reset value - #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - - - /** TIM4 auto-reload register (ARR at 0x5346) */ - union { - - /// bytewise access to ARR - uint8_t byte; - - /// bitwise access to register ARR - struct { - BITS ARR : 8; // bits 0-7 - }; // ARR bitfield - - /// register _TIM4_ARR reset value - #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) - - } ARR; - -} TIM4_t; - -/// access to TIM4 SFR registers -#define sfr_TIM4 (*((TIM4_t*) 0x5340)) - - -//------------------------ -// Module UART1 -//------------------------ - -/** struct containing UART1 module registers */ -typedef struct { - - /** UART1 status register (SR at 0x5230) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS PE : 1; // bit 0 - BITS FE : 1; // bit 1 - BITS NF : 1; // bit 2 - BITS OR_LHE : 1; // bit 3 - BITS IDLE : 1; // bit 4 - BITS RXNE : 1; // bit 5 - BITS TC : 1; // bit 6 - BITS TXE : 1; // bit 7 - }; // SR bitfield - - /// register _UART1_SR reset value - #define sfr_UART1_SR_RESET_VALUE ((uint8_t) 0xC0) - - } SR; - - - /** UART1 data register (DR at 0x5231) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _UART1_DR reset value - #define sfr_UART1_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** UART1 baud rate register 1 (BRR1 at 0x5232) */ - union { - - /// bytewise access to BRR1 - uint8_t byte; - - /// bitwise access to register BRR1 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR1 bitfield - - /// register _UART1_BRR1 reset value - #define sfr_UART1_BRR1_RESET_VALUE ((uint8_t) 0x00) - - } BRR1; - - - /** UART1 baud rate register 2 (BRR2 at 0x5233) */ - union { - - /// bytewise access to BRR2 - uint8_t byte; - - /// bitwise access to register BRR2 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR2 bitfield - - /// register _UART1_BRR2 reset value - #define sfr_UART1_BRR2_RESET_VALUE ((uint8_t) 0x00) - - } BRR2; - - - /** UART1 control register 1 (CR1 at 0x5234) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PIEN : 1; // bit 0 - BITS PS : 1; // bit 1 - BITS PCEN : 1; // bit 2 - BITS WAKE : 1; // bit 3 - BITS M : 1; // bit 4 - BITS UART0 : 1; // bit 5 - BITS T8 : 1; // bit 6 - BITS R8 : 1; // bit 7 - }; // CR1 bitfield - - /// register _UART1_CR1 reset value - #define sfr_UART1_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** UART1 control register 2 (CR2 at 0x5235) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS SBK : 1; // bit 0 - BITS RWU : 1; // bit 1 - BITS REN : 1; // bit 2 - BITS TEN : 1; // bit 3 - BITS ILIEN : 1; // bit 4 - BITS RIEN : 1; // bit 5 - BITS TCIEN : 1; // bit 6 - BITS TIEN : 1; // bit 7 - }; // CR2 bitfield - - /// register _UART1_CR2 reset value - #define sfr_UART1_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** UART1 control register 3 (CR3 at 0x5236) */ - union { - - /// bytewise access to CR3 - uint8_t byte; - - /// bitwise access to register CR3 - struct { - BITS LBCL : 1; // bit 0 - BITS CPHA : 1; // bit 1 - BITS CPOL : 1; // bit 2 - BITS CKEN : 1; // bit 3 - BITS STOP : 2; // bits 4-5 - BITS : 1; // 1 bit - BITS LINEN : 1; // bit 7 - }; // CR3 bitfield - - /// register _UART1_CR3 reset value - #define sfr_UART1_CR3_RESET_VALUE ((uint8_t) 0x00) - - } CR3; - - - /** UART1 control register 4 (CR4 at 0x5237) */ - union { - - /// bytewise access to CR4 - uint8_t byte; - - /// bitwise access to register CR4 - struct { - BITS ADD : 4; // bits 0-3 - BITS LBDF : 1; // bit 4 - BITS LBDL : 1; // bit 5 - BITS LBDIEN : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR4 bitfield - - /// register _UART1_CR4 reset value - #define sfr_UART1_CR4_RESET_VALUE ((uint8_t) 0x00) - - } CR4; - - - /** UART1 control register 5 (CR5 at 0x5238) */ - union { - - /// bytewise access to CR5 - uint8_t byte; - - /// bitwise access to register CR5 - struct { - BITS : 1; // 1 bit - BITS IREN : 1; // bit 1 - BITS IRLP : 1; // bit 2 - BITS HDSEL : 1; // bit 3 - BITS NACK : 1; // bit 4 - BITS SCEN : 1; // bit 5 - BITS : 2; // 2 bits - }; // CR5 bitfield - - /// register _UART1_CR5 reset value - #define sfr_UART1_CR5_RESET_VALUE ((uint8_t) 0x00) - - } CR5; - - - /** UART1 guard time register (GTR at 0x5239) */ - union { - - /// bytewise access to GTR - uint8_t byte; - - /// bitwise access to register GTR - struct { - BITS GT : 8; // bits 0-7 - }; // GTR bitfield - - /// register _UART1_GTR reset value - #define sfr_UART1_GTR_RESET_VALUE ((uint8_t) 0x00) - - } GTR; - - - /** UART1 prescaler register (PSCR at 0x523a) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCR bitfield - - /// register _UART1_PSCR reset value - #define sfr_UART1_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - -} UART1_t; - -/// access to UART1 SFR registers -#define sfr_UART1 (*((UART1_t*) 0x5230)) - - -//------------------------ -// Module UART3 -//------------------------ - -/** struct containing UART3 module registers */ -typedef struct { - - /** UART3 status register (SR at 0x5240) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS PE : 1; // bit 0 - BITS FE : 1; // bit 1 - BITS NF : 1; // bit 2 - BITS OR : 1; // bit 3 - BITS IDLE : 1; // bit 4 - BITS RXNE : 1; // bit 5 - BITS TC : 1; // bit 6 - BITS TXE : 1; // bit 7 - }; // SR bitfield - - /// register _UART3_SR reset value - #define sfr_UART3_SR_RESET_VALUE ((uint8_t) 0xC0) - - } SR; - - - /** UART3 data register (DR at 0x5241) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _UART3_DR reset value - #define sfr_UART3_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** UART3 baud rate register 1 (BRR1 at 0x5242) */ - union { - - /// bytewise access to BRR1 - uint8_t byte; - - /// bitwise access to register BRR1 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR1 bitfield - - /// register _UART3_BRR1 reset value - #define sfr_UART3_BRR1_RESET_VALUE ((uint8_t) 0x00) - - } BRR1; - - - /** UART3 baud rate register 2 (BRR2 at 0x5243) */ - union { - - /// bytewise access to BRR2 - uint8_t byte; - - /// bitwise access to register BRR2 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR2 bitfield - - /// register _UART3_BRR2 reset value - #define sfr_UART3_BRR2_RESET_VALUE ((uint8_t) 0x00) - - } BRR2; - - - /** UART3 control register 1 (CR1 at 0x5244) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PIEN : 1; // bit 0 - BITS PS : 1; // bit 1 - BITS PCEN : 1; // bit 2 - BITS WAKE : 1; // bit 3 - BITS M : 1; // bit 4 - BITS UARTD : 1; // bit 5 - BITS T8 : 1; // bit 6 - BITS R8 : 1; // bit 7 - }; // CR1 bitfield - - /// register _UART3_CR1 reset value - #define sfr_UART3_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** UART3 control register 2 (CR2 at 0x5245) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS SBK : 1; // bit 0 - BITS RWU : 1; // bit 1 - BITS REN : 1; // bit 2 - BITS TEN : 1; // bit 3 - BITS ILIEN : 1; // bit 4 - BITS RIEN : 1; // bit 5 - BITS TCIEN : 1; // bit 6 - BITS TIEN : 1; // bit 7 - }; // CR2 bitfield - - /// register _UART3_CR2 reset value - #define sfr_UART3_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** UART3 control register 3 (CR3 at 0x5246) */ - union { - - /// bytewise access to CR3 - uint8_t byte; - - /// bitwise access to register CR3 - struct { - BITS : 4; // 4 bits - BITS STOP : 2; // bits 4-5 - BITS LINEN : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR3 bitfield - - /// register _UART3_CR3 reset value - #define sfr_UART3_CR3_RESET_VALUE ((uint8_t) 0x00) - - } CR3; - - - /** UART3 control register 4 (CR4 at 0x5247) */ - union { - - /// bytewise access to CR4 - uint8_t byte; - - /// bitwise access to register CR4 - struct { - BITS ADD : 4; // bits 0-3 - BITS LBDF : 1; // bit 4 - BITS LBDL : 1; // bit 5 - BITS LBDIEN : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR4 bitfield - - /// register _UART3_CR4 reset value - #define sfr_UART3_CR4_RESET_VALUE ((uint8_t) 0x00) - - } CR4; - - - /// Reserved register (1B) - uint8_t Reserved_1[1]; - - - /** UART3 control register 6 (CR6 at 0x5249) */ - union { - - /// bytewise access to CR6 - uint8_t byte; - - /// bitwise access to register CR6 - struct { - BITS LSF : 1; // bit 0 - BITS LHDF : 1; // bit 1 - BITS LHDIEN : 1; // bit 2 - BITS : 1; // 1 bit - BITS LASE : 1; // bit 4 - BITS LSLV : 1; // bit 5 - BITS : 1; // 1 bit - BITS LDUM : 1; // bit 7 - }; // CR6 bitfield - - /// register _UART3_CR6 reset value - #define sfr_UART3_CR6_RESET_VALUE ((uint8_t) 0x00) - - } CR6; - -} UART3_t; - -/// access to UART3 SFR registers -#define sfr_UART3 (*((UART3_t*) 0x5240)) - - -//------------------------ -// Module WWDG -//------------------------ - -/** struct containing WWDG module registers */ -typedef struct { - - /** WWDG control register (CR at 0x50d1) */ - union { - - /// bytewise access to CR - uint8_t byte; - - /// bitwise access to register CR - struct { - BITS T0 : 1; // bit 0 - BITS T1 : 1; // bit 1 - BITS T2 : 1; // bit 2 - BITS T3 : 1; // bit 3 - BITS T4 : 1; // bit 4 - BITS T5 : 1; // bit 5 - BITS T6 : 1; // bit 6 - BITS WDGA : 1; // bit 7 - }; // CR bitfield - - /// register _WWDG_CR reset value - #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) - - } CR; - - - /** WWDR window register (WR at 0x50d2) */ - union { - - /// bytewise access to WR - uint8_t byte; - - /// bitwise access to register WR - struct { - BITS W0 : 1; // bit 0 - BITS W1 : 1; // bit 1 - BITS W2 : 1; // bit 2 - BITS W3 : 1; // bit 3 - BITS W4 : 1; // bit 4 - BITS W5 : 1; // bit 5 - BITS W6 : 1; // bit 6 - BITS : 1; // 1 bit - }; // WR bitfield - - /// register _WWDG_WR reset value - #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) - - } WR; - -} WWDG_t; - -/// access to WWDG SFR registers -#define sfr_WWDG (*((WWDG_t*) 0x50d1)) - - -// undefine local macros -#undef BITS - -// required for C++ -#ifdef __cplusplus - } // extern "C" -#endif - -/*------------------------------------------------------------------------- - END OF MODULE DEFINITION FOR MULTIPLE INLUSION --------------------------------------------------------------------------*/ -#endif // STM8S207K8_H diff --git a/examples/native-blink/src/STM8S208RB.h b/examples/native-blink/src/STM8S208RB.h deleted file mode 100644 index 31523aa..0000000 --- a/examples/native-blink/src/STM8S208RB.h +++ /dev/null @@ -1,6376 +0,0 @@ -/*------------------------------------------------------------------------- - - STM8S208RB.h - Device Declarations - - STM8S/STM8AF, high density with ROM bootloader - - Copyright (C) 2020, Georg Icking-Konert - - Mainstream Performance line 8-bit MCU with 128 Kbyes Flash, 24 MHz CPU, integrated EEPROM - - datasheet: https://www.st.com/resource/en/datasheet/stm8s208rb.pdf - reference: RM0016 https://www.st.com/content/ccc/resource/technical/document/reference_manual/9a/1b/85/07/ca/eb/4f/dd/CD00190271.pdf/files/CD00190271.pdf/jcr:content/translations/en.CD00190271.pdf - - MIT License - - Copyright (c) 2020 Georg Icking-Konert - - Permission is hereby granted, free of charge, to any person obtaining a copy - of this software and associated documentation files (the "Software"), to deal - in the Software without restriction, including without limitation the rights - to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - copies of the Software, and to permit persons to whom the Software is - furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in all - copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - SOFTWARE. - --------------------------------------------------------------------------*/ - -/*------------------------------------------------------------------------- - MODULE DEFINITION FOR MULTIPLE INCLUSION --------------------------------------------------------------------------*/ -#ifndef STM8S208RB_H -#define STM8S208RB_H - -// DEVICE NAME -#define DEVICE_STM8S208RB - -// DEVICE FAMILY -#define FAMILY_STM8S - -// required for C++ -#ifdef __cplusplus - extern "C" { -#endif - - -/*------------------------------------------------------------------------- - INCLUDE FILES --------------------------------------------------------------------------*/ -#include - - -/*------------------------------------------------------------------------- - COMPILER SPECIFIC SETTINGS --------------------------------------------------------------------------*/ - -// Cosmic compiler -#if defined(__CSMC__) - - // macros to unify ISR declaration and implementation - #define ISR_HANDLER(func,irq) @far @interrupt void func(void) ///< handler for interrupt service routine - #define ISR_HANDLER_TRAP(func) void @far @interrupt func(void) ///< handler for trap service routine - - // definition of inline functions - #define INLINE @inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() _asm("nop") ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() _asm("sim") ///< disable interrupt handling - #define ENABLE_INTERRUPTS() _asm("rim") ///< enable interrupt handling - #define TRIGGER_TRAP _asm("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() _asm("wfi") ///< stop code execution and wait for interrupt - #define ENTER_HALT() _asm("halt") ///< put controller to HALT mode - #define SW_RESET() _asm("dc.b $75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned int ///< data type in bit structs (follow C90 standard) - - -// IAR Compiler -#elif defined(__ICCSTM8__) - - // include intrinsic functions - #include - - // macros to unify ISR declaration and implementation - #define STRINGVECTOR(x) #x - #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) - #define ISR_HANDLER( a, b ) \ - _Pragma( VECTOR_ID( (b)+2 ) ) \ - __interrupt void (a)( void ) - #define ISR_HANDLER_TRAP(a) \ - _Pragma( VECTOR_ID( 1 ) ) \ - __interrupt void (a) (void) - - // definition of inline functions - #define INLINE static inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() __no_operation() ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() __disable_interrupt() ///< disable interrupt handling - #define ENABLE_INTERRUPTS() __enable_interrupt() ///< enable interrupt handling - #define TRIGGER_TRAP __trap() ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() __wait_for_interrupt() ///< stop code execution and wait for interrupt - #define ENTER_HALT() __halt() ///< put controller to HALT mode - #define SW_RESET() __asm("dc8 0x75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned char ///< data type in bit structs (deviating from C90 standard) - - -// SDCC compiler -#elif defined(__SDCC) - - // store SDCC version in preprocessor friendly way - #define SDCC_VERSION (__SDCC_VERSION_MAJOR * 10000 \ - + __SDCC_VERSION_MINOR * 100 \ - + __SDCC_VERSION_PATCH) - - // unify ISR declaration and implementation - #define ISR_HANDLER(func,irq) void func(void) __interrupt(irq) ///< handler for interrupt service routine - #if SDCC_VERSION >= 30403 // traps require >=v3.4.3 - #define ISR_HANDLER_TRAP(func) void func() __trap ///< handler for trap service routine - #else - #error traps require SDCC >=3.4.3. Please update! - #endif - - // definition of inline functions - #define INLINE static inline ///< keyword for inline functions - - // common assembler instructions - #define NOP() __asm__("nop") ///< perform a nop() operation (=minimum delay) - #define DISABLE_INTERRUPTS() __asm__("sim") ///< disable interrupt handling - #define ENABLE_INTERRUPTS() __asm__("rim") ///< enable interrupt handling - #define TRIGGER_TRAP __asm__("trap") ///< trigger a trap (=soft interrupt) e.g. for EMC robustness (see AN1015) - #define WAIT_FOR_INTERRUPT() __asm__("wfi") ///< stop code execution and wait for interrupt - #define ENTER_HALT() __asm__("halt") ///< put controller to HALT mode - #define SW_RESET() __asm__(".db 0x75") ///< reset via illegal opcode (works for all devices) - - // data type in bit fields - #define BITS unsigned int ///< data type in bit structs (follow C90 standard) - -// unsupported compiler -> stop -#else - #error: compiler not supported -#endif - - -/*------------------------------------------------------------------------- - FOR CONVENIENT PIN ACCESS --------------------------------------------------------------------------*/ - -#define PIN0 0x01 -#define PIN1 0x02 -#define PIN2 0x04 -#define PIN3 0x08 -#define PIN4 0x10 -#define PIN5 0x20 -#define PIN6 0x40 -#define PIN7 0x80 - - -/*------------------------------------------------------------------------- - DEVICE MEMORY (size in bytes) --------------------------------------------------------------------------*/ - -// RAM -#define RAM_ADDR_START 0x000000 -#define RAM_ADDR_END 0x0017FF -#define RAM_SIZE 6144 - - -// FLASH -#define FLASH_ADDR_START 0x008000 -#define FLASH_ADDR_END 0x027FFF -#define FLASH_SIZE 131072 - - -// SFR1 -#define SFR1_ADDR_START 0x005000 -#define SFR1_ADDR_END 0x0057FF -#define SFR1_SIZE 2048 - - -// SFR2 -#define SFR2_ADDR_START 0x007F00 -#define SFR2_ADDR_END 0x007FFF -#define SFR2_SIZE 256 - - -// BOOTROM -#define BOOTROM_ADDR_START 0x006000 -#define BOOTROM_ADDR_END 0x0067FF -#define BOOTROM_SIZE 2048 - - -// EEPROM -#define EEPROM_ADDR_START 0x004000 -#define EEPROM_ADDR_END 0x0047FF -#define EEPROM_SIZE 2048 - - -// OPTION -#define OPTION_ADDR_START 0x004800 -#define OPTION_ADDR_END 0x00487F -#define OPTION_SIZE 128 - - -// MEMORY WIDTH (>32kB flash exceeds 16bit, as flash starts at 0x8000) -#define FLASH_ADDR_WIDTH 32 ///< width of address space -#define FLASH_POINTER_T uint32_t ///< address variable type - - -/*------------------------------------------------------------------------- - UNIQUE IDENTIFIER (size in bytes) --------------------------------------------------------------------------*/ - -#define UID_ADDR_START 0x48CD ///< start address of unique identifier -#define UID_SIZE 12 ///< size of unique identifier [B] -#define UID(N) (*((uint8_t*) (UID_ADDR_START+N))) ///< read unique identifier byte N - - -/*------------------------------------------------------------------------- - MISC OPTIONS --------------------------------------------------------------------------*/ - -/// LSI frequency measurement channel -#define LSI_MEASURE_TIM3_IC1 - - -/*------------------------------------------------------------------------- - ISR Vector Table (SDCC, IAR) - Notes: - - IAR has an IRQ offset of +2 compared to datasheet and below numbers - - Cosmic uses a separate, device specific file 'stm8_interrupt_vector.c' - - different interrupt sources may share the same IRQ --------------------------------------------------------------------------*/ - -// interrupt IRQ -#define _TLI_VECTOR_ 0 -#define _AWU_VECTOR_ 1 ///< AWU interrupt vector: enable: AWU_CSR1.AWUEN, pending: AWU_CSR1.AWUF, priority: ITC_SPR1.VECT1SPR -#define _CLK_CSS_VECTOR_ 2 ///< CLK_CSS interrupt vector: enable: CLK_CSSR.CSSDIE, pending: CLK_CSSR.CSSD, priority: ITC_SPR1.VECT2SPR -#define _CLK_SWITCH_VECTOR_ 2 ///< CLK_SWITCH interrupt vector: enable: CLK_SWCR.SWIEN, pending: CLK_SWCR.SWIF, priority: ITC_SPR1.VECT2SPR -#define _EXTI0_VECTOR_ 3 ///< EXTI0 interrupt vector: enable: PA_CR2.C20, pending: PA_IDR.IDR0, priority: ITC_SPR1.VECT3SPR -#define _EXTI1_VECTOR_ 4 ///< EXTI1 interrupt vector: enable: PB_CR2.C20, pending: PB_IDR.IDR0, priority: ITC_SPR2.VECT4SPR -#define _EXTI2_VECTOR_ 5 ///< EXTI2 interrupt vector: enable: PC_CR2.C20, pending: PC_IDR.IDR0, priority: ITC_SPR2.VECT5SPR -#define _EXTI3_VECTOR_ 6 ///< EXTI3 interrupt vector: enable: PD_CR2.C20, pending: PD_IDR.IDR0, priority: ITC_SPR2.VECT6SPR -#define _EXTI4_VECTOR_ 7 ///< EXTI4 interrupt vector: enable: PE_CR2.C20, pending: PE_IDR.IDR0, priority: ITC_SPR2.VECT7SPR -#define _CAN_FMP_VECTOR_ 8 ///< CAN_FMP interrupt vector: enable: CAN_IER.FMPIE, pending: CAN_RFR.FMP, priority: ITC_SPR3.VECT8SPR -#define _CAN_FOVR_VECTOR_ 8 ///< CAN_FOVR interrupt vector: enable: CAN_IER.FOVIE, pending: CAN_RFR.FOVR, priority: ITC_SPR3.VECT8SPR -#define _CAN_FULL_VECTOR_ 8 ///< CAN_FULL interrupt vector: enable: CAN_IER.FFIE, pending: CAN_RFR.FULL, priority: ITC_SPR3.VECT8SPR -#define _CAN_BOFF_VECTOR_ 9 ///< CAN_BOFF interrupt vector: enable: CAN_EIER.BOFIE, pending: CAN_ESR.BOFF, priority: ITC_SPR3.VECT9SPR -#define _CAN_EPVF_VECTOR_ 9 ///< CAN_EPVF interrupt vector: enable: CAN_EIER.EPVIE, pending: CAN_ESR.EPVF, priority: ITC_SPR3.VECT9SPR -#define _CAN_EWGF_VECTOR_ 9 ///< CAN_EWGF interrupt vector: enable: CAN_EIER.EWGIE, pending: CAN_ESR.EWGF, priority: ITC_SPR3.VECT9SPR -#define _CAN_LEC0_VECTOR_ 9 ///< CAN_LEC0 interrupt vector: enable: CAN_EIER.LECIE, pending: CAN_ESR.LEC0, priority: ITC_SPR3.VECT9SPR -#define _CAN_LEC1_VECTOR_ 9 ///< CAN_LEC1 interrupt vector: enable: CAN_EIER.LECIE, pending: CAN_ESR.LEC1, priority: ITC_SPR3.VECT9SPR -#define _CAN_LEC2_VECTOR_ 9 ///< CAN_LEC2 interrupt vector: enable: CAN_EIER.LECIE, pending: CAN_ESR.LEC2, priority: ITC_SPR3.VECT9SPR -#define _CAN_RQCP0_VECTOR_ 9 ///< CAN_RQCP0 interrupt vector: enable: CAN_IER.TMEIE, pending: CAN_TSR.RQCP0, priority: ITC_SPR3.VECT9SPR -#define _CAN_RQCP1_VECTOR_ 9 ///< CAN_RQCP1 interrupt vector: enable: CAN_IER.TMEIE, pending: CAN_TSR.RQCP1, priority: ITC_SPR3.VECT9SPR -#define _CAN_RQCP2_VECTOR_ 9 ///< CAN_RQCP2 interrupt vector: enable: CAN_IER.TMEIE, pending: CAN_TSR.RQCP2, priority: ITC_SPR3.VECT9SPR -#define _CAN_WKUI_VECTOR_ 9 ///< CAN_WKUI interrupt vector: enable: CAN_IER.WKUIE, pending: CAN_MSR.WKUI, priority: ITC_SPR3.VECT9SPR -#define _SPI_CRCERR_VECTOR_ 10 ///< SPI_CRCERR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.CRCERR, priority: ITC_SPR3.VECT10SPR -#define _SPI_MODF_VECTOR_ 10 ///< SPI_MODF interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.MODF, priority: ITC_SPR3.VECT10SPR -#define _SPI_OVR_VECTOR_ 10 ///< SPI_OVR interrupt vector: enable: SPI_ICR.ERRIE, pending: SPI_SR.OVR, priority: ITC_SPR3.VECT10SPR -#define _SPI_RXNE_VECTOR_ 10 ///< SPI_RXNE interrupt vector: enable: SPI_ICR.RXIE, pending: SPI_SR.RXNE, priority: ITC_SPR3.VECT10SPR -#define _SPI_TXE_VECTOR_ 10 ///< SPI_TXE interrupt vector: enable: SPI_ICR.TXIE, pending: SPI_SR.TXE, priority: ITC_SPR3.VECT10SPR -#define _SPI_WKUP_VECTOR_ 10 ///< SPI_WKUP interrupt vector: enable: SPI_ICR.WKIE, pending: SPI_SR.WKUP, priority: ITC_SPR3.VECT10SPR -#define _TIM1_CAPCOM_BIF_VECTOR_ 11 ///< TIM1_CAPCOM_BIF interrupt vector: enable: TIM1_IER.BIE, pending: TIM1_SR1.BIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_CAPCOM_TIF_VECTOR_ 11 ///< TIM1_CAPCOM_TIF interrupt vector: enable: TIM1_IER.TIE, pending: TIM1_SR1.TIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_OVR_UIF_VECTOR_ 11 ///< TIM1_OVR_UIF interrupt vector: enable: TIM1_IER.UIE, pending: TIM1_SR1.UIF, priority: ITC_SPR3.VECT11SPR -#define _TIM1_CAPCOM_CC1IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC1IF interrupt vector: enable: TIM1_IER.CC1IE, pending: TIM1_SR1.CC1IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC2IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC2IF interrupt vector: enable: TIM1_IER.CC2IE, pending: TIM1_SR1.CC2IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC3IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC3IF interrupt vector: enable: TIM1_IER.CC3IE, pending: TIM1_SR1.CC3IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_CC4IF_VECTOR_ 12 ///< TIM1_CAPCOM_CC4IF interrupt vector: enable: TIM1_IER.CC4IE, pending: TIM1_SR1.CC4IF, priority: ITC_SPR4.VECT12SPR -#define _TIM1_CAPCOM_COMIF_VECTOR_ 12 ///< TIM1_CAPCOM_COMIF interrupt vector: enable: TIM1_IER.COMIE, pending: TIM1_SR1.COMIF, priority: ITC_SPR4.VECT12SPR -#define _TIM2_OVR_UIF_VECTOR_ 13 ///< TIM2_OVR_UIF interrupt vector: enable: TIM2_IER.UIE, pending: TIM2_SR1.UIF, priority: ITC_SPR4.VECT13SPR -#define _TIM2_CAPCOM_CC1IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC1IF interrupt vector: enable: TIM2_IER.CC1IE, pending: TIM2_SR1.CC1IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_CC2IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC2IF interrupt vector: enable: TIM2_IER.CC2IE, pending: TIM2_SR1.CC2IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_CC3IF_VECTOR_ 14 ///< TIM2_CAPCOM_CC3IF interrupt vector: enable: TIM2_IER.CC3IE, pending: TIM2_SR1.CC3IF, priority: ITC_SPR4.VECT14SPR -#define _TIM2_CAPCOM_TIF_VECTOR_ 14 ///< TIM2_CAPCOM_TIF interrupt vector: enable: TIM2_IER.TIE, pending: TIM2_SR1.TIF, priority: ITC_SPR4.VECT14SPR -#define _TIM3_OVR_UIF_VECTOR_ 15 ///< TIM3_OVR_UIF interrupt vector: enable: TIM3_IER.UIE, pending: TIM3_SR1.UIF, priority: ITC_SPR4.VECT15SPR -#define _TIM3_CAPCOM_CC1IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC1IF interrupt vector: enable: TIM3_IER.CC1IE, pending: TIM3_SR1.CC1IF, priority: ITC_SPR5.VECT16SPR -#define _TIM3_CAPCOM_CC2IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC2IF interrupt vector: enable: TIM3_IER.CC2IE, pending: TIM3_SR1.CC2IF, priority: ITC_SPR5.VECT16SPR -#define _TIM3_CAPCOM_CC3IF_VECTOR_ 16 ///< TIM3_CAPCOM_CC3IF interrupt vector: enable: TIM3_IER.CC3IE, pending: TIM3_SR1.CC3IF, priority: ITC_SPR5.VECT16SPR -#define _TIM3_CAPCOM_TIF_VECTOR_ 16 ///< TIM3_CAPCOM_TIF interrupt vector: enable: TIM3_IER.TIE, pending: TIM3_SR1.TIF, priority: ITC_SPR5.VECT16SPR -#define _UART1_T_TC_VECTOR_ 17 ///< UART1_T_TC interrupt vector: enable: UART1_CR2.TCIEN, pending: UART1_SR.TC, priority: ITC_SPR5.VECT17SPR -#define _UART1_T_TXE_VECTOR_ 17 ///< UART1_T_TXE interrupt vector: enable: UART1_CR2.TIEN, pending: UART1_SR.TXE, priority: ITC_SPR5.VECT17SPR -#define _UART1_R_IDLE_VECTOR_ 18 ///< UART1_R_IDLE interrupt vector: enable: UART1_CR2.ILIEN, pending: UART1_SR.IDLE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_LBDF_VECTOR_ 18 ///< UART1_R_LBDF interrupt vector: enable: UART1_CR4.LBDIEN, pending: UART1_CR4.LBDF, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_OR_VECTOR_ 18 ///< UART1_R_OR interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.OR_LHE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_PE_VECTOR_ 18 ///< UART1_R_PE interrupt vector: enable: UART1_CR1.PIEN, pending: UART1_SR.PE, priority: ITC_SPR5.VECT18SPR -#define _UART1_R_RXNE_VECTOR_ 18 ///< UART1_R_RXNE interrupt vector: enable: UART1_CR2.RIEN, pending: UART1_SR.RXNE, priority: ITC_SPR5.VECT18SPR -#define _I2C_ADD10_VECTOR_ 19 ///< I2C_ADD10 interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADD10, priority: ITC_SPR5.VECT19SPR -#define _I2C_ADDR_VECTOR_ 19 ///< I2C_ADDR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.ADDR, priority: ITC_SPR5.VECT19SPR -#define _I2C_AF_VECTOR_ 19 ///< I2C_AF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.AF, priority: ITC_SPR5.VECT19SPR -#define _I2C_ARLO_VECTOR_ 19 ///< I2C_ARLO interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.ARLO, priority: ITC_SPR5.VECT19SPR -#define _I2C_BERR_VECTOR_ 19 ///< I2C_BERR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.BERR, priority: ITC_SPR5.VECT19SPR -#define _I2C_BTF_VECTOR_ 19 ///< I2C_BTF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.BTF, priority: ITC_SPR5.VECT19SPR -#define _I2C_OVR_VECTOR_ 19 ///< I2C_OVR interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.OVR, priority: ITC_SPR5.VECT19SPR -#define _I2C_RXNE_VECTOR_ 19 ///< I2C_RXNE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.RXNE, priority: ITC_SPR5.VECT19SPR -#define _I2C_SB_VECTOR_ 19 ///< I2C_SB interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.SB, priority: ITC_SPR5.VECT19SPR -#define _I2C_STOPF_VECTOR_ 19 ///< I2C_STOPF interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR1.STOPF, priority: ITC_SPR5.VECT19SPR -#define _I2C_TXE_VECTOR_ 19 ///< I2C_TXE interrupt vector: enable: I2C_ITR.ITBUFEN, pending: I2C_SR1.TXE, priority: ITC_SPR5.VECT19SPR -#define _I2C_WUFH_VECTOR_ 19 ///< I2C_WUFH interrupt vector: enable: I2C_ITR.ITEVTEN, pending: I2C_SR2.WUFH, priority: ITC_SPR5.VECT19SPR -#define _UART3_T_TC_VECTOR_ 20 ///< UART3_T_TC interrupt vector: enable: UART3_CR2.TCIEN, pending: UART3_SR.TC, priority: ITC_SPR6.VECT20SPR -#define _UART3_T_TXE_VECTOR_ 20 ///< UART3_T_TXE interrupt vector: enable: UART3_CR2.TIEN, pending: UART3_SR.TXE, priority: ITC_SPR6.VECT20SPR -#define _UART3_R_IDLE_VECTOR_ 21 ///< UART3_R_IDLE interrupt vector: enable: UART3_CR2.ILIEN, pending: UART3_SR.IDLE, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_LBDF_VECTOR_ 21 ///< UART3_R_LBDF interrupt vector: enable: UART3_CR4.LBDIEN, pending: UART3_CR4.LBDF, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_LHDF_VECTOR_ 21 ///< UART3_R_LHDF interrupt vector: enable: UART3_CR6.LHDIEN, pending: UART3_CR6.LHDF, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_OR_VECTOR_ 21 ///< UART3_R_OR interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.OR, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_PE_VECTOR_ 21 ///< UART3_R_PE interrupt vector: enable: UART3_CR1.PIEN, pending: UART3_SR.PE, priority: ITC_SPR6.VECT21SPR -#define _UART3_R_RXNE_VECTOR_ 21 ///< UART3_R_RXNE interrupt vector: enable: UART3_CR2.RIEN, pending: UART3_SR.RXNE, priority: ITC_SPR6.VECT21SPR -#define _ADC2_AWDG_VECTOR_ 22 ///< ADC2_AWDG interrupt vector: enable: ADC_CSR.AWDIE, pending: ADC_CSR.AWD, priority: ITC_SPR6.VECT22SPR -#define _ADC2_EOC_VECTOR_ 22 ///< ADC2_EOC interrupt vector: enable: ADC_CSR.EOCIE, pending: ADC_CSR.EOC, priority: ITC_SPR6.VECT22SPR -#define _TIM4_OVR_UIF_VECTOR_ 23 ///< TIM4_OVR_UIF interrupt vector: enable: TIM4_IER.UIE, pending: TIM4_SR.UIF, priority: ITC_SPR6.VECT23SPR -#define _FLASH_EOP_VECTOR_ 24 ///< FLASH_EOP interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.EOP, priority: ITC_SPR6.VECT24SPR -#define _FLASH_WR_PG_DIS_VECTOR_ 24 ///< FLASH_WR_PG_DIS interrupt vector: enable: FLASH_CR1.IE, pending: FLASH_IAPSR.WR_PG_DIS, priority: ITC_SPR6.VECT24SPR - - -/*------------------------------------------------------------------------- - DEFINITION OF STM8 PERIPHERAL REGISTERS --------------------------------------------------------------------------*/ - -//------------------------ -// Module ADC2 -//------------------------ - -/** struct containing ADC2 module registers */ -typedef struct { - - /** ADC control/status register (CSR at 0x5400) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// bitwise access to register CSR - struct { - BITS CH : 4; // bits 0-3 - BITS AWDIE : 1; // bit 4 - BITS EOCIE : 1; // bit 5 - BITS AWD : 1; // bit 6 - BITS EOC : 1; // bit 7 - }; // CSR bitfield - - /// register _ADC2_CSR reset value - #define sfr_ADC2_CSR_RESET_VALUE ((uint8_t) 0x00) - - } CSR; - - - /** ADC configuration register 1 (CR1 at 0x5401) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS ADON : 1; // bit 0 - BITS CONT : 1; // bit 1 - BITS : 2; // 2 bits - BITS SPSEL : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CR1 bitfield - - /// register _ADC2_CR1 reset value - #define sfr_ADC2_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** ADC configuration register 2 (CR2 at 0x5402) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS : 1; // 1 bit - BITS SCAN : 1; // bit 1 - BITS : 1; // 1 bit - BITS ALIGN : 1; // bit 3 - BITS EXTSEL : 2; // bits 4-5 - BITS EXTTRIG : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR2 bitfield - - /// register _ADC2_CR2 reset value - #define sfr_ADC2_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** ADC configuration register 3 (CR3 at 0x5403) */ - union { - - /// bytewise access to CR3 - uint8_t byte; - - /// bitwise access to register CR3 - struct { - BITS : 6; // 6 bits - BITS OVR : 1; // bit 6 - BITS DBUF : 1; // bit 7 - }; // CR3 bitfield - - /// register _ADC2_CR3 reset value - #define sfr_ADC2_CR3_RESET_VALUE ((uint8_t) 0x00) - - } CR3; - - - /** ADC data register high (DRH at 0x5404) */ - union { - - /// bytewise access to DRH - uint8_t byte; - - /// bitwise access to register DRH - struct { - BITS DH : 8; // bits 0-7 - }; // DRH bitfield - - /// register _ADC2_DRH reset value - #define sfr_ADC2_DRH_RESET_VALUE ((uint8_t) 0x00) - - } DRH; - - - /** ADC data register low (DRL at 0x5405) */ - union { - - /// bytewise access to DRL - uint8_t byte; - - /// bitwise access to register DRL - struct { - BITS DL : 8; // bits 0-7 - }; // DRL bitfield - - /// register _ADC2_DRL reset value - #define sfr_ADC2_DRL_RESET_VALUE ((uint8_t) 0x00) - - } DRL; - - - /** ADC Schmitt trigger disable register high (TDRH at 0x5406) */ - union { - - /// bytewise access to TDRH - uint8_t byte; - - /// bitwise access to register TDRH - struct { - BITS TD : 8; // bits 0-7 - }; // TDRH bitfield - - /// register _ADC2_TDRH reset value - #define sfr_ADC2_TDRH_RESET_VALUE ((uint8_t) 0x00) - - } TDRH; - - - /** ADC Schmitt trigger disable register low (TDRL at 0x5407) */ - union { - - /// bytewise access to TDRL - uint8_t byte; - - /// bitwise access to register TDRL - struct { - BITS TL : 8; // bits 0-7 - }; // TDRL bitfield - - /// register _ADC2_TDRL reset value - #define sfr_ADC2_TDRL_RESET_VALUE ((uint8_t) 0x00) - - } TDRL; - -} ADC2_t; - -/// access to ADC2 SFR registers -#define sfr_ADC2 (*((ADC2_t*) 0x5400)) - - -//------------------------ -// Module AWU -//------------------------ - -/** struct containing AWU module registers */ -typedef struct { - - /** AWU control/status register 1 (CSR1 at 0x50f0) */ - union { - - /// bytewise access to CSR1 - uint8_t byte; - - /// bitwise access to register CSR1 - struct { - BITS MSR : 1; // bit 0 - BITS : 3; // 3 bits - BITS AWUEN : 1; // bit 4 - BITS AWUF : 1; // bit 5 - BITS : 2; // 2 bits - }; // CSR1 bitfield - - /// register _AWU_CSR1 reset value - #define sfr_AWU_CSR1_RESET_VALUE ((uint8_t) 0x00) - - } CSR1; - - - /** AWU asynchronous prescaler buffer register (APR at 0x50f1) */ - union { - - /// bytewise access to APR - uint8_t byte; - - /// bitwise access to register APR - struct { - BITS APR : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // APR bitfield - - /// register _AWU_APR reset value - #define sfr_AWU_APR_RESET_VALUE ((uint8_t) 0x3F) - - } APR; - - - /** AWU timebase selection register (TBR at 0x50f2) */ - union { - - /// bytewise access to TBR - uint8_t byte; - - /// bitwise access to register TBR - struct { - BITS AWUTB : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // TBR bitfield - - /// register _AWU_TBR reset value - #define sfr_AWU_TBR_RESET_VALUE ((uint8_t) 0x00) - - } TBR; - -} AWU_t; - -/// access to AWU SFR registers -#define sfr_AWU (*((AWU_t*) 0x50f0)) - - -//------------------------ -// Module BEEP -//------------------------ - -/** struct containing BEEP module registers */ -typedef struct { - - /** BEEP control/status register (CSR at 0x50f3) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// bitwise access to register CSR - struct { - BITS BEEPDIV : 5; // bits 0-4 - BITS BEEPEN : 1; // bit 5 - BITS BEEPSEL : 2; // bits 6-7 - }; // CSR bitfield - - /// register _BEEP_CSR reset value - #define sfr_BEEP_CSR_RESET_VALUE ((uint8_t) 0x1F) - - } CSR; - -} BEEP_t; - -/// access to BEEP SFR registers -#define sfr_BEEP (*((BEEP_t*) 0x50f3)) - - -//------------------------ -// Module CLK -//------------------------ - -/** struct containing CLK module registers */ -typedef struct { - - /** Internal clock control register (ICKR at 0x50c0) */ - union { - - /// bytewise access to ICKR - uint8_t byte; - - /// bitwise access to register ICKR - struct { - BITS HSIEN : 1; // bit 0 - BITS HSIRDY : 1; // bit 1 - BITS FHW : 1; // bit 2 - BITS LSIEN : 1; // bit 3 - BITS LSIRDY : 1; // bit 4 - BITS REGAH : 1; // bit 5 - BITS : 2; // 2 bits - }; // ICKR bitfield - - /// register _CLK_ICKR reset value - #define sfr_CLK_ICKR_RESET_VALUE ((uint8_t) 0x01) - - } ICKR; - - - /** External clock control register (ECKR at 0x50c1) */ - union { - - /// bytewise access to ECKR - uint8_t byte; - - /// bitwise access to register ECKR - struct { - BITS HSEEN : 1; // bit 0 - BITS HSERDY : 1; // bit 1 - BITS : 6; // 6 bits - }; // ECKR bitfield - - /// register _CLK_ECKR reset value - #define sfr_CLK_ECKR_RESET_VALUE ((uint8_t) 0x00) - - } ECKR; - - - /// Reserved register (1B) - uint8_t Reserved_1[1]; - - - /** Clock master status register (CMSR at 0x50c3) */ - union { - - /// bytewise access to CMSR - uint8_t byte; - - /// bitwise access to register CMSR - struct { - BITS CKM : 8; // bits 0-7 - }; // CMSR bitfield - - /// register _CLK_CMSR reset value - #define sfr_CLK_CMSR_RESET_VALUE ((uint8_t) 0xE1) - - } CMSR; - - - /** Clock master switch register (SWR at 0x50c4) */ - union { - - /// bytewise access to SWR - uint8_t byte; - - /// bitwise access to register SWR - struct { - BITS SWI : 8; // bits 0-7 - }; // SWR bitfield - - /// register _CLK_SWR reset value - #define sfr_CLK_SWR_RESET_VALUE ((uint8_t) 0xE1) - - } SWR; - - - /** Clock switch control register (SWCR at 0x50c5) */ - union { - - /// bytewise access to SWCR - uint8_t byte; - - /// bitwise access to register SWCR - struct { - BITS SWBSY : 1; // bit 0 - BITS SWEN : 1; // bit 1 - BITS SWIEN : 1; // bit 2 - BITS SWIF : 1; // bit 3 - BITS : 4; // 4 bits - }; // SWCR bitfield - - /// register _CLK_SWCR reset value - #define sfr_CLK_SWCR_RESET_VALUE ((uint8_t) 0x00) - - } SWCR; - - - /** Clock divider register (CKDIVR at 0x50c6) */ - union { - - /// bytewise access to CKDIVR - uint8_t byte; - - /// bitwise access to register CKDIVR - struct { - BITS CPUDIV : 3; // bits 0-2 - BITS HSIDIV : 2; // bits 3-4 - BITS : 3; // 3 bits - }; // CKDIVR bitfield - - /// register _CLK_CKDIVR reset value - #define sfr_CLK_CKDIVR_RESET_VALUE ((uint8_t) 0x18) - - } CKDIVR; - - - /** Peripheral clock gating register 1 (PCKENR1 at 0x50c7) */ - union { - - /// bytewise access to PCKENR1 - uint8_t byte; - - /// bitwise access to register PCKENR1 - struct { - BITS PCKEN : 8; // bits 0-7 - }; // PCKENR1 bitfield - - /// register _CLK_PCKENR1 reset value - #define sfr_CLK_PCKENR1_RESET_VALUE ((uint8_t) 0xFF) - - } PCKENR1; - - - /** Clock security system register (CSSR at 0x50c8) */ - union { - - /// bytewise access to CSSR - uint8_t byte; - - /// bitwise access to register CSSR - struct { - BITS CSSEN : 1; // bit 0 - BITS AUX : 1; // bit 1 - BITS CSSDIE : 1; // bit 2 - BITS CSSD : 1; // bit 3 - BITS : 4; // 4 bits - }; // CSSR bitfield - - /// register _CLK_CSSR reset value - #define sfr_CLK_CSSR_RESET_VALUE ((uint8_t) 0x00) - - } CSSR; - - - /** Configurable clock control register (CCOR at 0x50c9) */ - union { - - /// bytewise access to CCOR - uint8_t byte; - - /// bitwise access to register CCOR - struct { - BITS CCOEN : 1; // bit 0 - BITS CCOSEL : 4; // bits 1-4 - BITS CCORDY : 1; // bit 5 - BITS CC0BSY : 1; // bit 6 - BITS : 1; // 1 bit - }; // CCOR bitfield - - /// register _CLK_CCOR reset value - #define sfr_CLK_CCOR_RESET_VALUE ((uint8_t) 0x00) - - } CCOR; - - - /** Peripheral clock gating register 2 (PCKENR2 at 0x50ca) */ - union { - - /// bytewise access to PCKENR2 - uint8_t byte; - - /// bitwise access to register PCKENR2 - struct { - BITS PCKEN2 : 8; // bits 0-7 - }; // PCKENR2 bitfield - - /// register _CLK_PCKENR2 reset value - #define sfr_CLK_PCKENR2_RESET_VALUE ((uint8_t) 0xFF) - - } PCKENR2; - - - /** CAN clock control register (CANCCR at 0x50cb) */ - union { - - /// bytewise access to CANCCR - uint8_t byte; - - /// bitwise access to register CANCCR - struct { - BITS CANDIV : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // CANCCR bitfield - - /// register _CLK_CANCCR reset value - #define sfr_CLK_CANCCR_RESET_VALUE ((uint8_t) 0x00) - - } CANCCR; - - - /** HSI clock calibration trimming register (HSITRIMR at 0x50cc) */ - union { - - /// bytewise access to HSITRIMR - uint8_t byte; - - /// bitwise access to register HSITRIMR - struct { - BITS HSITRIM : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // HSITRIMR bitfield - - /// register _CLK_HSITRIMR reset value - #define sfr_CLK_HSITRIMR_RESET_VALUE ((uint8_t) 0x00) - - } HSITRIMR; - - - /** SWIM clock control register (SWIMCCR at 0x50cd) */ - union { - - /// bytewise access to SWIMCCR - uint8_t byte; - - /// bitwise access to register SWIMCCR - struct { - BITS SWIMCLK : 1; // bit 0 - BITS : 7; // 7 bits - }; // SWIMCCR bitfield - - /// register _CLK_SWIMCCR reset value - #define sfr_CLK_SWIMCCR_RESET_VALUE ((uint8_t) 0x00) - - } SWIMCCR; - -} CLK_t; - -/// access to CLK SFR registers -#define sfr_CLK (*((CLK_t*) 0x50c0)) - - -//------------------------ -// Module CPU -//------------------------ - -/** struct containing CPU module registers */ -typedef struct { - - /** Accumulator (A at 0x7f00) */ - union { - - /// bytewise access to A - uint8_t byte; - - /// skip bitwise access to register A - - /// register _CPU_A reset value - #define sfr_CPU_A_RESET_VALUE ((uint8_t) 0x00) - - } A; - - - /** Program counter extended (PCE at 0x7f01) */ - union { - - /// bytewise access to PCE - uint8_t byte; - - /// skip bitwise access to register PCE - - /// register _CPU_PCE reset value - #define sfr_CPU_PCE_RESET_VALUE ((uint8_t) 0x00) - - } PCE; - - - /** Program counter high (PCH at 0x7f02) */ - union { - - /// bytewise access to PCH - uint8_t byte; - - /// skip bitwise access to register PCH - - /// register _CPU_PCH reset value - #define sfr_CPU_PCH_RESET_VALUE ((uint8_t) 0x00) - - } PCH; - - - /** Program counter low (PCL at 0x7f03) */ - union { - - /// bytewise access to PCL - uint8_t byte; - - /// skip bitwise access to register PCL - - /// register _CPU_PCL reset value - #define sfr_CPU_PCL_RESET_VALUE ((uint8_t) 0x00) - - } PCL; - - - /** X index register high (XH at 0x7f04) */ - union { - - /// bytewise access to XH - uint8_t byte; - - /// skip bitwise access to register XH - - /// register _CPU_XH reset value - #define sfr_CPU_XH_RESET_VALUE ((uint8_t) 0x00) - - } XH; - - - /** X index register low (XL at 0x7f05) */ - union { - - /// bytewise access to XL - uint8_t byte; - - /// skip bitwise access to register XL - - /// register _CPU_XL reset value - #define sfr_CPU_XL_RESET_VALUE ((uint8_t) 0x00) - - } XL; - - - /** Y index register high (YH at 0x7f06) */ - union { - - /// bytewise access to YH - uint8_t byte; - - /// skip bitwise access to register YH - - /// register _CPU_YH reset value - #define sfr_CPU_YH_RESET_VALUE ((uint8_t) 0x00) - - } YH; - - - /** Y index register low (YL at 0x7f07) */ - union { - - /// bytewise access to YL - uint8_t byte; - - /// skip bitwise access to register YL - - /// register _CPU_YL reset value - #define sfr_CPU_YL_RESET_VALUE ((uint8_t) 0x00) - - } YL; - - - /** Stack pointer high (SPH at 0x7f08) */ - union { - - /// bytewise access to SPH - uint8_t byte; - - /// skip bitwise access to register SPH - - /// register _CPU_SPH reset value - #define sfr_CPU_SPH_RESET_VALUE ((uint8_t) 0x17) - - } SPH; - - - /** Stack pointer low (SPL at 0x7f09) */ - union { - - /// bytewise access to SPL - uint8_t byte; - - /// skip bitwise access to register SPL - - /// register _CPU_SPL reset value - #define sfr_CPU_SPL_RESET_VALUE ((uint8_t) 0xFF) - - } SPL; - - - /** Condition code register (CCR at 0x7f0a) */ - union { - - /// bytewise access to CCR - uint8_t byte; - - /// bitwise access to register CCR - struct { - BITS C : 1; // bit 0 - BITS Z : 1; // bit 1 - BITS NF : 1; // bit 2 - BITS I0 : 1; // bit 3 - BITS H : 1; // bit 4 - BITS I1 : 1; // bit 5 - BITS : 1; // 1 bit - BITS V : 1; // bit 7 - }; // CCR bitfield - - /// register _CPU_CCR reset value - #define sfr_CPU_CCR_RESET_VALUE ((uint8_t) 0x28) - - } CCR; - - - /// Reserved register (85B) - uint8_t Reserved_1[85]; - - - /** Global configuration register (CFG_GCR at 0x7f60) */ - union { - - /// bytewise access to CFG_GCR - uint8_t byte; - - /// bitwise access to register CFG_GCR - struct { - BITS SWO : 1; // bit 0 - BITS AL : 1; // bit 1 - BITS : 6; // 6 bits - }; // CFG_GCR bitfield - - /// register _CPU_CFG_GCR reset value - #define sfr_CPU_CFG_GCR_RESET_VALUE ((uint8_t) 0x00) - - } CFG_GCR; - -} CPU_t; - -/// access to CPU SFR registers -#define sfr_CPU (*((CPU_t*) 0x7f00)) - - -//------------------------ -// Module DM -//------------------------ - -/** struct containing DM module registers */ -typedef struct { - - /** DM breakpoint 1 register extended byte (BK1RE at 0x7f90) */ - union { - - /// bytewise access to BK1RE - uint8_t byte; - - /// skip bitwise access to register BK1RE - - /// register _DM_BK1RE reset value - #define sfr_DM_BK1RE_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RE; - - - /** DM breakpoint 1 register high byte (BK1RH at 0x7f91) */ - union { - - /// bytewise access to BK1RH - uint8_t byte; - - /// skip bitwise access to register BK1RH - - /// register _DM_BK1RH reset value - #define sfr_DM_BK1RH_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RH; - - - /** DM breakpoint 1 register low byte (BK1RL at 0x7f92) */ - union { - - /// bytewise access to BK1RL - uint8_t byte; - - /// skip bitwise access to register BK1RL - - /// register _DM_BK1RL reset value - #define sfr_DM_BK1RL_RESET_VALUE ((uint8_t) 0xFF) - - } BK1RL; - - - /** DM breakpoint 2 register extended byte (BK2RE at 0x7f93) */ - union { - - /// bytewise access to BK2RE - uint8_t byte; - - /// skip bitwise access to register BK2RE - - /// register _DM_BK2RE reset value - #define sfr_DM_BK2RE_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RE; - - - /** DM breakpoint 2 register high byte (BK2RH at 0x7f94) */ - union { - - /// bytewise access to BK2RH - uint8_t byte; - - /// skip bitwise access to register BK2RH - - /// register _DM_BK2RH reset value - #define sfr_DM_BK2RH_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RH; - - - /** DM breakpoint 2 register low byte (BK2RL at 0x7f95) */ - union { - - /// bytewise access to BK2RL - uint8_t byte; - - /// skip bitwise access to register BK2RL - - /// register _DM_BK2RL reset value - #define sfr_DM_BK2RL_RESET_VALUE ((uint8_t) 0xFF) - - } BK2RL; - - - /** DM debug module control register 1 (CR1 at 0x7f96) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// skip bitwise access to register CR1 - - /// register _DM_CR1 reset value - #define sfr_DM_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** DM debug module control register 2 (CR2 at 0x7f97) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// skip bitwise access to register CR2 - - /// register _DM_CR2 reset value - #define sfr_DM_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** DM debug module control/status register 1 (CSR1 at 0x7f98) */ - union { - - /// bytewise access to CSR1 - uint8_t byte; - - /// skip bitwise access to register CSR1 - - /// register _DM_CSR1 reset value - #define sfr_DM_CSR1_RESET_VALUE ((uint8_t) 0x10) - - } CSR1; - - - /** DM debug module control/status register 2 (CSR2 at 0x7f99) */ - union { - - /// bytewise access to CSR2 - uint8_t byte; - - /// skip bitwise access to register CSR2 - - /// register _DM_CSR2 reset value - #define sfr_DM_CSR2_RESET_VALUE ((uint8_t) 0x00) - - } CSR2; - - - /** DM enable function register (ENFCTR at 0x7f9a) */ - union { - - /// bytewise access to ENFCTR - uint8_t byte; - - /// skip bitwise access to register ENFCTR - - /// register _DM_ENFCTR reset value - #define sfr_DM_ENFCTR_RESET_VALUE ((uint8_t) 0xFF) - - } ENFCTR; - -} DM_t; - -/// access to DM SFR registers -#define sfr_DM (*((DM_t*) 0x7f90)) - - -//------------------------ -// Module FLASH -//------------------------ - -/** struct containing FLASH module registers */ -typedef struct { - - /** Flash control register 1 (CR1 at 0x505a) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS FIX : 1; // bit 0 - BITS IE : 1; // bit 1 - BITS AHALT : 1; // bit 2 - BITS HALT : 1; // bit 3 - BITS : 4; // 4 bits - }; // CR1 bitfield - - /// register _FLASH_CR1 reset value - #define sfr_FLASH_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** Flash control register 2 (CR2 at 0x505b) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS PRG : 1; // bit 0 - BITS : 3; // 3 bits - BITS FPRG : 1; // bit 4 - BITS ERASE : 1; // bit 5 - BITS WPRG : 1; // bit 6 - BITS OPT : 1; // bit 7 - }; // CR2 bitfield - - /// register _FLASH_CR2 reset value - #define sfr_FLASH_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** Flash complementary control register 2 (NCR2 at 0x505c) */ - union { - - /// bytewise access to NCR2 - uint8_t byte; - - /// bitwise access to register NCR2 - struct { - BITS NPRG : 1; // bit 0 - BITS : 3; // 3 bits - BITS NFPRG : 1; // bit 4 - BITS NERASE : 1; // bit 5 - BITS NWPRG : 1; // bit 6 - BITS NOPT : 1; // bit 7 - }; // NCR2 bitfield - - /// register _FLASH_NCR2 reset value - #define sfr_FLASH_NCR2_RESET_VALUE ((uint8_t) 0xFF) - - } NCR2; - - - /** Flash protection register (FPR at 0x505d) */ - union { - - /// bytewise access to FPR - uint8_t byte; - - /// bitwise access to register FPR - struct { - BITS WPB0 : 1; // bit 0 - BITS WPB1 : 1; // bit 1 - BITS WPB2 : 1; // bit 2 - BITS WPB3 : 1; // bit 3 - BITS WPB4 : 1; // bit 4 - BITS WPB5 : 1; // bit 5 - BITS : 2; // 2 bits - }; // FPR bitfield - - /// register _FLASH_FPR reset value - #define sfr_FLASH_FPR_RESET_VALUE ((uint8_t) 0x00) - - } FPR; - - - /** Flash complementary protection register (NFPR at 0x505e) */ - union { - - /// bytewise access to NFPR - uint8_t byte; - - /// bitwise access to register NFPR - struct { - BITS NWPB0 : 1; // bit 0 - BITS NWPB1 : 1; // bit 1 - BITS NWPB2 : 1; // bit 2 - BITS NWPB3 : 1; // bit 3 - BITS NWPB4 : 1; // bit 4 - BITS NWPB5 : 1; // bit 5 - BITS : 2; // 2 bits - }; // NFPR bitfield - - /// register _FLASH_NFPR reset value - #define sfr_FLASH_NFPR_RESET_VALUE ((uint8_t) 0xFF) - - } NFPR; - - - /** Flash in-application programming status register (IAPSR at 0x505f) */ - union { - - /// bytewise access to IAPSR - uint8_t byte; - - /// bitwise access to register IAPSR - struct { - BITS WR_PG_DIS : 1; // bit 0 - BITS PUL : 1; // bit 1 - BITS EOP : 1; // bit 2 - BITS DUL : 1; // bit 3 - BITS : 2; // 2 bits - BITS HVOFF : 1; // bit 6 - BITS : 1; // 1 bit - }; // IAPSR bitfield - - /// register _FLASH_IAPSR reset value - #define sfr_FLASH_IAPSR_RESET_VALUE ((uint8_t) 0x00) - - } IAPSR; - - - /// Reserved register (2B) - uint8_t Reserved_1[2]; - - - /** Flash Program memory unprotection register (PUKR at 0x5062) */ - union { - - /// bytewise access to PUKR - uint8_t byte; - - /// bitwise access to register PUKR - struct { - BITS MASS_PRG : 8; // bits 0-7 - }; // PUKR bitfield - - /// register _FLASH_PUKR reset value - #define sfr_FLASH_PUKR_RESET_VALUE ((uint8_t) 0x00) - - } PUKR; - - - /// Reserved register (1B) - uint8_t Reserved_2[1]; - - - /** Data EEPROM unprotection register (DUKR at 0x5064) */ - union { - - /// bytewise access to DUKR - uint8_t byte; - - /// bitwise access to register DUKR - struct { - BITS MASS_DATA : 8; // bits 0-7 - }; // DUKR bitfield - - /// register _FLASH_DUKR reset value - #define sfr_FLASH_DUKR_RESET_VALUE ((uint8_t) 0x00) - - } DUKR; - -} FLASH_t; - -/// access to FLASH SFR registers -#define sfr_FLASH (*((FLASH_t*) 0x505a)) - - -//------------------------ -// Module I2C -//------------------------ - -/** struct containing I2C module registers */ -typedef struct { - - /** I2C control register 1 (CR1 at 0x5210) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PE : 1; // bit 0 - BITS : 5; // 5 bits - BITS ENGC : 1; // bit 6 - BITS NOSTRETCH : 1; // bit 7 - }; // CR1 bitfield - - /// register _I2C_CR1 reset value - #define sfr_I2C_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** I2C control register 2 (CR2 at 0x5211) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS START : 1; // bit 0 - BITS STOP : 1; // bit 1 - BITS ACK : 1; // bit 2 - BITS POS : 1; // bit 3 - BITS : 3; // 3 bits - BITS SWRST : 1; // bit 7 - }; // CR2 bitfield - - /// register _I2C_CR2 reset value - #define sfr_I2C_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** I2C frequency register (FREQR at 0x5212) */ - union { - - /// bytewise access to FREQR - uint8_t byte; - - /// bitwise access to register FREQR - struct { - BITS FREQ : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // FREQR bitfield - - /// register _I2C_FREQR reset value - #define sfr_I2C_FREQR_RESET_VALUE ((uint8_t) 0x00) - - } FREQR; - - - /** I2C own address register low (OARL at 0x5213) */ - union { - - /// bytewise access to OARL - uint8_t byte; - - /// bitwise access to register OARL - struct { - BITS ADD0 : 1; // bit 0 - BITS ADD : 7; // bits 1-7 - }; // OARL bitfield - - /// register _I2C_OARL reset value - #define sfr_I2C_OARL_RESET_VALUE ((uint8_t) 0x00) - - } OARL; - - - /** I2C own address register high (OARH at 0x5214) */ - union { - - /// bytewise access to OARH - uint8_t byte; - - /// bitwise access to register OARH - struct { - BITS : 1; // 1 bit - BITS ADD : 2; // bits 1-2 - BITS : 3; // 3 bits - BITS ADDCONF : 1; // bit 6 - BITS ADDMODE : 1; // bit 7 - }; // OARH bitfield - - /// register _I2C_OARH reset value - #define sfr_I2C_OARH_RESET_VALUE ((uint8_t) 0x00) - - } OARH; - - - /// Reserved register (1B) - uint8_t Reserved_1[1]; - - - /** I2C data register (DR at 0x5216) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _I2C_DR reset value - #define sfr_I2C_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** I2C status register 1 (SR1 at 0x5217) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS SB : 1; // bit 0 - BITS ADDR : 1; // bit 1 - BITS BTF : 1; // bit 2 - BITS ADD10 : 1; // bit 3 - BITS STOPF : 1; // bit 4 - BITS : 1; // 1 bit - BITS RXNE : 1; // bit 6 - BITS TXE : 1; // bit 7 - }; // SR1 bitfield - - /// register _I2C_SR1 reset value - #define sfr_I2C_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** I2C status register 2 (SR2 at 0x5218) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS BERR : 1; // bit 0 - BITS ARLO : 1; // bit 1 - BITS AF : 1; // bit 2 - BITS OVR : 1; // bit 3 - BITS : 1; // 1 bit - BITS WUFH : 1; // bit 5 - BITS : 2; // 2 bits - }; // SR2 bitfield - - /// register _I2C_SR2 reset value - #define sfr_I2C_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** I2C status register 3 (SR3 at 0x5219) */ - union { - - /// bytewise access to SR3 - uint8_t byte; - - /// bitwise access to register SR3 - struct { - BITS MSL : 1; // bit 0 - BITS BUSY : 1; // bit 1 - BITS TRA : 1; // bit 2 - BITS : 1; // 1 bit - BITS GENCALL : 1; // bit 4 - BITS : 3; // 3 bits - }; // SR3 bitfield - - /// register _I2C_SR3 reset value - #define sfr_I2C_SR3_RESET_VALUE ((uint8_t) 0x00) - - } SR3; - - - /** I2C interrupt control register (ITR at 0x521a) */ - union { - - /// bytewise access to ITR - uint8_t byte; - - /// bitwise access to register ITR - struct { - BITS ITERREN : 1; // bit 0 - BITS ITEVTEN : 1; // bit 1 - BITS ITBUFEN : 1; // bit 2 - BITS : 5; // 5 bits - }; // ITR bitfield - - /// register _I2C_ITR reset value - #define sfr_I2C_ITR_RESET_VALUE ((uint8_t) 0x00) - - } ITR; - - - /** I2C clock control register low (CCRL at 0x521b) */ - union { - - /// bytewise access to CCRL - uint8_t byte; - - /// bitwise access to register CCRL - struct { - BITS CCR : 8; // bits 0-7 - }; // CCRL bitfield - - /// register _I2C_CCRL reset value - #define sfr_I2C_CCRL_RESET_VALUE ((uint8_t) 0x00) - - } CCRL; - - - /** I2C clock control register high (CCRH at 0x521c) */ - union { - - /// bytewise access to CCRH - uint8_t byte; - - /// bitwise access to register CCRH - struct { - BITS CCR : 4; // bits 0-3 - BITS : 2; // 2 bits - BITS DUTY : 1; // bit 6 - BITS F_S : 1; // bit 7 - }; // CCRH bitfield - - /// register _I2C_CCRH reset value - #define sfr_I2C_CCRH_RESET_VALUE ((uint8_t) 0x00) - - } CCRH; - - - /** I2C TRISE register (TRISER at 0x521d) */ - union { - - /// bytewise access to TRISER - uint8_t byte; - - /// bitwise access to register TRISER - struct { - BITS TRISE : 6; // bits 0-5 - BITS : 2; // 2 bits - }; // TRISER bitfield - - /// register _I2C_TRISER reset value - #define sfr_I2C_TRISER_RESET_VALUE ((uint8_t) 0x02) - - } TRISER; - - - /** I2C packet error checking register (PECR at 0x521e) */ - union { - - /// bytewise access to PECR - uint8_t byte; - - /// skip bitwise access to register PECR - - /// register _I2C_PECR reset value - #define sfr_I2C_PECR_RESET_VALUE ((uint8_t) 0x00) - - } PECR; - -} I2C_t; - -/// access to I2C SFR registers -#define sfr_I2C (*((I2C_t*) 0x5210)) - - -//------------------------ -// Module ITC -//------------------------ - -/** struct containing ITC module registers */ -typedef struct { - - /** External interrupt control register 1 (CR1 at 0x50a0) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PAIS : 2; // bits 0-1 - BITS PBIS : 2; // bits 2-3 - BITS PCIS : 2; // bits 4-5 - BITS PDIS : 2; // bits 6-7 - }; // CR1 bitfield - - /// register _ITC_CR1 reset value - #define sfr_ITC_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** External interrupt control register 2 (CR2 at 0x50a1) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS PEIS : 2; // bits 0-1 - BITS TLIS : 1; // bit 2 - BITS : 5; // 5 bits - }; // CR2 bitfield - - /// register _ITC_CR2 reset value - #define sfr_ITC_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /// Reserved register (11982B) - uint8_t Reserved_1[11982]; - - - /** Interrupt software priority register 1 (SPR1 at 0x7f70) */ - union { - - /// bytewise access to SPR1 - uint8_t byte; - - /// bitwise access to register SPR1 - struct { - BITS VECT0SPR : 2; // bits 0-1 - BITS VECT1SPR : 2; // bits 2-3 - BITS VECT2SPR : 2; // bits 4-5 - BITS VECT3SPR : 2; // bits 6-7 - }; // SPR1 bitfield - - /// register _ITC_SPR1 reset value - #define sfr_ITC_SPR1_RESET_VALUE ((uint8_t) 0xFF) - - } SPR1; - - - /** Interrupt software priority register 2 (SPR2 at 0x7f71) */ - union { - - /// bytewise access to SPR2 - uint8_t byte; - - /// bitwise access to register SPR2 - struct { - BITS VECT4SPR : 2; // bits 0-1 - BITS VECT5SPR : 2; // bits 2-3 - BITS VECT6SPR : 2; // bits 4-5 - BITS VECT7SPR : 2; // bits 6-7 - }; // SPR2 bitfield - - /// register _ITC_SPR2 reset value - #define sfr_ITC_SPR2_RESET_VALUE ((uint8_t) 0xFF) - - } SPR2; - - - /** Interrupt software priority register 3 (SPR3 at 0x7f72) */ - union { - - /// bytewise access to SPR3 - uint8_t byte; - - /// bitwise access to register SPR3 - struct { - BITS VECT8SPR : 2; // bits 0-1 - BITS VECT9SPR : 2; // bits 2-3 - BITS VECT10SPR : 2; // bits 4-5 - BITS VECT11SPR : 2; // bits 6-7 - }; // SPR3 bitfield - - /// register _ITC_SPR3 reset value - #define sfr_ITC_SPR3_RESET_VALUE ((uint8_t) 0xFF) - - } SPR3; - - - /** Interrupt software priority register 4 (SPR4 at 0x7f73) */ - union { - - /// bytewise access to SPR4 - uint8_t byte; - - /// bitwise access to register SPR4 - struct { - BITS VECT12SPR : 2; // bits 0-1 - BITS VECT13SPR : 2; // bits 2-3 - BITS VECT14SPR : 2; // bits 4-5 - BITS VECT15SPR : 2; // bits 6-7 - }; // SPR4 bitfield - - /// register _ITC_SPR4 reset value - #define sfr_ITC_SPR4_RESET_VALUE ((uint8_t) 0xFF) - - } SPR4; - - - /** Interrupt software priority register 5 (SPR5 at 0x7f74) */ - union { - - /// bytewise access to SPR5 - uint8_t byte; - - /// bitwise access to register SPR5 - struct { - BITS VECT16SPR : 2; // bits 0-1 - BITS VECT17SPR : 2; // bits 2-3 - BITS VECT18SPR : 2; // bits 4-5 - BITS VECT19SPR : 2; // bits 6-7 - }; // SPR5 bitfield - - /// register _ITC_SPR5 reset value - #define sfr_ITC_SPR5_RESET_VALUE ((uint8_t) 0xFF) - - } SPR5; - - - /** Interrupt software priority register 6 (SPR6 at 0x7f75) */ - union { - - /// bytewise access to SPR6 - uint8_t byte; - - /// bitwise access to register SPR6 - struct { - BITS VECT20SPR : 2; // bits 0-1 - BITS VECT21SPR : 2; // bits 2-3 - BITS VECT22SPR : 2; // bits 4-5 - BITS VECT23SPR : 2; // bits 6-7 - }; // SPR6 bitfield - - /// register _ITC_SPR6 reset value - #define sfr_ITC_SPR6_RESET_VALUE ((uint8_t) 0xFF) - - } SPR6; - - - /** Interrupt software priority register 7 (SPR7 at 0x7f76) */ - union { - - /// bytewise access to SPR7 - uint8_t byte; - - /// bitwise access to register SPR7 - struct { - BITS VECT24SPR : 2; // bits 0-1 - BITS VECT25SPR : 2; // bits 2-3 - BITS VECT26SPR : 2; // bits 4-5 - BITS VECT27SPR : 2; // bits 6-7 - }; // SPR7 bitfield - - /// register _ITC_SPR7 reset value - #define sfr_ITC_SPR7_RESET_VALUE ((uint8_t) 0xFF) - - } SPR7; - - - /** Interrupt software priority register 8 (SPR8 at 0x7f77) */ - union { - - /// bytewise access to SPR8 - uint8_t byte; - - /// bitwise access to register SPR8 - struct { - BITS VECT28SPR : 2; // bits 0-1 - BITS VECT29SPR : 2; // bits 2-3 - BITS : 4; // 4 bits - }; // SPR8 bitfield - - /// register _ITC_SPR8 reset value - #define sfr_ITC_SPR8_RESET_VALUE ((uint8_t) 0xFF) - - } SPR8; - -} ITC_t; - -/// access to ITC SFR registers -#define sfr_ITC (*((ITC_t*) 0x50a0)) - - -//------------------------ -// Module IWDG -//------------------------ - -/** struct containing IWDG module registers */ -typedef struct { - - /** IWDG key register (KR at 0x50e0) */ - union { - - /// bytewise access to KR - uint8_t byte; - - /// bitwise access to register KR - struct { - BITS KEY : 8; // bits 0-7 - }; // KR bitfield - - /// register _IWDG_KR reset value - #define sfr_IWDG_KR_RESET_VALUE ((uint8_t) 0x00) - - } KR; - - - /** IWDG prescaler register (PR at 0x50e1) */ - union { - - /// bytewise access to PR - uint8_t byte; - - /// bitwise access to register PR - struct { - BITS PR : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // PR bitfield - - /// register _IWDG_PR reset value - #define sfr_IWDG_PR_RESET_VALUE ((uint8_t) 0x00) - - } PR; - - - /** IWDG reload register (RLR at 0x50e2) */ - union { - - /// bytewise access to RLR - uint8_t byte; - - /// bitwise access to register RLR - struct { - BITS RL : 8; // bits 0-7 - }; // RLR bitfield - - /// register _IWDG_RLR reset value - #define sfr_IWDG_RLR_RESET_VALUE ((uint8_t) 0xFF) - - } RLR; - -} IWDG_t; - -/// access to IWDG SFR registers -#define sfr_IWDG (*((IWDG_t*) 0x50e0)) - - -//------------------------ -// Module OPT -//------------------------ - -/** struct containing OPT module registers */ -typedef struct { - - /** Read-out protection (ROP) (OPT0 at 0x4800) */ - union { - - /// bytewise access to OPT0 - uint8_t byte; - - /// skip bitwise access to register OPT0 - - /// register _OPT_OPT0 reset value - #define sfr_OPT_OPT0_RESET_VALUE ((uint8_t) 0x00) - - } OPT0; - - - /** User boot code (UBC) (OPT1 at 0x4801) */ - union { - - /// bytewise access to OPT1 - uint8_t byte; - - /// skip bitwise access to register OPT1 - - /// register _OPT_OPT1 reset value - #define sfr_OPT_OPT1_RESET_VALUE ((uint8_t) 0x00) - - } OPT1; - - - /** User boot code (UBC) (complementary byte) (NOPT1 at 0x4802) */ - union { - - /// bytewise access to NOPT1 - uint8_t byte; - - /// skip bitwise access to register NOPT1 - - /// register _OPT_NOPT1 reset value - #define sfr_OPT_NOPT1_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT1; - - - /** Alternate function remapping (AFR) (OPT2 at 0x4803) */ - union { - - /// bytewise access to OPT2 - uint8_t byte; - - /// skip bitwise access to register OPT2 - - /// register _OPT_OPT2 reset value - #define sfr_OPT_OPT2_RESET_VALUE ((uint8_t) 0x00) - - } OPT2; - - - /** Alternate function remapping (AFR) (complementary byte) (NOPT2 at 0x4804) */ - union { - - /// bytewise access to NOPT2 - uint8_t byte; - - /// skip bitwise access to register NOPT2 - - /// register _OPT_NOPT2 reset value - #define sfr_OPT_NOPT2_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT2; - - - /** Misc. option (OPT3 at 0x4805) */ - union { - - /// bytewise access to OPT3 - uint8_t byte; - - /// skip bitwise access to register OPT3 - - /// register _OPT_OPT3 reset value - #define sfr_OPT_OPT3_RESET_VALUE ((uint8_t) 0x00) - - } OPT3; - - - /** Misc. option (complementary byte) (NOPT3 at 0x4806) */ - union { - - /// bytewise access to NOPT3 - uint8_t byte; - - /// skip bitwise access to register NOPT3 - - /// register _OPT_NOPT3 reset value - #define sfr_OPT_NOPT3_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT3; - - - /** Clock option (OPT4 at 0x4807) */ - union { - - /// bytewise access to OPT4 - uint8_t byte; - - /// skip bitwise access to register OPT4 - - /// register _OPT_OPT4 reset value - #define sfr_OPT_OPT4_RESET_VALUE ((uint8_t) 0x00) - - } OPT4; - - - /** Clock option (complementary byte) (NOPT4 at 0x4808) */ - union { - - /// bytewise access to NOPT4 - uint8_t byte; - - /// skip bitwise access to register NOPT4 - - /// register _OPT_NOPT4 reset value - #define sfr_OPT_NOPT4_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT4; - - - /** HSE clock startup (OPT5 at 0x4809) */ - union { - - /// bytewise access to OPT5 - uint8_t byte; - - /// skip bitwise access to register OPT5 - - /// register _OPT_OPT5 reset value - #define sfr_OPT_OPT5_RESET_VALUE ((uint8_t) 0x00) - - } OPT5; - - - /** HSE clock startup (complementary byte) (NOPT5 at 0x480a) */ - union { - - /// bytewise access to NOPT5 - uint8_t byte; - - /// skip bitwise access to register NOPT5 - - /// register _OPT_NOPT5 reset value - #define sfr_OPT_NOPT5_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT5; - - - /// Reserved register (2B) - uint8_t Reserved_1[2]; - - - /** Flash wait states (OPT7 at 0x480d) */ - union { - - /// bytewise access to OPT7 - uint8_t byte; - - /// skip bitwise access to register OPT7 - - /// register _OPT_OPT7 reset value - #define sfr_OPT_OPT7_RESET_VALUE ((uint8_t) 0x00) - - } OPT7; - - - /** Flash wait states (complementary byte) (NOPT7 at 0x480e) */ - union { - - /// bytewise access to NOPT7 - uint8_t byte; - - /// skip bitwise access to register NOPT7 - - /// register _OPT_NOPT7 reset value - #define sfr_OPT_NOPT7_RESET_VALUE ((uint8_t) 0xFF) - - } NOPT7; - - - /// Reserved register (111B) - uint8_t Reserved_2[111]; - - - /** Bootloader (OPTBL at 0x487e) */ - union { - - /// bytewise access to OPTBL - uint8_t byte; - - /// skip bitwise access to register OPTBL - - /// register _OPT_OPTBL reset value - #define sfr_OPT_OPTBL_RESET_VALUE ((uint8_t) 0x00) - - } OPTBL; - - - /** Bootloader (complementary byte) (NOPTBL at 0x487f) */ - union { - - /// bytewise access to NOPTBL - uint8_t byte; - - /// skip bitwise access to register NOPTBL - - /// register _OPT_NOPTBL reset value - #define sfr_OPT_NOPTBL_RESET_VALUE ((uint8_t) 0xFF) - - } NOPTBL; - -} OPT_t; - -/// access to OPT SFR registers -#define sfr_OPT (*((OPT_t*) 0x4800)) - - -//------------------------ -// Module PORT -//------------------------ - -/** struct containing PORTA module registers */ -typedef struct { - - /** Port A data output latch register (ODR at 0x5000) */ - union { - - /// bytewise access to ODR - uint8_t byte; - - /// bitwise access to register ODR - struct { - BITS ODR0 : 1; // bit 0 - BITS ODR1 : 1; // bit 1 - BITS ODR2 : 1; // bit 2 - BITS ODR3 : 1; // bit 3 - BITS ODR4 : 1; // bit 4 - BITS ODR5 : 1; // bit 5 - BITS ODR6 : 1; // bit 6 - BITS ODR7 : 1; // bit 7 - }; // ODR bitfield - - /// register _PORT_ODR reset value - #define sfr_PORT_ODR_RESET_VALUE ((uint8_t) 0x00) - - } ODR; - - - /** Port A input pin value register (IDR at 0x5001) */ - union { - - /// bytewise access to IDR - uint8_t byte; - - /// bitwise access to register IDR - struct { - BITS IDR0 : 1; // bit 0 - BITS IDR1 : 1; // bit 1 - BITS IDR2 : 1; // bit 2 - BITS IDR3 : 1; // bit 3 - BITS IDR4 : 1; // bit 4 - BITS IDR5 : 1; // bit 5 - BITS IDR6 : 1; // bit 6 - BITS IDR7 : 1; // bit 7 - }; // IDR bitfield - - /// register _PORT_IDR reset value - #define sfr_PORT_IDR_RESET_VALUE ((uint8_t) 0x00) - - } IDR; - - - /** Port A data direction register (DDR at 0x5002) */ - union { - - /// bytewise access to DDR - uint8_t byte; - - /// bitwise access to register DDR - struct { - BITS DDR0 : 1; // bit 0 - BITS DDR1 : 1; // bit 1 - BITS DDR2 : 1; // bit 2 - BITS DDR3 : 1; // bit 3 - BITS DDR4 : 1; // bit 4 - BITS DDR5 : 1; // bit 5 - BITS DDR6 : 1; // bit 6 - BITS DDR7 : 1; // bit 7 - }; // DDR bitfield - - /// register _PORT_DDR reset value - #define sfr_PORT_DDR_RESET_VALUE ((uint8_t) 0x00) - - } DDR; - - - /** Port A control register 1 (CR1 at 0x5003) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS C10 : 1; // bit 0 - BITS C11 : 1; // bit 1 - BITS C12 : 1; // bit 2 - BITS C13 : 1; // bit 3 - BITS C14 : 1; // bit 4 - BITS C15 : 1; // bit 5 - BITS C16 : 1; // bit 6 - BITS C17 : 1; // bit 7 - }; // CR1 bitfield - - /// register _PORT_CR1 reset value - #define sfr_PORT_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** Port A control register 2 (CR2 at 0x5004) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS C20 : 1; // bit 0 - BITS C21 : 1; // bit 1 - BITS C22 : 1; // bit 2 - BITS C23 : 1; // bit 3 - BITS C24 : 1; // bit 4 - BITS C25 : 1; // bit 5 - BITS C26 : 1; // bit 6 - BITS C27 : 1; // bit 7 - }; // CR2 bitfield - - /// register _PORT_CR2 reset value - #define sfr_PORT_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - -} PORT_t; - -/// access to PORTA SFR registers -#define sfr_PORTA (*((PORT_t*) 0x5000)) - - -/// access to PORTB SFR registers -#define sfr_PORTB (*((PORT_t*) 0x5005)) - - -/// access to PORTC SFR registers -#define sfr_PORTC (*((PORT_t*) 0x500a)) - - -/// access to PORTD SFR registers -#define sfr_PORTD (*((PORT_t*) 0x500f)) - - -/// access to PORTE SFR registers -#define sfr_PORTE (*((PORT_t*) 0x5014)) - - -/// access to PORTF SFR registers -#define sfr_PORTF (*((PORT_t*) 0x5019)) - - -/// access to PORTG SFR registers -#define sfr_PORTG (*((PORT_t*) 0x501e)) - - -/// access to PORTH SFR registers -#define sfr_PORTH (*((PORT_t*) 0x5023)) - - -/// access to PORTI SFR registers -#define sfr_PORTI (*((PORT_t*) 0x5028)) - - -//------------------------ -// Module RST -//------------------------ - -/** struct containing RST module registers */ -typedef struct { - - /** Reset status register (SR at 0x50b3) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS WWDGF : 1; // bit 0 - BITS IWDGF : 1; // bit 1 - BITS ILLOPF : 1; // bit 2 - BITS SWIMF : 1; // bit 3 - BITS EMCF : 1; // bit 4 - BITS : 3; // 3 bits - }; // SR bitfield - - /// register _RST_SR reset value - #define sfr_RST_SR_RESET_VALUE ((uint8_t) 0x00) - - } SR; - -} RST_t; - -/// access to RST SFR registers -#define sfr_RST (*((RST_t*) 0x50b3)) - - -//------------------------ -// Module SPI -//------------------------ - -/** struct containing SPI module registers */ -typedef struct { - - /** SPI control register 1 (CR1 at 0x5200) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CPHA : 1; // bit 0 - BITS CPOL : 1; // bit 1 - BITS MSTR : 1; // bit 2 - BITS BR : 3; // bits 3-5 - BITS SPE : 1; // bit 6 - BITS LSBFIRST : 1; // bit 7 - }; // CR1 bitfield - - /// register _SPI_CR1 reset value - #define sfr_SPI_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** SPI control register 2 (CR2 at 0x5201) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS SSI : 1; // bit 0 - BITS SSM : 1; // bit 1 - BITS RXONLY : 1; // bit 2 - BITS : 1; // 1 bit - BITS CRCNEXT : 1; // bit 4 - BITS CECEN : 1; // bit 5 - BITS BDOE : 1; // bit 6 - BITS BDM : 1; // bit 7 - }; // CR2 bitfield - - /// register _SPI_CR2 reset value - #define sfr_SPI_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** SPI interrupt control register (ICR at 0x5202) */ - union { - - /// bytewise access to ICR - uint8_t byte; - - /// bitwise access to register ICR - struct { - BITS : 4; // 4 bits - BITS WKIE : 1; // bit 4 - BITS ERRIE : 1; // bit 5 - BITS RXIE : 1; // bit 6 - BITS TXIE : 1; // bit 7 - }; // ICR bitfield - - /// register _SPI_ICR reset value - #define sfr_SPI_ICR_RESET_VALUE ((uint8_t) 0x00) - - } ICR; - - - /** SPI status register (SR at 0x5203) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS RXNE : 1; // bit 0 - BITS TXE : 1; // bit 1 - BITS : 1; // 1 bit - BITS WKUP : 1; // bit 3 - BITS CRCERR : 1; // bit 4 - BITS MODF : 1; // bit 5 - BITS OVR : 1; // bit 6 - BITS BSY : 1; // bit 7 - }; // SR bitfield - - /// register _SPI_SR reset value - #define sfr_SPI_SR_RESET_VALUE ((uint8_t) 0x02) - - } SR; - - - /** SPI data register (DR at 0x5204) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _SPI_DR reset value - #define sfr_SPI_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** SPI CRC polynomial register (CRCPR at 0x5205) */ - union { - - /// bytewise access to CRCPR - uint8_t byte; - - /// bitwise access to register CRCPR - struct { - BITS CRCPOLY : 8; // bits 0-7 - }; // CRCPR bitfield - - /// register _SPI_CRCPR reset value - #define sfr_SPI_CRCPR_RESET_VALUE ((uint8_t) 0x07) - - } CRCPR; - - - /** SPI Rx CRC register (RXCRCR at 0x5206) */ - union { - - /// bytewise access to RXCRCR - uint8_t byte; - - /// bitwise access to register RXCRCR - struct { - BITS RXCRC : 8; // bits 0-7 - }; // RXCRCR bitfield - - /// register _SPI_RXCRCR reset value - #define sfr_SPI_RXCRCR_RESET_VALUE ((uint8_t) 0xFF) - - } RXCRCR; - - - /** SPI Tx CRC register (TXCRCR at 0x5207) */ - union { - - /// bytewise access to TXCRCR - uint8_t byte; - - /// bitwise access to register TXCRCR - struct { - BITS TXCRC : 8; // bits 0-7 - }; // TXCRCR bitfield - - /// register _SPI_TXCRCR reset value - #define sfr_SPI_TXCRCR_RESET_VALUE ((uint8_t) 0xFF) - - } TXCRCR; - -} SPI_t; - -/// access to SPI SFR registers -#define sfr_SPI (*((SPI_t*) 0x5200)) - - -//------------------------ -// Module SWIM -//------------------------ - -/** struct containing SWIM module registers */ -typedef struct { - - /** SWIM control status register (CSR at 0x7f80) */ - union { - - /// bytewise access to CSR - uint8_t byte; - - /// skip bitwise access to register CSR - - /// register _SWIM_CSR reset value - #define sfr_SWIM_CSR_RESET_VALUE ((uint8_t) 0x00) - - } CSR; - -} SWIM_t; - -/// access to SWIM SFR registers -#define sfr_SWIM (*((SWIM_t*) 0x7f80)) - - -//------------------------ -// Module TIM1 -//------------------------ - -/** struct containing TIM1 module registers */ -typedef struct { - - /** TIM1 control register 1 (CR1 at 0x5250) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS DIR : 1; // bit 4 - BITS CMS : 2; // bits 5-6 - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM1_CR1 reset value - #define sfr_TIM1_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM1 control register 2 (CR2 at 0x5251) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS CCPG : 1; // bit 0 - BITS : 1; // 1 bit - BITS COMS : 1; // bit 2 - BITS : 1; // 1 bit - BITS MMS : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CR2 bitfield - - /// register _TIM1_CR2 reset value - #define sfr_TIM1_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** TIM1 slave mode control register (SMCR at 0x5252) */ - union { - - /// bytewise access to SMCR - uint8_t byte; - - /// bitwise access to register SMCR - struct { - BITS SMS : 3; // bits 0-2 - BITS : 1; // 1 bit - BITS TS : 3; // bits 4-6 - BITS MSM : 1; // bit 7 - }; // SMCR bitfield - - /// register _TIM1_SMCR reset value - #define sfr_TIM1_SMCR_RESET_VALUE ((uint8_t) 0x00) - - } SMCR; - - - /** TIM1 external trigger register (ETR at 0x5253) */ - union { - - /// bytewise access to ETR - uint8_t byte; - - /// bitwise access to register ETR - struct { - BITS ETF : 4; // bits 0-3 - BITS ETPS : 2; // bits 4-5 - BITS ECE : 1; // bit 6 - BITS ETP : 1; // bit 7 - }; // ETR bitfield - - /// register _TIM1_ETR reset value - #define sfr_TIM1_ETR_RESET_VALUE ((uint8_t) 0x00) - - } ETR; - - - /** TIM1 Interrupt enable register (IER at 0x5254) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS CC1IE : 1; // bit 1 - BITS CC2IE : 1; // bit 2 - BITS CC3IE : 1; // bit 3 - BITS CC4IE : 1; // bit 4 - BITS COMIE : 1; // bit 5 - BITS TIE : 1; // bit 6 - BITS BIE : 1; // bit 7 - }; // IER bitfield - - /// register _TIM1_IER reset value - #define sfr_TIM1_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM1 status register 1 (SR1 at 0x5255) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS UIF : 1; // bit 0 - BITS CC1IF : 1; // bit 1 - BITS CC2IF : 1; // bit 2 - BITS CC3IF : 1; // bit 3 - BITS CC4IF : 1; // bit 4 - BITS COMIF : 1; // bit 5 - BITS TIF : 1; // bit 6 - BITS BIF : 1; // bit 7 - }; // SR1 bitfield - - /// register _TIM1_SR1 reset value - #define sfr_TIM1_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** TIM1 status register 2 (SR2 at 0x5256) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS : 1; // 1 bit - BITS CC1OF : 1; // bit 1 - BITS CC2OF : 1; // bit 2 - BITS CC3OF : 1; // bit 3 - BITS CC4OF : 1; // bit 4 - BITS : 3; // 3 bits - }; // SR2 bitfield - - /// register _TIM1_SR2 reset value - #define sfr_TIM1_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** TIM1 event generation register (EGR at 0x5257) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS CC1G : 1; // bit 1 - BITS CC2G : 1; // bit 2 - BITS CC3G : 1; // bit 3 - BITS CC4G : 1; // bit 4 - BITS COMG : 1; // bit 5 - BITS TG : 1; // bit 6 - BITS BG : 1; // bit 7 - }; // EGR bitfield - - /// register _TIM1_EGR reset value - #define sfr_TIM1_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM1 capture/compare mode register 1 (CCMR1 at 0x5258) */ - union { - - /// bytewise access to CCMR1 - uint8_t byte; - - /// bitwise access to register CCMR1 - struct { - BITS CC1S : 2; // bits 0-1 - BITS OC1FE : 1; // bit 2 - BITS OC1PE : 1; // bit 3 - BITS OC1M : 3; // bits 4-6 - BITS OC1CE : 1; // bit 7 - }; // CCMR1 bitfield - - /// register _TIM1_CCMR1 reset value - #define sfr_TIM1_CCMR1_RESET_VALUE ((uint8_t) 0x00) - - } CCMR1; - - - /** TIM1 capture/compare mode register 2 (CCMR2 at 0x5259) */ - union { - - /// bytewise access to CCMR2 - uint8_t byte; - - /// bitwise access to register CCMR2 - struct { - BITS CC2S : 2; // bits 0-1 - BITS OC2FE : 1; // bit 2 - BITS OC2PE : 1; // bit 3 - BITS OC2M : 3; // bits 4-6 - BITS OC2CE : 1; // bit 7 - }; // CCMR2 bitfield - - /// register _TIM1_CCMR2 reset value - #define sfr_TIM1_CCMR2_RESET_VALUE ((uint8_t) 0x00) - - } CCMR2; - - - /** TIM1 capture/compare mode register 3 (CCMR3 at 0x525a) */ - union { - - /// bytewise access to CCMR3 - uint8_t byte; - - /// bitwise access to register CCMR3 - struct { - BITS CC3S : 2; // bits 0-1 - BITS OC3FE : 1; // bit 2 - BITS OC3PE : 1; // bit 3 - BITS OC3M : 3; // bits 4-6 - BITS OC3CE : 1; // bit 7 - }; // CCMR3 bitfield - - /// register _TIM1_CCMR3 reset value - #define sfr_TIM1_CCMR3_RESET_VALUE ((uint8_t) 0x00) - - } CCMR3; - - - /** TIM1 capture/compare mode register 4 (CCMR4 at 0x525b) */ - union { - - /// bytewise access to CCMR4 - uint8_t byte; - - /// bitwise access to register CCMR4 - struct { - BITS CC4S : 2; // bits 0-1 - BITS OC4FE : 1; // bit 2 - BITS OC4PE : 1; // bit 3 - BITS OC4M : 3; // bits 4-6 - BITS OC4CE : 1; // bit 7 - }; // CCMR4 bitfield - - /// register _TIM1_CCMR4 reset value - #define sfr_TIM1_CCMR4_RESET_VALUE ((uint8_t) 0x00) - - } CCMR4; - - - /** TIM1 capture/compare enable register 1 (CCER1 at 0x525c) */ - union { - - /// bytewise access to CCER1 - uint8_t byte; - - /// bitwise access to register CCER1 - struct { - BITS CC1E : 1; // bit 0 - BITS CC1P : 1; // bit 1 - BITS CC1NE : 1; // bit 2 - BITS CC1NP : 1; // bit 3 - BITS CC2E : 1; // bit 4 - BITS CC2P : 1; // bit 5 - BITS CC2NE : 1; // bit 6 - BITS CC2NP : 1; // bit 7 - }; // CCER1 bitfield - - /// register _TIM1_CCER1 reset value - #define sfr_TIM1_CCER1_RESET_VALUE ((uint8_t) 0x00) - - } CCER1; - - - /** TIM1 capture/compare enable register 2 (CCER2 at 0x525d) */ - union { - - /// bytewise access to CCER2 - uint8_t byte; - - /// bitwise access to register CCER2 - struct { - BITS CC3E : 1; // bit 0 - BITS CC3P : 1; // bit 1 - BITS CC3NE : 1; // bit 2 - BITS CC3NP : 1; // bit 3 - BITS CC4E : 1; // bit 4 - BITS CC4P : 1; // bit 5 - BITS : 2; // 2 bits - }; // CCER2 bitfield - - /// register _TIM1_CCER2 reset value - #define sfr_TIM1_CCER2_RESET_VALUE ((uint8_t) 0x00) - - } CCER2; - - - /** TIM1 counter high (CNTRH at 0x525e) */ - union { - - /// bytewise access to CNTRH - uint8_t byte; - - /// bitwise access to register CNTRH - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRH bitfield - - /// register _TIM1_CNTRH reset value - #define sfr_TIM1_CNTRH_RESET_VALUE ((uint8_t) 0x00) - - } CNTRH; - - - /** TIM1 counter low (CNTRL at 0x525f) */ - union { - - /// bytewise access to CNTRL - uint8_t byte; - - /// bitwise access to register CNTRL - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRL bitfield - - /// register _TIM1_CNTRL reset value - #define sfr_TIM1_CNTRL_RESET_VALUE ((uint8_t) 0x00) - - } CNTRL; - - - /** TIM1 prescaler register high (PSCRH at 0x5260) */ - union { - - /// bytewise access to PSCRH - uint8_t byte; - - /// bitwise access to register PSCRH - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCRH bitfield - - /// register _TIM1_PSCRH reset value - #define sfr_TIM1_PSCRH_RESET_VALUE ((uint8_t) 0x00) - - } PSCRH; - - - /** TIM1 prescaler register low (PSCRL at 0x5261) */ - union { - - /// bytewise access to PSCRL - uint8_t byte; - - /// bitwise access to register PSCRL - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCRL bitfield - - /// register _TIM1_PSCRL reset value - #define sfr_TIM1_PSCRL_RESET_VALUE ((uint8_t) 0x00) - - } PSCRL; - - - /** TIM1 auto-reload register high (ARRH at 0x5262) */ - union { - - /// bytewise access to ARRH - uint8_t byte; - - /// bitwise access to register ARRH - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRH bitfield - - /// register _TIM1_ARRH reset value - #define sfr_TIM1_ARRH_RESET_VALUE ((uint8_t) 0xFF) - - } ARRH; - - - /** TIM1 auto-reload register low (ARRL at 0x5263) */ - union { - - /// bytewise access to ARRL - uint8_t byte; - - /// bitwise access to register ARRL - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRL bitfield - - /// register _TIM1_ARRL reset value - #define sfr_TIM1_ARRL_RESET_VALUE ((uint8_t) 0xFF) - - } ARRL; - - - /** TIM1 repetition counter register (RCR at 0x5264) */ - union { - - /// bytewise access to RCR - uint8_t byte; - - /// bitwise access to register RCR - struct { - BITS REP : 8; // bits 0-7 - }; // RCR bitfield - - /// register _TIM1_RCR reset value - #define sfr_TIM1_RCR_RESET_VALUE ((uint8_t) 0x00) - - } RCR; - - - /** TIM1 capture/compare register 1 high (CCR1H at 0x5265) */ - union { - - /// bytewise access to CCR1H - uint8_t byte; - - /// bitwise access to register CCR1H - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1H bitfield - - /// register _TIM1_CCR1H reset value - #define sfr_TIM1_CCR1H_RESET_VALUE ((uint8_t) 0x00) - - } CCR1H; - - - /** TIM1 capture/compare register 1 low (CCR1L at 0x5266) */ - union { - - /// bytewise access to CCR1L - uint8_t byte; - - /// bitwise access to register CCR1L - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1L bitfield - - /// register _TIM1_CCR1L reset value - #define sfr_TIM1_CCR1L_RESET_VALUE ((uint8_t) 0x00) - - } CCR1L; - - - /** TIM1 capture/compare register 2 high (CCR2H at 0x5267) */ - union { - - /// bytewise access to CCR2H - uint8_t byte; - - /// bitwise access to register CCR2H - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2H bitfield - - /// register _TIM1_CCR2H reset value - #define sfr_TIM1_CCR2H_RESET_VALUE ((uint8_t) 0x00) - - } CCR2H; - - - /** TIM1 capture/compare register 2 low (CCR2L at 0x5268) */ - union { - - /// bytewise access to CCR2L - uint8_t byte; - - /// bitwise access to register CCR2L - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2L bitfield - - /// register _TIM1_CCR2L reset value - #define sfr_TIM1_CCR2L_RESET_VALUE ((uint8_t) 0x00) - - } CCR2L; - - - /** TIM1 capture/compare register 3 high (CCR3H at 0x5269) */ - union { - - /// bytewise access to CCR3H - uint8_t byte; - - /// bitwise access to register CCR3H - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3H bitfield - - /// register _TIM1_CCR3H reset value - #define sfr_TIM1_CCR3H_RESET_VALUE ((uint8_t) 0x00) - - } CCR3H; - - - /** TIM1 capture/compare register 3 low (CCR3L at 0x526a) */ - union { - - /// bytewise access to CCR3L - uint8_t byte; - - /// bitwise access to register CCR3L - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3L bitfield - - /// register _TIM1_CCR3L reset value - #define sfr_TIM1_CCR3L_RESET_VALUE ((uint8_t) 0x00) - - } CCR3L; - - - /** TIM1 capture/compare register 4 high (CCR4H at 0x526b) */ - union { - - /// bytewise access to CCR4H - uint8_t byte; - - /// bitwise access to register CCR4H - struct { - BITS CCR4 : 8; // bits 0-7 - }; // CCR4H bitfield - - /// register _TIM1_CCR4H reset value - #define sfr_TIM1_CCR4H_RESET_VALUE ((uint8_t) 0x00) - - } CCR4H; - - - /** TIM1 capture/compare register 4 low (CCR4L at 0x526c) */ - union { - - /// bytewise access to CCR4L - uint8_t byte; - - /// bitwise access to register CCR4L - struct { - BITS CCR4 : 8; // bits 0-7 - }; // CCR4L bitfield - - /// register _TIM1_CCR4L reset value - #define sfr_TIM1_CCR4L_RESET_VALUE ((uint8_t) 0x00) - - } CCR4L; - - - /** TIM1 break register (BKR at 0x526d) */ - union { - - /// bytewise access to BKR - uint8_t byte; - - /// bitwise access to register BKR - struct { - BITS LOCK : 2; // bits 0-1 - BITS OSSI : 1; // bit 2 - BITS OSSR : 1; // bit 3 - BITS BKE : 1; // bit 4 - BITS BKP : 1; // bit 5 - BITS AOE : 1; // bit 6 - BITS MOE : 1; // bit 7 - }; // BKR bitfield - - /// register _TIM1_BKR reset value - #define sfr_TIM1_BKR_RESET_VALUE ((uint8_t) 0x00) - - } BKR; - - - /** TIM1 dead-time register (DTR at 0x526e) */ - union { - - /// bytewise access to DTR - uint8_t byte; - - /// bitwise access to register DTR - struct { - BITS DTG : 8; // bits 0-7 - }; // DTR bitfield - - /// register _TIM1_DTR reset value - #define sfr_TIM1_DTR_RESET_VALUE ((uint8_t) 0x00) - - } DTR; - - - /** TIM1 output idle state register (OISR at 0x526f) */ - union { - - /// bytewise access to OISR - uint8_t byte; - - /// bitwise access to register OISR - struct { - BITS OIS1 : 1; // bit 0 - BITS OIS1N : 1; // bit 1 - BITS OIS2 : 1; // bit 2 - BITS OIS2N : 1; // bit 3 - BITS OIS3 : 1; // bit 4 - BITS OIS3N : 1; // bit 5 - BITS OIS4 : 1; // bit 6 - BITS : 1; // 1 bit - }; // OISR bitfield - - /// register _TIM1_OISR reset value - #define sfr_TIM1_OISR_RESET_VALUE ((uint8_t) 0x00) - - } OISR; - -} TIM1_t; - -/// access to TIM1 SFR registers -#define sfr_TIM1 (*((TIM1_t*) 0x5250)) - - -//------------------------ -// Module TIM2 -//------------------------ - -/** struct containing TIM2 module registers */ -typedef struct { - - /** TIM2 control register 1 (CR1 at 0x5300) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS : 3; // 3 bits - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM2_CR1 reset value - #define sfr_TIM2_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM2 interrupt enable register (IER at 0x5301) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS CC1IE : 1; // bit 1 - BITS CC2IE : 1; // bit 2 - BITS CC3IE : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIE : 1; // bit 6 - BITS : 1; // 1 bit - }; // IER bitfield - - /// register _TIM2_IER reset value - #define sfr_TIM2_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM2 status register 1 (SR1 at 0x5302) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS UIF : 1; // bit 0 - BITS CC1IF : 1; // bit 1 - BITS CC2IF : 1; // bit 2 - BITS CC3IF : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIF : 1; // bit 6 - BITS : 1; // 1 bit - }; // SR1 bitfield - - /// register _TIM2_SR1 reset value - #define sfr_TIM2_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** TIM2 status register 2 (SR2 at 0x5303) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS : 1; // 1 bit - BITS CC1OF : 1; // bit 1 - BITS CC2OF : 1; // bit 2 - BITS CC3OF : 1; // bit 3 - BITS : 4; // 4 bits - }; // SR2 bitfield - - /// register _TIM2_SR2 reset value - #define sfr_TIM2_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** TIM2 event generation register (EGR at 0x5304) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS CC1G : 1; // bit 1 - BITS CC2G : 1; // bit 2 - BITS CC3G : 1; // bit 3 - BITS : 2; // 2 bits - BITS TG : 1; // bit 6 - BITS : 1; // 1 bit - }; // EGR bitfield - - /// register _TIM2_EGR reset value - #define sfr_TIM2_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM2 capture/compare mode register 1 (CCMR1 at 0x5305) */ - union { - - /// bytewise access to CCMR1 - uint8_t byte; - - /// bitwise access to register CCMR1 - struct { - BITS CC1S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC1PE : 1; // bit 3 - BITS OC1M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR1 bitfield - - /// register _TIM2_CCMR1 reset value - #define sfr_TIM2_CCMR1_RESET_VALUE ((uint8_t) 0x00) - - } CCMR1; - - - /** TIM2 capture/compare mode register 2 (CCMR2 at 0x5306) */ - union { - - /// bytewise access to CCMR2 - uint8_t byte; - - /// bitwise access to register CCMR2 - struct { - BITS CC2S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC2PE : 1; // bit 3 - BITS OC2M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR2 bitfield - - /// register _TIM2_CCMR2 reset value - #define sfr_TIM2_CCMR2_RESET_VALUE ((uint8_t) 0x00) - - } CCMR2; - - - /** TIM2 capture/compare mode register 3 (CCMR3 at 0x5307) */ - union { - - /// bytewise access to CCMR3 - uint8_t byte; - - /// bitwise access to register CCMR3 - struct { - BITS CC3S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC3PE : 1; // bit 3 - BITS OC3M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR3 bitfield - - /// register _TIM2_CCMR3 reset value - #define sfr_TIM2_CCMR3_RESET_VALUE ((uint8_t) 0x00) - - } CCMR3; - - - /** TIM2 capture/compare enable register 1 (CCER1 at 0x5308) */ - union { - - /// bytewise access to CCER1 - uint8_t byte; - - /// bitwise access to register CCER1 - struct { - BITS CC1E : 1; // bit 0 - BITS CC1P : 1; // bit 1 - BITS : 2; // 2 bits - BITS CC2E : 1; // bit 4 - BITS CC2P : 1; // bit 5 - BITS : 2; // 2 bits - }; // CCER1 bitfield - - /// register _TIM2_CCER1 reset value - #define sfr_TIM2_CCER1_RESET_VALUE ((uint8_t) 0x00) - - } CCER1; - - - /** TIM2 capture/compare enable register 2 (CCER2 at 0x5309) */ - union { - - /// bytewise access to CCER2 - uint8_t byte; - - /// bitwise access to register CCER2 - struct { - BITS CC3E : 1; // bit 0 - BITS CC3P : 1; // bit 1 - BITS : 6; // 6 bits - }; // CCER2 bitfield - - /// register _TIM2_CCER2 reset value - #define sfr_TIM2_CCER2_RESET_VALUE ((uint8_t) 0x00) - - } CCER2; - - - /** TIM2 counter high (CNTRH at 0x530a) */ - union { - - /// bytewise access to CNTRH - uint8_t byte; - - /// bitwise access to register CNTRH - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRH bitfield - - /// register _TIM2_CNTRH reset value - #define sfr_TIM2_CNTRH_RESET_VALUE ((uint8_t) 0x00) - - } CNTRH; - - - /** TIM2 counter low (CNTRL at 0x530b) */ - union { - - /// bytewise access to CNTRL - uint8_t byte; - - /// bitwise access to register CNTRL - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRL bitfield - - /// register _TIM2_CNTRL reset value - #define sfr_TIM2_CNTRL_RESET_VALUE ((uint8_t) 0x00) - - } CNTRL; - - - /** TIM2 prescaler register (PSCR at 0x530c) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // PSCR bitfield - - /// register _TIM2_PSCR reset value - #define sfr_TIM2_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - - - /** TIM2 auto-reload register high (ARRH at 0x530d) */ - union { - - /// bytewise access to ARRH - uint8_t byte; - - /// bitwise access to register ARRH - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRH bitfield - - /// register _TIM2_ARRH reset value - #define sfr_TIM2_ARRH_RESET_VALUE ((uint8_t) 0xFF) - - } ARRH; - - - /** TIM2 auto-reload register low (ARRL at 0x530e) */ - union { - - /// bytewise access to ARRL - uint8_t byte; - - /// bitwise access to register ARRL - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRL bitfield - - /// register _TIM2_ARRL reset value - #define sfr_TIM2_ARRL_RESET_VALUE ((uint8_t) 0xFF) - - } ARRL; - - - /** TIM2 capture/compare register 1 high (CCR1H at 0x530f) */ - union { - - /// bytewise access to CCR1H - uint8_t byte; - - /// bitwise access to register CCR1H - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1H bitfield - - /// register _TIM2_CCR1H reset value - #define sfr_TIM2_CCR1H_RESET_VALUE ((uint8_t) 0x00) - - } CCR1H; - - - /** TIM2 capture/compare register 1 low (CCR1L at 0x5310) */ - union { - - /// bytewise access to CCR1L - uint8_t byte; - - /// bitwise access to register CCR1L - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1L bitfield - - /// register _TIM2_CCR1L reset value - #define sfr_TIM2_CCR1L_RESET_VALUE ((uint8_t) 0x00) - - } CCR1L; - - - /** TIM2 capture/compare reg (CCR2H at 0x5311) */ - union { - - /// bytewise access to CCR2H - uint8_t byte; - - /// bitwise access to register CCR2H - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2H bitfield - - /// register _TIM2_CCR2H reset value - #define sfr_TIM2_CCR2H_RESET_VALUE ((uint8_t) 0x00) - - } CCR2H; - - - /** TIM2 capture/compare register 2 low (CCR2L at 0x5312) */ - union { - - /// bytewise access to CCR2L - uint8_t byte; - - /// bitwise access to register CCR2L - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2L bitfield - - /// register _TIM2_CCR2L reset value - #define sfr_TIM2_CCR2L_RESET_VALUE ((uint8_t) 0x00) - - } CCR2L; - - - /** TIM2 capture/compare register 3 high (CCR3H at 0x5313) */ - union { - - /// bytewise access to CCR3H - uint8_t byte; - - /// bitwise access to register CCR3H - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3H bitfield - - /// register _TIM2_CCR3H reset value - #define sfr_TIM2_CCR3H_RESET_VALUE ((uint8_t) 0x00) - - } CCR3H; - - - /** TIM2 capture/compare register 3 low (CCR3L at 0x5314) */ - union { - - /// bytewise access to CCR3L - uint8_t byte; - - /// bitwise access to register CCR3L - struct { - BITS CCR3 : 8; // bits 0-7 - }; // CCR3L bitfield - - /// register _TIM2_CCR3L reset value - #define sfr_TIM2_CCR3L_RESET_VALUE ((uint8_t) 0x00) - - } CCR3L; - -} TIM2_t; - -/// access to TIM2 SFR registers -#define sfr_TIM2 (*((TIM2_t*) 0x5300)) - - -//------------------------ -// Module TIM3 -//------------------------ - -/** struct containing TIM3 module registers */ -typedef struct { - - /** TIM3 control register 1 (CR1 at 0x5320) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS : 3; // 3 bits - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM3_CR1 reset value - #define sfr_TIM3_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM3 interrupt enable register (IER at 0x5321) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS CC1IE : 1; // bit 1 - BITS CC2IE : 1; // bit 2 - BITS CC3IE : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIE : 1; // bit 6 - BITS : 1; // 1 bit - }; // IER bitfield - - /// register _TIM3_IER reset value - #define sfr_TIM3_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM3 status register 1 (SR1 at 0x5322) */ - union { - - /// bytewise access to SR1 - uint8_t byte; - - /// bitwise access to register SR1 - struct { - BITS UIF : 1; // bit 0 - BITS CC1IF : 1; // bit 1 - BITS CC2IF : 1; // bit 2 - BITS CC3IF : 1; // bit 3 - BITS : 2; // 2 bits - BITS TIF : 1; // bit 6 - BITS : 1; // 1 bit - }; // SR1 bitfield - - /// register _TIM3_SR1 reset value - #define sfr_TIM3_SR1_RESET_VALUE ((uint8_t) 0x00) - - } SR1; - - - /** TIM3 status register 2 (SR2 at 0x5323) */ - union { - - /// bytewise access to SR2 - uint8_t byte; - - /// bitwise access to register SR2 - struct { - BITS : 1; // 1 bit - BITS CC1OF : 1; // bit 1 - BITS CC2OF : 1; // bit 2 - BITS CC3OF : 1; // bit 3 - BITS : 4; // 4 bits - }; // SR2 bitfield - - /// register _TIM3_SR2 reset value - #define sfr_TIM3_SR2_RESET_VALUE ((uint8_t) 0x00) - - } SR2; - - - /** TIM3 event generation register (EGR at 0x5324) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS CC1G : 1; // bit 1 - BITS CC2G : 1; // bit 2 - BITS CC3G : 1; // bit 3 - BITS : 2; // 2 bits - BITS TG : 1; // bit 6 - BITS : 1; // 1 bit - }; // EGR bitfield - - /// register _TIM3_EGR reset value - #define sfr_TIM3_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM3 capture/compare mode register 1 (CCMR1 at 0x5325) */ - union { - - /// bytewise access to CCMR1 - uint8_t byte; - - /// bitwise access to register CCMR1 - struct { - BITS CC1S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC1PE : 1; // bit 3 - BITS OC1M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR1 bitfield - - /// register _TIM3_CCMR1 reset value - #define sfr_TIM3_CCMR1_RESET_VALUE ((uint8_t) 0x00) - - } CCMR1; - - - /** TIM3 capture/compare mode register 2 (CCMR2 at 0x5326) */ - union { - - /// bytewise access to CCMR2 - uint8_t byte; - - /// bitwise access to register CCMR2 - struct { - BITS CC2S : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS OC2PE : 1; // bit 3 - BITS OC2M : 3; // bits 4-6 - BITS : 1; // 1 bit - }; // CCMR2 bitfield - - /// register _TIM3_CCMR2 reset value - #define sfr_TIM3_CCMR2_RESET_VALUE ((uint8_t) 0x00) - - } CCMR2; - - - /** TIM3 capture/compare enable register 1 (CCER1 at 0x5327) */ - union { - - /// bytewise access to CCER1 - uint8_t byte; - - /// bitwise access to register CCER1 - struct { - BITS CC1E : 1; // bit 0 - BITS CC1P : 1; // bit 1 - BITS : 2; // 2 bits - BITS CC2E : 1; // bit 4 - BITS CC2P : 1; // bit 5 - BITS : 2; // 2 bits - }; // CCER1 bitfield - - /// register _TIM3_CCER1 reset value - #define sfr_TIM3_CCER1_RESET_VALUE ((uint8_t) 0x00) - - } CCER1; - - - /** TIM3 counter high (CNTRH at 0x5328) */ - union { - - /// bytewise access to CNTRH - uint8_t byte; - - /// bitwise access to register CNTRH - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRH bitfield - - /// register _TIM3_CNTRH reset value - #define sfr_TIM3_CNTRH_RESET_VALUE ((uint8_t) 0x00) - - } CNTRH; - - - /** TIM3 counter low (CNTRL at 0x5329) */ - union { - - /// bytewise access to CNTRL - uint8_t byte; - - /// bitwise access to register CNTRL - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTRL bitfield - - /// register _TIM3_CNTRL reset value - #define sfr_TIM3_CNTRL_RESET_VALUE ((uint8_t) 0x00) - - } CNTRL; - - - /** TIM3 prescaler register (PSCR at 0x532a) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 4; // bits 0-3 - BITS : 4; // 4 bits - }; // PSCR bitfield - - /// register _TIM3_PSCR reset value - #define sfr_TIM3_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - - - /** TIM3 auto-reload register high (ARRH at 0x532b) */ - union { - - /// bytewise access to ARRH - uint8_t byte; - - /// bitwise access to register ARRH - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRH bitfield - - /// register _TIM3_ARRH reset value - #define sfr_TIM3_ARRH_RESET_VALUE ((uint8_t) 0xFF) - - } ARRH; - - - /** TIM3 auto-reload register low (ARRL at 0x532c) */ - union { - - /// bytewise access to ARRL - uint8_t byte; - - /// bitwise access to register ARRL - struct { - BITS ARR : 8; // bits 0-7 - }; // ARRL bitfield - - /// register _TIM3_ARRL reset value - #define sfr_TIM3_ARRL_RESET_VALUE ((uint8_t) 0xFF) - - } ARRL; - - - /** TIM3 capture/compare register 1 high (CCR1H at 0x532d) */ - union { - - /// bytewise access to CCR1H - uint8_t byte; - - /// bitwise access to register CCR1H - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1H bitfield - - /// register _TIM3_CCR1H reset value - #define sfr_TIM3_CCR1H_RESET_VALUE ((uint8_t) 0x00) - - } CCR1H; - - - /** TIM3 capture/compare register 1 low (CCR1L at 0x532e) */ - union { - - /// bytewise access to CCR1L - uint8_t byte; - - /// bitwise access to register CCR1L - struct { - BITS CCR1 : 8; // bits 0-7 - }; // CCR1L bitfield - - /// register _TIM3_CCR1L reset value - #define sfr_TIM3_CCR1L_RESET_VALUE ((uint8_t) 0x00) - - } CCR1L; - - - /** TIM3 capture/compare register 2 high (CCR2H at 0x532f) */ - union { - - /// bytewise access to CCR2H - uint8_t byte; - - /// bitwise access to register CCR2H - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2H bitfield - - /// register _TIM3_CCR2H reset value - #define sfr_TIM3_CCR2H_RESET_VALUE ((uint8_t) 0x00) - - } CCR2H; - - - /** TIM3 capture/compare register 2 low (CCR2L at 0x5330) */ - union { - - /// bytewise access to CCR2L - uint8_t byte; - - /// bitwise access to register CCR2L - struct { - BITS CCR2 : 8; // bits 0-7 - }; // CCR2L bitfield - - /// register _TIM3_CCR2L reset value - #define sfr_TIM3_CCR2L_RESET_VALUE ((uint8_t) 0x00) - - } CCR2L; - -} TIM3_t; - -/// access to TIM3 SFR registers -#define sfr_TIM3 (*((TIM3_t*) 0x5320)) - - -//------------------------ -// Module TIM4 -//------------------------ - -/** struct containing TIM4 module registers */ -typedef struct { - - /** TIM4 control register 1 (CR1 at 0x5340) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS CEN : 1; // bit 0 - BITS UDIS : 1; // bit 1 - BITS URS : 1; // bit 2 - BITS OPM : 1; // bit 3 - BITS : 3; // 3 bits - BITS ARPE : 1; // bit 7 - }; // CR1 bitfield - - /// register _TIM4_CR1 reset value - #define sfr_TIM4_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** TIM4 interrupt enable register (IER at 0x5341) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS UIE : 1; // bit 0 - BITS : 5; // 5 bits - BITS TIE : 1; // bit 6 - BITS : 1; // 1 bit - }; // IER bitfield - - /// register _TIM4_IER reset value - #define sfr_TIM4_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** TIM4 status register (SR at 0x5342) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS UIF : 1; // bit 0 - BITS : 5; // 5 bits - BITS TIF : 1; // bit 6 - BITS : 1; // 1 bit - }; // SR bitfield - - /// register _TIM4_SR reset value - #define sfr_TIM4_SR_RESET_VALUE ((uint8_t) 0x00) - - } SR; - - - /** TIM4 event generation register (EGR at 0x5343) */ - union { - - /// bytewise access to EGR - uint8_t byte; - - /// bitwise access to register EGR - struct { - BITS UG : 1; // bit 0 - BITS : 5; // 5 bits - BITS TG : 1; // bit 6 - BITS : 1; // 1 bit - }; // EGR bitfield - - /// register _TIM4_EGR reset value - #define sfr_TIM4_EGR_RESET_VALUE ((uint8_t) 0x00) - - } EGR; - - - /** TIM4 counter (CNTR at 0x5344) */ - union { - - /// bytewise access to CNTR - uint8_t byte; - - /// bitwise access to register CNTR - struct { - BITS CNT : 8; // bits 0-7 - }; // CNTR bitfield - - /// register _TIM4_CNTR reset value - #define sfr_TIM4_CNTR_RESET_VALUE ((uint8_t) 0x00) - - } CNTR; - - - /** TIM4 prescaler register (PSCR at 0x5345) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // PSCR bitfield - - /// register _TIM4_PSCR reset value - #define sfr_TIM4_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - - - /** TIM4 auto-reload register (ARR at 0x5346) */ - union { - - /// bytewise access to ARR - uint8_t byte; - - /// bitwise access to register ARR - struct { - BITS ARR : 8; // bits 0-7 - }; // ARR bitfield - - /// register _TIM4_ARR reset value - #define sfr_TIM4_ARR_RESET_VALUE ((uint8_t) 0xFF) - - } ARR; - -} TIM4_t; - -/// access to TIM4 SFR registers -#define sfr_TIM4 (*((TIM4_t*) 0x5340)) - - -//------------------------ -// Module UART1 -//------------------------ - -/** struct containing UART1 module registers */ -typedef struct { - - /** UART1 status register (SR at 0x5230) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS PE : 1; // bit 0 - BITS FE : 1; // bit 1 - BITS NF : 1; // bit 2 - BITS OR_LHE : 1; // bit 3 - BITS IDLE : 1; // bit 4 - BITS RXNE : 1; // bit 5 - BITS TC : 1; // bit 6 - BITS TXE : 1; // bit 7 - }; // SR bitfield - - /// register _UART1_SR reset value - #define sfr_UART1_SR_RESET_VALUE ((uint8_t) 0xC0) - - } SR; - - - /** UART1 data register (DR at 0x5231) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _UART1_DR reset value - #define sfr_UART1_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** UART1 baud rate register 1 (BRR1 at 0x5232) */ - union { - - /// bytewise access to BRR1 - uint8_t byte; - - /// bitwise access to register BRR1 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR1 bitfield - - /// register _UART1_BRR1 reset value - #define sfr_UART1_BRR1_RESET_VALUE ((uint8_t) 0x00) - - } BRR1; - - - /** UART1 baud rate register 2 (BRR2 at 0x5233) */ - union { - - /// bytewise access to BRR2 - uint8_t byte; - - /// bitwise access to register BRR2 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR2 bitfield - - /// register _UART1_BRR2 reset value - #define sfr_UART1_BRR2_RESET_VALUE ((uint8_t) 0x00) - - } BRR2; - - - /** UART1 control register 1 (CR1 at 0x5234) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PIEN : 1; // bit 0 - BITS PS : 1; // bit 1 - BITS PCEN : 1; // bit 2 - BITS WAKE : 1; // bit 3 - BITS M : 1; // bit 4 - BITS UART0 : 1; // bit 5 - BITS T8 : 1; // bit 6 - BITS R8 : 1; // bit 7 - }; // CR1 bitfield - - /// register _UART1_CR1 reset value - #define sfr_UART1_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** UART1 control register 2 (CR2 at 0x5235) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS SBK : 1; // bit 0 - BITS RWU : 1; // bit 1 - BITS REN : 1; // bit 2 - BITS TEN : 1; // bit 3 - BITS ILIEN : 1; // bit 4 - BITS RIEN : 1; // bit 5 - BITS TCIEN : 1; // bit 6 - BITS TIEN : 1; // bit 7 - }; // CR2 bitfield - - /// register _UART1_CR2 reset value - #define sfr_UART1_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** UART1 control register 3 (CR3 at 0x5236) */ - union { - - /// bytewise access to CR3 - uint8_t byte; - - /// bitwise access to register CR3 - struct { - BITS LBCL : 1; // bit 0 - BITS CPHA : 1; // bit 1 - BITS CPOL : 1; // bit 2 - BITS CKEN : 1; // bit 3 - BITS STOP : 2; // bits 4-5 - BITS : 1; // 1 bit - BITS LINEN : 1; // bit 7 - }; // CR3 bitfield - - /// register _UART1_CR3 reset value - #define sfr_UART1_CR3_RESET_VALUE ((uint8_t) 0x00) - - } CR3; - - - /** UART1 control register 4 (CR4 at 0x5237) */ - union { - - /// bytewise access to CR4 - uint8_t byte; - - /// bitwise access to register CR4 - struct { - BITS ADD : 4; // bits 0-3 - BITS LBDF : 1; // bit 4 - BITS LBDL : 1; // bit 5 - BITS LBDIEN : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR4 bitfield - - /// register _UART1_CR4 reset value - #define sfr_UART1_CR4_RESET_VALUE ((uint8_t) 0x00) - - } CR4; - - - /** UART1 control register 5 (CR5 at 0x5238) */ - union { - - /// bytewise access to CR5 - uint8_t byte; - - /// bitwise access to register CR5 - struct { - BITS : 1; // 1 bit - BITS IREN : 1; // bit 1 - BITS IRLP : 1; // bit 2 - BITS HDSEL : 1; // bit 3 - BITS NACK : 1; // bit 4 - BITS SCEN : 1; // bit 5 - BITS : 2; // 2 bits - }; // CR5 bitfield - - /// register _UART1_CR5 reset value - #define sfr_UART1_CR5_RESET_VALUE ((uint8_t) 0x00) - - } CR5; - - - /** UART1 guard time register (GTR at 0x5239) */ - union { - - /// bytewise access to GTR - uint8_t byte; - - /// bitwise access to register GTR - struct { - BITS GT : 8; // bits 0-7 - }; // GTR bitfield - - /// register _UART1_GTR reset value - #define sfr_UART1_GTR_RESET_VALUE ((uint8_t) 0x00) - - } GTR; - - - /** UART1 prescaler register (PSCR at 0x523a) */ - union { - - /// bytewise access to PSCR - uint8_t byte; - - /// bitwise access to register PSCR - struct { - BITS PSC : 8; // bits 0-7 - }; // PSCR bitfield - - /// register _UART1_PSCR reset value - #define sfr_UART1_PSCR_RESET_VALUE ((uint8_t) 0x00) - - } PSCR; - -} UART1_t; - -/// access to UART1 SFR registers -#define sfr_UART1 (*((UART1_t*) 0x5230)) - - -//------------------------ -// Module UART3 -//------------------------ - -/** struct containing UART3 module registers */ -typedef struct { - - /** UART3 status register (SR at 0x5240) */ - union { - - /// bytewise access to SR - uint8_t byte; - - /// bitwise access to register SR - struct { - BITS PE : 1; // bit 0 - BITS FE : 1; // bit 1 - BITS NF : 1; // bit 2 - BITS OR : 1; // bit 3 - BITS IDLE : 1; // bit 4 - BITS RXNE : 1; // bit 5 - BITS TC : 1; // bit 6 - BITS TXE : 1; // bit 7 - }; // SR bitfield - - /// register _UART3_SR reset value - #define sfr_UART3_SR_RESET_VALUE ((uint8_t) 0xC0) - - } SR; - - - /** UART3 data register (DR at 0x5241) */ - union { - - /// bytewise access to DR - uint8_t byte; - - /// bitwise access to register DR - struct { - BITS DR : 8; // bits 0-7 - }; // DR bitfield - - /// register _UART3_DR reset value - #define sfr_UART3_DR_RESET_VALUE ((uint8_t) 0x00) - - } DR; - - - /** UART3 baud rate register 1 (BRR1 at 0x5242) */ - union { - - /// bytewise access to BRR1 - uint8_t byte; - - /// bitwise access to register BRR1 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR1 bitfield - - /// register _UART3_BRR1 reset value - #define sfr_UART3_BRR1_RESET_VALUE ((uint8_t) 0x00) - - } BRR1; - - - /** UART3 baud rate register 2 (BRR2 at 0x5243) */ - union { - - /// bytewise access to BRR2 - uint8_t byte; - - /// bitwise access to register BRR2 - struct { - BITS UART_DIV : 8; // bits 0-7 - }; // BRR2 bitfield - - /// register _UART3_BRR2 reset value - #define sfr_UART3_BRR2_RESET_VALUE ((uint8_t) 0x00) - - } BRR2; - - - /** UART3 control register 1 (CR1 at 0x5244) */ - union { - - /// bytewise access to CR1 - uint8_t byte; - - /// bitwise access to register CR1 - struct { - BITS PIEN : 1; // bit 0 - BITS PS : 1; // bit 1 - BITS PCEN : 1; // bit 2 - BITS WAKE : 1; // bit 3 - BITS M : 1; // bit 4 - BITS UARTD : 1; // bit 5 - BITS T8 : 1; // bit 6 - BITS R8 : 1; // bit 7 - }; // CR1 bitfield - - /// register _UART3_CR1 reset value - #define sfr_UART3_CR1_RESET_VALUE ((uint8_t) 0x00) - - } CR1; - - - /** UART3 control register 2 (CR2 at 0x5245) */ - union { - - /// bytewise access to CR2 - uint8_t byte; - - /// bitwise access to register CR2 - struct { - BITS SBK : 1; // bit 0 - BITS RWU : 1; // bit 1 - BITS REN : 1; // bit 2 - BITS TEN : 1; // bit 3 - BITS ILIEN : 1; // bit 4 - BITS RIEN : 1; // bit 5 - BITS TCIEN : 1; // bit 6 - BITS TIEN : 1; // bit 7 - }; // CR2 bitfield - - /// register _UART3_CR2 reset value - #define sfr_UART3_CR2_RESET_VALUE ((uint8_t) 0x00) - - } CR2; - - - /** UART3 control register 3 (CR3 at 0x5246) */ - union { - - /// bytewise access to CR3 - uint8_t byte; - - /// bitwise access to register CR3 - struct { - BITS : 4; // 4 bits - BITS STOP : 2; // bits 4-5 - BITS LINEN : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR3 bitfield - - /// register _UART3_CR3 reset value - #define sfr_UART3_CR3_RESET_VALUE ((uint8_t) 0x00) - - } CR3; - - - /** UART3 control register 4 (CR4 at 0x5247) */ - union { - - /// bytewise access to CR4 - uint8_t byte; - - /// bitwise access to register CR4 - struct { - BITS ADD : 4; // bits 0-3 - BITS LBDF : 1; // bit 4 - BITS LBDL : 1; // bit 5 - BITS LBDIEN : 1; // bit 6 - BITS : 1; // 1 bit - }; // CR4 bitfield - - /// register _UART3_CR4 reset value - #define sfr_UART3_CR4_RESET_VALUE ((uint8_t) 0x00) - - } CR4; - - - /// Reserved register (1B) - uint8_t Reserved_1[1]; - - - /** UART3 control register 6 (CR6 at 0x5249) */ - union { - - /// bytewise access to CR6 - uint8_t byte; - - /// bitwise access to register CR6 - struct { - BITS LSF : 1; // bit 0 - BITS LHDF : 1; // bit 1 - BITS LHDIEN : 1; // bit 2 - BITS : 1; // 1 bit - BITS LASE : 1; // bit 4 - BITS LSLV : 1; // bit 5 - BITS : 1; // 1 bit - BITS LDUM : 1; // bit 7 - }; // CR6 bitfield - - /// register _UART3_CR6 reset value - #define sfr_UART3_CR6_RESET_VALUE ((uint8_t) 0x00) - - } CR6; - -} UART3_t; - -/// access to UART3 SFR registers -#define sfr_UART3 (*((UART3_t*) 0x5240)) - - -//------------------------ -// Module WWDG -//------------------------ - -/** struct containing WWDG module registers */ -typedef struct { - - /** WWDG control register (CR at 0x50d1) */ - union { - - /// bytewise access to CR - uint8_t byte; - - /// bitwise access to register CR - struct { - BITS T0 : 1; // bit 0 - BITS T1 : 1; // bit 1 - BITS T2 : 1; // bit 2 - BITS T3 : 1; // bit 3 - BITS T4 : 1; // bit 4 - BITS T5 : 1; // bit 5 - BITS T6 : 1; // bit 6 - BITS WDGA : 1; // bit 7 - }; // CR bitfield - - /// register _WWDG_CR reset value - #define sfr_WWDG_CR_RESET_VALUE ((uint8_t) 0x7F) - - } CR; - - - /** WWDR window register (WR at 0x50d2) */ - union { - - /// bytewise access to WR - uint8_t byte; - - /// bitwise access to register WR - struct { - BITS W0 : 1; // bit 0 - BITS W1 : 1; // bit 1 - BITS W2 : 1; // bit 2 - BITS W3 : 1; // bit 3 - BITS W4 : 1; // bit 4 - BITS W5 : 1; // bit 5 - BITS W6 : 1; // bit 6 - BITS : 1; // 1 bit - }; // WR bitfield - - /// register _WWDG_WR reset value - #define sfr_WWDG_WR_RESET_VALUE ((uint8_t) 0x7F) - - } WR; - -} WWDG_t; - -/// access to WWDG SFR registers -#define sfr_WWDG (*((WWDG_t*) 0x50d1)) - - -//------------------------ -// Module CAN -//------------------------ - -/** struct containing CAN module registers */ -typedef struct { - - /** CAN master control register (MCR at 0x5420) */ - union { - - /// bytewise access to MCR - uint8_t byte; - - /// bitwise access to register MCR - struct { - BITS INRQ : 1; // bit 0 - BITS SLEEP : 1; // bit 1 - BITS TXFP : 1; // bit 2 - BITS RFLM : 1; // bit 3 - BITS NART : 1; // bit 4 - BITS AWUM : 1; // bit 5 - BITS ABOM : 1; // bit 6 - BITS TTOM : 1; // bit 7 - }; // MCR bitfield - - /// register CAN_MCR reset value - #define sfr_CAN_MCR_RESET_VALUE ((uint8_t) 0x02) - - } MCR; - - - /** CAN master status register (MSR at 0x5421) */ - union { - - /// bytewise access to MSR - uint8_t byte; - - /// bitwise access to register MSR - struct { - BITS INAK : 1; // bit 0 - BITS SLAK : 1; // bit 1 - BITS ERRI : 1; // bit 2 - BITS WKUI : 1; // bit 3 - BITS TX : 1; // bit 4 - BITS RX : 1; // bit 5 - BITS : 2; // 2 bits - }; // MSR bitfield - - /// register CAN_MSR reset value - #define sfr_CAN_MSR_RESET_VALUE ((uint8_t) 0x02) - - } MSR; - - - /** CAN transmit status register (TSR at 0x5422) */ - union { - - /// bytewise access to TSR - uint8_t byte; - - /// bitwise access to register TSR - struct { - BITS RQCP0 : 1; // bit 0 - BITS RQCP1 : 1; // bit 1 - BITS RQCP2 : 1; // bit 2 - BITS : 1; // 1 bit - BITS TXQOK0 : 1; // bit 4 - BITS TXQOK1 : 1; // bit 5 - BITS TXQOK2 : 1; // bit 6 - BITS : 1; // 1 bit - }; // TSR bitfield - - /// register CAN_TSR reset value - #define sfr_CAN_TSR_RESET_VALUE ((uint8_t) 0x00) - - } TSR; - - - /** CAN transmit priority register (TPR at 0x5423) */ - union { - - /// bytewise access to TPR - uint8_t byte; - - /// bitwise access to register TPR - struct { - BITS CODE0 : 1; // bit 0 - BITS CODE1 : 1; // bit 1 - BITS TME0 : 1; // bit 2 - BITS TME1 : 1; // bit 3 - BITS TME2 : 1; // bit 4 - BITS LOW0 : 1; // bit 5 - BITS LOW1 : 1; // bit 6 - BITS LOW2 : 1; // bit 7 - }; // TPR bitfield - - /// register CAN_TPR reset value - #define sfr_CAN_TPR_RESET_VALUE ((uint8_t) 0x0C) - - } TPR; - - - /** CAN receive FIFO register (RFR at 0x5424) */ - union { - - /// bytewise access to RFR - uint8_t byte; - - /// bitwise access to register RFR - struct { - BITS FMP : 2; // bits 0-1 - BITS : 1; // 1 bit - BITS FULL : 1; // bit 3 - BITS FOVR : 1; // bit 4 - BITS RFOM : 1; // bit 5 - BITS : 2; // 2 bits - }; // RFR bitfield - - /// register CAN_RFR reset value - #define sfr_CAN_RFR_RESET_VALUE ((uint8_t) 0x00) - - } RFR; - - - /** CAN interrupt enable register (IER at 0x5425) */ - union { - - /// bytewise access to IER - uint8_t byte; - - /// bitwise access to register IER - struct { - BITS TMEIE : 1; // bit 0 - BITS FMPIE : 1; // bit 1 - BITS FFIE : 1; // bit 2 - BITS FOVIE : 1; // bit 3 (mismatch with IAR!) - BITS : 3; // 3 bits - BITS WKUIE : 1; // bit 7 - }; // IER bitfield - - /// register CAN_IER reset value - #define sfr_CAN_IER_RESET_VALUE ((uint8_t) 0x00) - - } IER; - - - /** CAN diagnosis register (DGR at 0x5426) */ - union { - - /// bytewise access to DGR - uint8_t byte; - - /// bitwise access to register DGR - struct { - BITS LBKM : 1; // bit 0 - BITS SILM : 1; // bit 1 - BITS SAMP : 1; // bit 2 - BITS RX : 1; // bit 3 - BITS TXM2E : 1; // bit 4 - BITS : 3; // 3 bits - }; // DGR bitfield - - /// register CAN_DGR reset value - #define sfr_CAN_DGR_RESET_VALUE ((uint8_t) 0x0C) - - } DGR; - - - /** CAN page selection register (PSR at 0x5427) */ - union { - - /// bytewise access to PSR - uint8_t byte; - - /// bitwise access to register PSR - struct { - BITS PS : 3; // bits 0-2 - BITS : 5; // 5 bits - }; // PSR bitfield - - /// register CAN_PSR reset value - #define sfr_CAN_PSR_RESET_VALUE ((uint8_t) 0x00) - - } PSR; - - - /** CAN paged register 0 (at 0x5428) */ - union { - - /// Page 0: CAN message control/status register (CAN_MCSR) - union { - - /// bytewise access to MCSR - uint8_t byte; - - /// bitwise access to register MCSR - struct { - BITS TXRQ : 1; // bit 0 - BITS ABRQ : 1; // bit 1 - BITS RQCP : 1; // bit 2 - BITS TXOK : 1; // bit 3 - BITS ALST : 1; // bit 4 - BITS TERR : 1; // bit 5 - BITS : 2; // 2 bits - }; // MCSR bitfield - - /// register CAN_MCSR reset value - #define sfr_CAN_MCSR_RESET_VALUE ((uint8_t) 0x00) - - } MCSR; - - - /// Page 1: CAN message control/status register (CAN_MCSR), see page 0 - - - /// Page 2: CAN filter bank 0 register 1 (CAN_F0R1) - union { - - /// bytewise access to F0R1 - uint8_t byte; - - /// bitwise access to register F0R1 - struct { - BITS FB : 8; // bits 0-7 - }; // F0R1 bitfield - - /// no register reset value - - } F0R1; - - - /// Page 3: CAN filter bank 2 register 1 (CAN_F2R1) - union { - - /// bytewise access to F2R1 - uint8_t byte; - - /// bitwise access to register F2R1 - struct { - BITS FB : 8; // bits 0-7 - }; // F2R1 bitfield - - /// no register reset value - - } F2R1; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F4R1) - union { - - /// bytewise access to F4R1 - uint8_t byte; - - /// bitwise access to register F4R1 - struct { - BITS FB : 8; // bits 0-7 - }; // F4R1 bitfield - - /// no register reset value - - } F4R1; - - - /// Page 5: CAN message control/status register (CAN_MCSR), see page 0 - - - /// Page 6: CAN error status register (CAN_ESR) - union { - - /// bytewise access to ESR - uint8_t byte; - - /// bitwise access to register ESR - struct { - BITS EWGF : 1; // bit 0 - BITS EPVF : 1; // bit 1 - BITS BOFF : 1; // bit 2 - BITS : 1; // 1 bit - BITS LEC : 3; // bits 4..6 - BITS : 1; // 1 bit - }; // ESR bitfield - - /// register CAN_ESR reset value - #define sfr_CAN_ESR_RESET_VALUE ((uint8_t) 0x00) - - } ESR; - - - /// Page 7: CAN mailbox filter match index register (CAN_MFMIR) - union { - - /// bytewise access to MFMIR - uint8_t byte; - - /// bitwise access to register MFMIR - struct { - BITS FMI : 8; // bits 0-7 - }; // MFMIR bitfield - - /// no register reset value - - } MFMIR; - - }; // CAN paged register 0 - - - /** CAN paged register 1 (at 0x5429) */ - union { - - /// Page 0: CAN mailbox data length control register (CAN_MDLCR) - union { - - /// bytewise access to MDLCR - uint8_t byte; - - /// bitwise access to register MDLCR - struct { - BITS DLC : 4; // bits 0-3 - BITS : 3; // 3 bits - BITS TGT : 1; // bit 7 - }; // MDLCR bitfield - - /// no register reset value - - } MDLCR; - - - /// Page 1: CAN mailbox data length control register (CAN_MDLCR), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F0R2) - union { - - /// bytewise access to F0R2 - uint8_t byte; - - /// bitwise access to register F0R2 - struct { - BITS FB : 8; // bits 0-7 - }; // F0R2 bitfield - - /// no register reset value - - } F0R2; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F2R2) - union { - - /// bytewise access to F2R2 - uint8_t byte; - - /// bitwise access to register F2R2 - struct { - BITS FB : 8; // bits 0-7 - }; // F2R2 bitfield - - /// no register reset value - - } F2R2; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F4R2) - union { - - /// bytewise access to F4R2 - uint8_t byte; - - /// bitwise access to register F4R2 - struct { - BITS FB : 8; // bits 0-7 - }; // F4R2 bitfield - - /// no register reset value - - } F4R2; - - - /// Page 5: CAN mailbox data length control register (CAN_MDLCR), see page 0 - - - /// Page 6: CAN error interrupt enable register (CAN_EIER) - union { - - /// bytewise access to EIER - uint8_t byte; - - /// bitwise access to register EIER - struct { - BITS EWGIE : 1; // bit 0 - BITS EPVIE : 1; // bit 1 - BITS BOFIE : 1; // bit 2 - BITS : 1; // 1 bit - BITS LECIE : 1; // bit 4 - BITS : 2; // 2 bits - BITS ERRIE : 1; // bit 7 - }; // EIER bitfield - - /// register CAN_EIER reset value - #define sfr_CAN_EIER_RESET_VALUE ((uint8_t) 0x00) - - } EIER; - - - /// Page 7: CAN mailbox data length control register (CAN_MDLCR), see page 0 - - }; // CAN paged register 1 - - - /** CAN paged register 2 (at 0x542a) */ - union { - - /// Page 0: CAN mailbox identifier register 1 (CAN_MIDR1) - union { - - /// bytewise access to MIDR1 - uint8_t byte; - - /// bitwise access to register MIDR1 - struct { - BITS ID : 5; // bits 0-4 - BITS RTR : 1; // bit 5 - BITS IDE : 1; // bit 6 - BITS : 1; // 1 bit - }; // MIDR1 bitfield - - /// no register reset value - - } MIDR1; - - - /// Page 1: CAN mailbox identifier register 1 (CAN_MIDR1), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F0R3) - union { - - /// bytewise access to F0R3 - uint8_t byte; - - /// bitwise access to register F0R3 - struct { - BITS FB : 8; // bits 0-7 - }; // F0R3 bitfield - - /// no register reset value - - } F0R3; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F2R3) - union { - - /// bytewise access to F2R3 - uint8_t byte; - - /// bitwise access to register F2R3 - struct { - BITS FB : 8; // bits 0-7 - }; // F2R3 bitfield - - /// no register reset value - - } F2R3; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F4R3) - union { - - /// bytewise access to F4R3 - uint8_t byte; - - /// bitwise access to register F4R3 - struct { - BITS FB : 8; // bits 0-7 - }; // F4R3 bitfield - - /// no register reset value - - } F4R3; - - - /// Page 5: CAN mailbox identifier register 1 (CAN_MIDR1), see page 0 - - - /// Page 6:CAN transmit error counter register (CAN_TECR) - union { - - /// bytewise access to TECR - uint8_t byte; - - /// bitwise access to register TECR - struct { - BITS EWGIE : 1; // bit 0 - BITS EPVIE : 1; // bit 1 - BITS BOFIE : 1; // bit 2 - BITS : 1; // 1 bit - BITS LECIE : 1; // bit 4 - BITS : 2; // 2 bits - BITS ERRIE : 1; // bit 7 - }; // TECR bitfield - - /// register CAN_TECR reset value - #define sfr_CAN_TECR_RESET_VALUE ((uint8_t) 0x00) - - } TECR; - - - /// Page 7: CAN mailbox identifier register 1 (CAN_MIDR1), see page 0 - - }; // CAN paged register 2 - - - /** CAN paged register 3 (at 0x542b) */ - union { - - /// Page 0: CAN mailbox identifier register 2 (CAN_MIDR2) - union { - - /// bytewise access to MIDR2 - uint8_t byte; - - /// bitwise access to register MIDR2 - struct { - BITS EXID : 2; // bits 0-1 - BITS ID : 6; // bits 2-7 - }; // MIDR2 bitfield - - /// no register reset value - - } MIDR2; - - - /// Page 1: CAN mailbox identifier register 2 (CAN_MIDR2), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F0R4) - union { - - /// bytewise access to F0R4 - uint8_t byte; - - /// bitwise access to register F0R4 - struct { - BITS FB : 8; // bits 0-7 - }; // F0R4 bitfield - - /// no register reset value - - } F0R4; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F2R4) - union { - - /// bytewise access to F2R4 - uint8_t byte; - - /// bitwise access to register F2R4 - struct { - BITS FB : 8; // bits 0-7 - }; // F2R4 bitfield - - /// no register reset value - - } F2R4; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F4R4) - union { - - /// bytewise access to F4R4 - uint8_t byte; - - /// bitwise access to register F4R4 - struct { - BITS FB : 8; // bits 0-7 - }; // F4R4 bitfield - - /// no register reset value - - } F4R4; - - - /// Page 5: CAN mailbox identifier register 2 (CAN_MIDR2), see page 0 - - - /// Page 6: CAN receive error counter register (CAN_RECR) - union { - - /// bytewise access to RECR - uint8_t byte; - - /// bitwise access to register RECR - struct { - BITS REC : 8; // bits 0-7 - }; // RECR bitfield - - /// register CAN_RECR reset value - #define sfr_CAN_RECR_RESET_VALUE ((uint8_t) 0x00) - - } RECR; - - - /// Page 7: CAN mailbox identifier register 2 (CAN_MIDR2), see page 0 - - }; // CAN paged register 3 - - - /** CAN paged register 4 (0x542c) */ - union { - - /// Page 0: CAN mailbox identifier register 3 (CAN_MIDR3) - union { - - /// bytewise access to MIDR3 - uint8_t byte; - - /// bitwise access to register MIDR3 - struct { - BITS EXID : 8; // bits 0-7 - }; // MIDR3 bitfield - - /// no register reset value - - } MIDR3; - - - /// Page 1: CAN mailbox identifier register 3 (CAN_MIDR3), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F0R5) - union { - - /// bytewise access to F0R5 - uint8_t byte; - - /// bitwise access to register F0R5 - struct { - BITS FB : 8; // bits 0-7 - }; // F0R5 bitfield - - /// no register reset value - - } F0R5; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F2R5) - union { - - /// bytewise access to F2R5 - uint8_t byte; - - /// bitwise access to register F2R5 - struct { - BITS FB : 8; // bits 0-7 - }; // F2R5 bitfield - - /// no register reset value - - } F2R5; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F4R5) - union { - - /// bytewise access to F4R5 - uint8_t byte; - - /// bitwise access to register F4R5 - struct { - BITS FB : 8; // bits 0-7 - }; // F4R5 bitfield - - /// no register reset value - - } F4R5; - - - /// Page 5: CAN mailbox identifier register 3 (CAN_MIDR3), see page 0 - - - /// Page 6: CAN bit timing register 1 (CAN_BTR1) - union { - - /// bytewise access to BTR1 - uint8_t byte; - - /// bitwise access to register BTR1 - struct { - BITS BRP : 6; // bits 0-5 - BITS SJW : 2; // bits 6-7 - }; // BTR1 bitfield - - /// register CAN_BTR1 reset value - #define sfr_CAN_BTR1_RESET_VALUE ((uint8_t) 0x40) - - } BTR1; - - - /// Page 7: CAN mailbox identifier register 3 (CAN_MIDR3), see page 0 - - }; // CAN paged register 4 - - - /** CAN paged register 5 (at 0x542d) */ - union { - - /// Page 0: CAN mailbox identifier register 4 (CAN_MIDR4) - union { - - /// bytewise access to MIDR4 - uint8_t byte; - - /// bitwise access to register MIDR4 - struct { - BITS EXID : 8; // bits 0-7 - }; // MIDR4 bitfield - - /// no register reset value - - } MIDR4; - - - /// Page 1: CAN mailbox identifier register 4 (CAN_MIDR4), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F0R6) - union { - - /// bytewise access to F0R6 - uint8_t byte; - - /// bitwise access to register F0R6 - struct { - BITS FB : 8; // bits 0-7 - }; // F0R6 bitfield - - /// no register reset value - - } F0R6; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F2R6) - union { - - /// bytewise access to F2R6 - uint8_t byte; - - /// bitwise access to register F2R6 - struct { - BITS FB : 8; // bits 0-7 - }; // F2R6 bitfield - - /// no register reset value - - } F2R6; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F4R6) - union { - - /// bytewise access to F4R6 - uint8_t byte; - - /// bitwise access to register F4R6 - struct { - BITS FB : 8; // bits 0-7 - }; // F4R6 bitfield - - /// no register reset value - - } F4R6; - - - /// Page 5: CAN mailbox identifier register 4 (CAN_MIDR4), see page 0 - - - /// Page 6: CAN bit timing register 2 (CAN_BTR2) - union { - - /// bytewise access to BTR2 - uint8_t byte; - - /// bitwise access to register BTR2 - struct { - BITS BS1 : 4; // bits 0-3 - BITS BS2 : 3; // bits 4-6 - BITS CLK : 1; // bit 7 (undocumented in newer UM!) - }; // BTR2 bitfield - - /// register CAN_BTR2 reset value - #define sfr_CAN_BTR2_RESET_VALUE ((uint8_t) 0x23) - - } BTR2; - - - /// Page 7: CAN mailbox identifier register 4 (CAN_MIDR4), see page 0 - - }; // CAN paged register 5 - - - /** CAN paged register 6 (at 0x542e) */ - union { - - /// Page 0: CAN mailbox data register 1 (CAN_MDAR1) - union { - - /// bytewise access to MDAR1 - uint8_t byte; - - /// bitwise access to register MDAR1 - struct { - BITS DATA : 8; // bits 0-7 - }; // MDAR1 bitfield - - /// no register reset value - - } MDAR1; - - - /// Page 1: CAN mailbox data register 1 (CAN_MDAR1), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F0R7) - union { - - /// bytewise access to F0R7 - uint8_t byte; - - /// bitwise access to register F0R7 - struct { - BITS FB : 8; // bits 0-7 - }; // F0R7 bitfield - - /// no register reset value - - } F0R7; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F2R7) - union { - - /// bytewise access to F2R7 - uint8_t byte; - - /// bitwise access to register F2R7 - struct { - BITS FB : 8; // bits 0-7 - }; // F2R7 bitfield - - /// no register reset value - - } F2R7; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F4R7) - union { - - /// bytewise access to F4R7 - uint8_t byte; - - /// bitwise access to register F4R7 - struct { - BITS FB : 8; // bits 0-7 - }; // F4R7 bitfield - - /// no register reset value - - } F4R7; - - - /// Page 5: CAN mailbox data register 1 (CAN_MDAR1), see page 0 - - - /// Page 6: Reserved - - - /// Page 7: CAN mailbox data register 1 (CAN_MDAR1), see page 0 - - }; // CAN paged register 6 - - - /** CAN paged register 7 (at 0x542f) */ - union { - - /// Page 0: CAN mailbox data register 1 (CAN_MDAR2) - union { - - /// bytewise access to MDAR2 - uint8_t byte; - - /// bitwise access to register MDAR2 - struct { - BITS DATA : 8; // bits 0-7 - }; // MDAR2 bitfield - - /// no register reset value - - } MDAR2; - - - /// Page 1: CAN mailbox data register 2 (CAN_MDAR2), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F0R8) - union { - - /// bytewise access to F0R8 - uint8_t byte; - - /// bitwise access to register F0R8 - struct { - BITS FB : 8; // bits 0-7 - }; // F0R8 bitfield - - /// no register reset value - - } F0R8; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F2R8) - union { - - /// bytewise access to F2R8 - uint8_t byte; - - /// bitwise access to register F2R8 - struct { - BITS FB : 8; // bits 0-7 - }; // F2R8 bitfield - - /// no register reset value - - } F2R8; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F4R8) - union { - - /// bytewise access to F4R8 - uint8_t byte; - - /// bitwise access to register F4R8 - struct { - BITS FB : 8; // bits 0-7 - }; // F4R8 bitfield - - /// no register reset value - - } F4R8; - - - /// Page 5: CAN mailbox data register 2 (CAN_MDAR2), see page 0 - - - /// Page 6: Reserved - - - /// Page 7: CAN mailbox data register 2 (CAN_MDAR2), see page 0 - - }; // CAN paged register 7 - - - /** CAN paged register 8 (at 0x5430) */ - union { - - /// Page 0: CAN mailbox data register 1 (CAN_MDAR3) - union { - - /// bytewise access to MDAR3 - uint8_t byte; - - /// bitwise access to register MDAR3 - struct { - BITS DATA : 8; // bits 0-7 - }; // MDAR3 bitfield - - /// no register reset value - - } MDAR3; - - - /// Page 1: CAN mailbox data register 3 (CAN_MDAR3), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F1R1) - union { - - /// bytewise access to F1R1 - uint8_t byte; - - /// bitwise access to register F1R1 - struct { - BITS FB : 8; // bits 0-7 - }; // F1R1 bitfield - - /// no register reset value - - } F1R1; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F3R1) - union { - - /// bytewise access to F3R1 - uint8_t byte; - - /// bitwise access to register F3R1 - struct { - BITS FB : 8; // bits 0-7 - }; // F3R1 bitfield - - /// no register reset value - - } F3R1; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F5R1) - union { - - /// bytewise access to F5R1 - uint8_t byte; - - /// bitwise access to register F5R1 - struct { - BITS FB : 8; // bits 0-7 - }; // F5R1 bitfield - - /// no register reset value - - } F5R1; - - - /// Page 5: CAN mailbox data register 3 (CAN_MDAR3), see page 0 - - - /// Page 6: CAN filter mode register 1 (CAN_FMR1) - union { - - /// bytewise access to FMR1 - uint8_t byte; - - /// bitwise access to register FMR1 - struct { - BITS FML0 : 1; // bit 0 - BITS FMH0 : 1; // bit 1 - BITS FML1 : 1; // bit 2 - BITS FMH1 : 1; // bit 3 - BITS FML2 : 1; // bit 4 - BITS FMH2 : 1; // bit 5 - BITS FML3 : 1; // bit 6 - BITS FMH3 : 1; // bit 7 - }; // FMR1 bitfield - - /// register CAN_FMR1 reset value - #define sfr_CAN_FMR1_RESET_VALUE ((uint8_t) 0x00) - - } FMR1; - - - /// Page 7: CAN mailbox data register 3 (CAN_MDAR3), see page 0 - - }; // CAN paged register 8 - - - /** CAN paged register 9 (at 0x5431) */ - union { - - /// Page 0: CAN mailbox data register 1 (CAN_MDAR4) - union { - - /// bytewise access to MDAR4 - uint8_t byte; - - /// bitwise access to register MDAR4 - struct { - BITS DATA : 8; // bits 0-7 - }; // MDAR4 bitfield - - /// no register reset value - - } MDAR4; - - - /// Page 1: CAN mailbox data register 4 (CAN_MDAR4), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F1R2) - union { - - /// bytewise access to F1R2 - uint8_t byte; - - /// bitwise access to register F1R2 - struct { - BITS FB : 8; // bits 0-7 - }; // F1R2 bitfield - - /// no register reset value - - } F1R2; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F3R2) - union { - - /// bytewise access to F3R2 - uint8_t byte; - - /// bitwise access to register F3R2 - struct { - BITS FB : 8; // bits 0-7 - }; // F3R2 bitfield - - /// no register reset value - - } F3R2; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F5R2) - union { - - /// bytewise access to F5R2 - uint8_t byte; - - /// bitwise access to register F5R2 - struct { - BITS FB : 8; // bits 0-7 - }; // F5R2 bitfield - - /// no register reset value - - } F5R2; - - - /// Page 5: CAN mailbox data register 4 (CAN_MDAR4), see page 0 - - - /// Page 6: CAN filter mode register 2 (CAN_FMR2) - union { - - /// bytewise access to FMR2 - uint8_t byte; - - /// bitwise access to register FMR2 - struct { - BITS FML4 : 1; // bit 0 - BITS FMH4 : 1; // bit 1 - BITS FML5 : 1; // bit 2 - BITS FMH5 : 1; // bit 3 - BITS : 4; // 4 bits - }; // FMR2 bitfield - - /// register CAN_FMR2 reset value - #define sfr_CAN_FMR2_RESET_VALUE ((uint8_t) 0x00) - - } FMR2; - - - /// Page 7: CAN mailbox data register 4 (CAN_MDAR4), see page 0 - - }; // CAN paged register 9 - - - /** CAN paged register A (at 0x5432) */ - union { - - /// Page 0: CAN mailbox data register 1 (CAN_MDAR5) - union { - - /// bytewise access to MDAR5 - uint8_t byte; - - /// bitwise access to register MDAR5 - struct { - BITS DATA : 8; // bits 0-7 - }; // MDAR5 bitfield - - /// no register reset value - - } MDAR5; - - - /// Page 1: CAN mailbox data register 5 (CAN_MDAR5), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F1R3) - union { - - /// bytewise access to F1R3 - uint8_t byte; - - /// bitwise access to register F1R3 - struct { - BITS FB : 8; // bits 0-7 - }; // F1R3 bitfield - - /// no register reset value - - } F1R3; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F3R3) - union { - - /// bytewise access to F3R3 - uint8_t byte; - - /// bitwise access to register F3R3 - struct { - BITS FB : 8; // bits 0-7 - }; // F3R3 bitfield - - /// no register reset value - - } F3R3; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F5R3) - union { - - /// bytewise access to F5R3 - uint8_t byte; - - /// bitwise access to register F5R3 - struct { - BITS FB : 8; // bits 0-7 - }; // F5R3 bitfield - - /// no register reset value - - } F5R3; - - - /// Page 5: CAN mailbox data register 5 (CAN_MDAR5), see page 0 - - - /// Page 6: CAN filter configuration register 1 (CAN_FCR1) - union { - - /// bytewise access to FCR1 - uint8_t byte; - - /// bitwise access to register FCR1 - struct { - BITS FACT0 : 1; // bit 0 - BITS FSC0 : 2; // bits 1-2 - BITS : 1; // 1 bit - BITS FACT1 : 1; // bit 4 - BITS FSC1 : 1; // bit 5-6 - BITS : 1; // 1 bit - }; // FCR1 bitfield - - /// register CAN_FCR1 reset value - #define sfr_CAN_FCR1_RESET_VALUE ((uint8_t) 0x00) - - } FCR1; - - - /// Page 7: CAN mailbox data register 5 (CAN_MDAR5), see page 0 - - }; // CAN paged register A - - - /** CAN paged register B (at 0x5433) */ - union { - - /// Page 0: CAN mailbox data register 1 (CAN_MDAR6) - union { - - /// bytewise access to MDAR6 - uint8_t byte; - - /// bitwise access to register MDAR6 - struct { - BITS DATA : 8; // bits 0-7 - }; // MDAR6 bitfield - - /// no register reset value - - } MDAR6; - - - /// Page 1: CAN mailbox data register 6 (CAN_MDAR6), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F1R4) - union { - - /// bytewise access to F1R4 - uint8_t byte; - - /// bitwise access to register F1R4 - struct { - BITS FB : 8; // bits 0-7 - }; // F1R4 bitfield - - /// no register reset value - - } F1R4; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F3R4) - union { - - /// bytewise access to F3R4 - uint8_t byte; - - /// bitwise access to register F3R4 - struct { - BITS FB : 8; // bits 0-7 - }; // F3R4 bitfield - - /// no register reset value - - } F3R4; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F5R4) - union { - - /// bytewise access to F5R4 - uint8_t byte; - - /// bitwise access to register F5R4 - struct { - BITS FB : 8; // bits 0-7 - }; // F5R4 bitfield - - /// no register reset value - - } F5R4; - - - /// Page 5: CAN mailbox data register 6 (CAN_MDAR6), see page 0 - - - /// Page 6: CAN filter configuration register 2 (CAN_FCR2) - union { - - /// bytewise access to FCR2 - uint8_t byte; - - /// bitwise access to register FCR2 - struct { - BITS FACT2 : 1; // bit 0 - BITS FSC2 : 2; // bit 1-2 - BITS : 1; // 1 bit - BITS FACT3 : 1; // bit 4 - BITS FSC3 : 2; // bit 5-6 - BITS : 1; // 1 bit - }; // FCR2 bitfield - - /// register CAN_FCR2 reset value - #define sfr_CAN_FCR2_RESET_VALUE ((uint8_t) 0x00) - - } FCR2; - - - /// Page 7: CAN mailbox data register 6 (CAN_MDAR6), see page 0 - - }; // CAN paged register B - - - /** CAN paged register C (at 0x5434) */ - union { - - /// Page 0: CAN mailbox data register 7 (CAN_MDAR7) - union { - - /// bytewise access to MDAR7 - uint8_t byte; - - /// bitwise access to register MDAR7 - struct { - BITS DATA : 8; // bits 0-7 - }; // MDAR7 bitfield - - /// no register reset value - - } MDAR7; - - - /// Page 1: CAN mailbox data register 7 (CAN_MDAR7), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F1R5) - union { - - /// bytewise access to F1R5 - uint8_t byte; - - /// bitwise access to register F1R5 - struct { - BITS FB : 8; // bits 0-7 - }; // F1R5 bitfield - - /// no register reset value - - } F1R5; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F3R5) - union { - - /// bytewise access to F3R5 - uint8_t byte; - - /// bitwise access to register F3R5 - struct { - BITS FB : 8; // bits 0-7 - }; // F3R5 bitfield - - /// no register reset value - - } F3R5; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F5R5) - union { - - /// bytewise access to F5R5 - uint8_t byte; - - /// bitwise access to register F5R5 - struct { - BITS FB : 8; // bits 0-7 - }; // F5R5 bitfield - - /// no register reset value - - } F5R5; - - - /// Page 5: CAN mailbox data register 7 (CAN_MDAR7), see page 0 - - - /// Page 6: CAN filter configuration register 3 (CAN_FCR3) - union { - - /// bytewise access to FCR3 - uint8_t byte; - - /// bitwise access to register FCR3 - struct { - BITS FACT4 : 1; // bit 0 - BITS FSC4 : 2; // bit 1-2 - BITS : 1; // 1 bit - BITS FACT5 : 1; // bit 4 - BITS FSC5 : 2; // bit 5-6 - BITS : 1; // 1 bit - }; // FCR3 bitfield - - /// register CAN_FCR3 reset value - #define sfr_CAN_FCR3_RESET_VALUE ((uint8_t) 0x00) - - } FCR3; - - - /// Page 7: CAN mailbox data register 7 (CAN_MDAR7), see page 0 - - }; // CAN paged register C - - - /** CAN paged register D (at 0x5435) */ - union { - - /// Page 0: CAN mailbox data register 1 (CAN_MDAR8) - union { - - /// bytewise access to MDAR8 - uint8_t byte; - - /// bitwise access to register MDAR8 - struct { - BITS DATA : 8; // bits 0-7 - }; // MDAR8 bitfield - - /// no register reset value - - } MDAR8; - - - /// Page 1: CAN mailbox data register 8 (CAN_MDAR8), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F1R6) - union { - - /// bytewise access to F1R6 - uint8_t byte; - - /// bitwise access to register F1R6 - struct { - BITS FB : 8; // bits 0-7 - }; // F1R6 bitfield - - /// no register reset value - - } F1R6; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F3R6) - union { - - /// bytewise access to F3R6 - uint8_t byte; - - /// bitwise access to register F3R6 - struct { - BITS FB : 8; // bits 0-7 - }; // F3R6 bitfield - - /// no register reset value - - } F3R6; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F5R6) - union { - - /// bytewise access to F5R6 - uint8_t byte; - - /// bitwise access to register F5R6 - struct { - BITS FB : 8; // bits 0-7 - }; // F5R6 bitfield - - /// no register reset value - - } F5R6; - - - /// Page 5: CAN mailbox data register 8 (CAN_MDAR8), see page 0 - - - /// Page 6: Reserved - - - /// Page 5: CAN mailbox data register 8 (CAN_MDAR8), see page 0 - - }; // CAN paged register D - - - /** CAN paged register E (at 0x5436) */ - union { - - /// Page 0: CAN mailbox time stamp register low (CAN_MTSRL) - union { - - /// bytewise access to MTSRL - uint8_t byte; - - /// bitwise access to register MTSRL - struct { - BITS TIME : 8; // bits 0-7 - }; // MTSRL bitfield - - /// no register reset value - - } MTSRL; - - - /// Page 1: CAN mailbox time stamp register low (CAN_MTSRL), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F1R7) - union { - - /// bytewise access to F1R7 - uint8_t byte; - - /// bitwise access to register F1R7 - struct { - BITS FB : 8; // bits 0-7 - }; // F1R7 bitfield - - /// no register reset value - - } F1R7; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F3R7) - union { - - /// bytewise access to F3R7 - uint8_t byte; - - /// bitwise access to register F3R7 - struct { - BITS FB : 8; // bits 0-7 - }; // F3R7 bitfield - - /// no register reset value - - } F3R7; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F5R7) - union { - - /// bytewise access to F5R7 - uint8_t byte; - - /// bitwise access to register F5R7 - struct { - BITS FB : 8; // bits 0-7 - }; // F5R7 bitfield - - /// no register reset value - - } F5R7; - - - /// Page 5: CAN mailbox time stamp register low (CAN_MTSRL), see page 0 - - - /// Page 6: Reserved - - - /// Page 7: CAN mailbox time stamp register low (CAN_MTSRL), see page 0 - - }; // CAN paged register E - - - /** CAN paged register F (at 0x5437) */ - union { - - /// page REGF - uint8_t byte; - - - /// Page 0: CAN mailbox time stamp register high (CAN_MTSRH) - union { - - /// bytewise access to MTSRH - uint8_t byte; - - /// bitwise access to register MTSRH - struct { - BITS TIME : 8; // bits 0-7 - }; // MTSRH bitfield - - /// no register reset value - - } MTSRH; - - - /// Page 1: CAN mailbox time stamp register high (CAN_MTSRH), see page 0 - - - /// Page 2: CAN filter bank 0 register 2 (CAN_F1R8) - union { - - /// bytewise access to F1R8 - uint8_t byte; - - /// bitwise access to register F1R8 - struct { - BITS FB : 8; // bits 0-7 - }; // F1R8 bitfield - - /// no register reset value - - } F1R8; - - - /// Page 3: CAN filter bank 2 register 2 (CAN_F3R8) - union { - - /// bytewise access to F3R8 - uint8_t byte; - - /// bitwise access to register F3R8 - struct { - BITS FB : 8; // bits 0-7 - }; // F3R8 bitfield - - /// no register reset value - - } F3R8; - - - /// Page 4: CAN filter bank 4 register 1 (CAN_F5R8) - union { - - /// bytewise access to F5R8 - uint8_t byte; - - /// bitwise access to register F5R8 - struct { - BITS FB : 8; // bits 0-7 - }; // F5R8 bitfield - - /// no register reset value - - } F5R8; - - - /// Page 5: CAN mailbox time stamp register high (CAN_MTSRH), see page 0 - - - /// Page 6: Reserved - - - /// Page 7: CAN mailbox time stamp register high (CAN_MTSRH), see page 0 - - }; // CAN paged register F - -} CAN_t; - -/// access to CAN SFR registers -#define sfr_CAN (*((CAN_t*) 0x5420)) -// undefine local macros -#undef BITS - -// required for C++ -#ifdef __cplusplus - } // extern "C" -#endif - -/*------------------------------------------------------------------------- - END OF MODULE DEFINITION FOR MULTIPLE INLUSION --------------------------------------------------------------------------*/ -#endif // STM8S208RB_H