diff --git a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Include/LPC2103.h b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Include/LPC2103.h index 934ac1f..38d1aa1 100644 --- a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Include/LPC2103.h +++ b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Include/LPC2103.h @@ -34,6 +34,13 @@ #define END_OF_RAM 0x40002000 +/* Interrupts num */ +#define VIC_SW 1 +#define VIC_TIMER0 4 +#define VIC_TIMER1 5 +#define VIC_TIMER2 26 +#define VIC_TIMER3 27 + #ifndef __ASSEMBLER__ #include "LPC2103bits.h" diff --git a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Include/device.h b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Include/device.h index 76dbeb9..6032df6 100644 --- a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Include/device.h +++ b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Include/device.h @@ -34,9 +34,6 @@ extern "C" void abort(void); #define RTOS_TICK_RATE 1000 // Hz -#define VIC_SW 1 -#define VIC_TIMER3 27 - // some handy DEFINES #ifndef FALSE diff --git a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/crt.s b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/crt.s deleted file mode 100644 index 744b0ea..0000000 --- a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/crt.s +++ /dev/null @@ -1,203 +0,0 @@ -//****************************************************************************** -//* -//* FULLNAME: Single-Chip Microcontroller Real-Time Operating System -//* -//* NICKNAME: scmRTOS -//* -//* PROCESSOR: AT91SAM7xxx (Atmel) -//* -//* TOOLKIT: arm-elf-gcc (GNU) -//* -//* PURPOSE: Startup file. -//* -//* Version: 3.10 -//* -//* $Revision: 260 $ -//* $Date:: 2010-01-26 #$ -//* -//* Copyright (c) 2003-2010, Harry E. Zhurov -//* -//* Permission is hereby granted, free of charge, to any person -//* obtaining a copy of this software and associated documentation -//* files (the "Software"), to deal in the Software without restriction, -//* including without limitation the rights to use, copy, modify, merge, -//* publish, distribute, sublicense, and/or sell copies of the Software, -//* and to permit persons to whom the Software is furnished to do so, -//* subject to the following conditions: -//* -//* The above copyright notice and this permission notice shall be included -//* in all copies or substantial portions of the Software. -//* -//* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -//* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -//* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -//* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -//* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH -//* THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -//* -//* ================================================================= -//* See http://scmrtos.sourceforge.net for documentation, latest -//* information, license and contact details. -//* ================================================================= -//* -//****************************************************************************** -//* ARM port by Sergey A. Borshch, Copyright (c) 2007-2010 - -#define MODE_USER 0x10 -#define MODE_FIQ 0x11 -#define MODE_IRQ 0x12 -#define MODE_SVC 0x13 -#define MODE_ABORT 0x17 -#define MODE_UND 0x1B -#define MODE_SYS 0x1F - -#define NIRQ (1<<7) -#define NFIQ (1<<6) -#define THUMB (1<<5) - -#include -#include - .code 32 -/****************************************************************************/ -/* Vector table and reset entry */ -/****************************************************************************/ - .section .vectors,"ax" - .global _start -_start: - LDR PC, ResetAddr /* Reset */ - LDR PC, UndefAddr /* Undefined instruction */ - LDR PC, SWIAddr /* Software interrupt */ - LDR PC, PAbortAddr /* Prefetch abort */ - LDR PC, DAbortAddr /* Data abort */ - NOP /* Reserved */ -#if scmRTOS_CONTEXT_SWITCH_SCHEME == 1 && !defined(GCC_IRQ_PATCH_REQUIRED) - LDR PC, [PC, #-0xF20] /* Read address from AIC */ -#else - LDR PC, IRQAddr /* IRQ interrupt */ -#endif - LDR PC, FIQAddr /* FIQ interrupt */ -ResetAddr: - .word ResetHandler -UndefAddr: - .word UndefHandler -SWIAddr: - .word SWIHandler -PAbortAddr: - .word PAbortHandler -DAbortAddr: - .word DAbortHandler - -#if scmRTOS_CONTEXT_SWITCH_SCHEME == 0 || defined(GCC_IRQ_PATCH_REQUIRED) -IRQAddr: - .word IRQHandler -#endif - -FIQAddr: - .word FIQHandler - .ltorg - -//----------------------------------------------------------------------------- -// -// Reset handler -// program starts here -// - .section .text, "ax" -ResetHandler: -//----------------------------------------------------------------------------- -// Setup stasks - MSR CPSR_c, #MODE_FIQ | NIRQ | NFIQ // Switch to fiq mode, IRQ & FIQ disabled - LDR SP, =__stack_fiq - MSR CPSR_c, #MODE_SVC | NIRQ | NFIQ // Switch to supervisor mode, IRQ & FIQ disabled - LDR SP, =__stack_svc - MSR CPSR_c, #MODE_UND | NIRQ | NFIQ // Switch to undefined mode, IRQ & FIQ disabled - LDR SP, =__stack_und - MSR CPSR_c, #MODE_ABORT | NIRQ | NFIQ // Switch to abort mode, IRQ & FIQ disabled - LDR SP, =__stack_abort - MSR CPSR_c, #MODE_IRQ | NIRQ | NFIQ // Switch to irq mode, IRQ & FIQ disabled - LDR SP, =__stack_irq - MSR CPSR_c, #MODE_SYS | NIRQ | NFIQ // Switch to system mode, IRQ & FIQ disabled - LDR SP, =__stack_sys -//----------------------------------------------------------------------------- -// Setup hardware - LDR R0,=__low_level_init - MOV LR,PC - BX R0 -//----------------------------------------------------------------------------- -// Clear .bss section - LDR R1, =__bss_start - LDR R2, =__bss_end - MOV R3, #0 -bss_clear_loop: - CMP R1, R2 - STRLO R3, [R1], #+4 - BLO bss_clear_loop -//----------------------------------------------------------------------------- -// Copy init values to .data section - LDR R1,=_data_image // data image start - LDR R2,=_data // destination - LDR R3,=_edata // end of destination -data_copy_loop: - CMP R2,R3 - LDRLO R0,[R1],#4 - STRLO R0,[R2],#4 - BLO data_copy_loop -//----------------------------------------------------------------------------- -// Call C++ constructors - LDR R0, =__ctors_start - LDR R1, =__ctors_end -ctor_loop: - CMP R0, R1 - BEQ ctor_end - LDR R2, [R0], #4 - STMFD SP!, {R0,R1} - MOV LR, PC - BX R2 // some constructors can be in THUMB mode - LDMFD SP!, {R0,R1} - B ctor_loop -ctor_end: -//----------------------------------------------------------------------------- -// Call main() with no arguments - MOV R0,#0 - MOV R1,R0 - LDR R2,=main - MOV LR,PC - BX R2 -//----------------------------------------------------------------------------- -// Exit function. Normaly never reach here - .section .text.weakExitFunction, "ax" - .global ExitFunction - .weak ExitFunction -ExitFunction: - B ExitFunction - -//----------------------------------------------------------------------------- -// Default exeptions handlers - .section .text.weakFIQHandler, "ax" - .weak FIQHandler -FIQHandler: - B FIQHandler - - .section .text.weakUndefHandler, "ax" - .weak UndefHandler -UndefHandler: - B UndefHandler - - .section .text.weakSWIHandler, "ax" - .weak SWIHandler -SWIHandler: - B SWIHandler - - .section .text.weakPAbortHandler, "ax" - .weak PAbortHandler -PAbortHandler: - B PAbortHandler - - .section .text.weakDAbortHandler, "ax" - .weak DAbortHandler -DAbortHandler: - B DAbortHandler - - .ltorg - - diff --git a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/scmRTOS_CONFIG.h b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/scmRTOS_CONFIG.h index 9b78993..141478c 100644 --- a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/scmRTOS_CONFIG.h +++ b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/scmRTOS_CONFIG.h @@ -111,7 +111,7 @@ typedef word TTimeout; // interrupt. See documentation fo details. // // -#define scmRTOS_CONTEXT_SWITCH_SCHEME 1 +#define scmRTOS_CONTEXT_SWITCH_SCHEME 0 //----------------------------------------------------------------------------- // diff --git a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/scmRTOS_TARGET_CFG.h b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/scmRTOS_TARGET_CFG.h index c8a1d94..41b6a15 100644 --- a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/scmRTOS_TARGET_CFG.h +++ b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Src/scmRTOS_TARGET_CFG.h @@ -60,13 +60,13 @@ // // System Timer stuff // -// TIMER3 used as System timer +// TIMER0 used as System timer // -#define SYSTEM_TIMER_INT VIC_TIMER3 +#define SYSTEM_TIMER_INT VIC_TIMER0 -#define RESET_SYSTIMER_INT() do { T3IR = T3IR; } while(0) -#define LOCK_SYSTEM_TIMER() do { T3MCR &= ~TMCR_MR0_I; } while(0) -#define UNLOCK_SYSTEM_TIMER() do { T3MCR |= TMCR_MR0_I; } while(0) +#define RESET_SYSTIMER_INT() do { T0IR = T0IR; } while(0) +#define LOCK_SYSTEM_TIMER() do { T0MCR &= ~TMCR_MR0_I; } while(0) +#define UNLOCK_SYSTEM_TIMER() do { T0MCR |= TMCR_MR0_I; } while(0) //----------------------------------------------------------------------------- diff --git a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Startup/system.cpp b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Startup/system.cpp index 1b02db7..9c101d0 100644 --- a/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Startup/system.cpp +++ b/Samples/ARM7/LPC2xxx/GCC4.x/1-EventFlag/Startup/system.cpp @@ -8,60 +8,71 @@ extern "C" void sysInit(void); void sysInit(void) { // lowInit(); // setup clocks and processor port pins - // setup the parallel port pin - PINSEL0 = 0x00000000; - PINSEL1 = 0x00000000; + // setup the parallel port pin + PINSEL0 = 0x00000000; + PINSEL1 = 0x00000000; #if (USE_FIO == 1) - SCS |= 0x01; // Enable Fast GPIO - FIO0MASK = 0x00000000; - FIO0SET = 0x00000000; //Initialize pins to high level - FIO0CLR = 0xFFFFFFFF; //Initialize pins to low level - FIO0DIR = 0x00000000; //Set pin direction + SCS |= 0x01; // Enable Fast GPIO + FIO0MASK = 0x00000000; + FIO0SET = 0x00000000; //Initialize pins to high level + FIO0CLR = 0xFFFFFFFF; //Initialize pins to low level + FIO0DIR = 0x00000000; //Set pin direction #else - IOSET = 0x00000000; //Initialize pins to high level - IOCLR = 0xFFFFFFFF; //Initialize pins to low level - IODIR = 0x00000000; //Set pin direction + IOSET = 0x00000000; //Initialize pins to high level + IOCLR = 0xFFFFFFFF; //Initialize pins to low level + IODIR = 0x00000000; //Set pin direction #endif - // setup & enable the MAM - MAMTIM = MAMTIM_CYCLES; - MAMCR = MAMCR_FULL; + // setup & enable the MAM + MAMTIM = MAMTIM_CYCLES; + MAMCR = MAMCR_FULL; - // set the peripheral bus speed - // value computed from config.h - VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed + // set the peripheral bus speed + // value computed from config.h + VPBDIV = VPBDIV_VALUE; // set the peripheral bus clock speed - // set the interrupt controller defaults + // set the interrupt controller defaults #if defined(RAM_RUN) - MEMMAP = MEMMAP_SRAM; // map interrupt vectors space into SRAM + MEMMAP = MEMMAP_SRAM; // map interrupt vectors space into SRAM #elif defined(ROM_RUN) - MEMMAP = MEMMAP_FLASH; // map interrupt vectors space into FLASH + MEMMAP = MEMMAP_FLASH; // map interrupt vectors space into FLASH #else #error RUN_MODE not defined! #endif - VICIntEnClear = 0xFFFFFFFF; // clear all interrupts - VICIntSelect = 0x00000000; // clear all FIQ selections - VICDefVectAddr = (uint32_t)reset; // point unvectored IRQs to reset() - - VICVectAddr0 = (unsigned int)0; /* Set the vector address */ - VICVectAddr1 = (unsigned int)0; /* Set the vector address */ - VICVectAddr2 = (unsigned int)0; /* Set the vector address */ - VICVectAddr3 = (unsigned int)0; /* Set the vector address */ - VICVectAddr4 = (unsigned int)0; /* Set the vector address */ - VICVectAddr5 = (unsigned int)0; /* Set the vector address */ - VICVectAddr6 = (unsigned int)0; /* Set the vector address */ - VICVectAddr7 = (unsigned int)0; /* Set the vector address */ - VICVectAddr8 = (unsigned int)0; /* Set the vector address */ - VICVectAddr9 = (unsigned int)0; /* Set the vector address */ - VICVectAddr10 = (unsigned int)0; /* Set the vector address */ - VICVectAddr11 = (unsigned int)0; /* Set the vector address */ - VICVectAddr12 = (unsigned int)0; /* Set the vector address */ - VICVectAddr13 = (unsigned int)0; /* Set the vector address */ - //VICVectAddr14 = (unsigned int)0; /* Set the vector address */ - //VICVectAddr15 = (unsigned int)0; /* Set the vector address */ + VICIntEnClear = 0xFFFFFFFF; // clear all interrupts + VICIntSelect = 0x00000000; // clear all FIQ selections + VICDefVectAddr = (uint32_t)reset; // point unvectored IRQs to reset() + + VICVectAddr0 = (unsigned int)0; /* Set the vector address */ + VICVectAddr1 = (unsigned int)0; /* Set the vector address */ + VICVectAddr2 = (unsigned int)0; /* Set the vector address */ + VICVectAddr3 = (unsigned int)0; /* Set the vector address */ + VICVectAddr4 = (unsigned int)0; /* Set the vector address */ + VICVectAddr5 = (unsigned int)0; /* Set the vector address */ + VICVectAddr6 = (unsigned int)0; /* Set the vector address */ + VICVectAddr7 = (unsigned int)0; /* Set the vector address */ + VICVectAddr8 = (unsigned int)0; /* Set the vector address */ + VICVectAddr9 = (unsigned int)0; /* Set the vector address */ + VICVectAddr10 = (unsigned int)0; /* Set the vector address */ + VICVectAddr11 = (unsigned int)0; /* Set the vector address */ + VICVectAddr12 = (unsigned int)0; /* Set the vector address */ + VICVectAddr13 = (unsigned int)0; /* Set the vector address */ + VICVectAddr14 = (unsigned int)0; /* Set the vector address */ + VICVectAddr15 = (unsigned int)0; /* Set the vector address */ + +// *************************************************************************** +// ** TIMER0 +// *************************************************************************** +// RTOS system timer + T0IR = 0x000000FF; // clear int requests + T0TCR = (1<<1); // reset timer + T0PR = 0; + T0MR0 = PCLK / RTOS_TICK_RATE; // int at TICK_RATE + T0MCR = TMCR_MR0_I | TMCR_MR0_R; + T0TCR = (1<<0); // CE = 1, enable timer // Set system timer interrupt vector with little bit higher priority than context switcher VICVectAddr14 = (dword)OS::SystemTimer_ISR; @@ -79,16 +90,6 @@ void sysInit(void) VICVectAddr = 0; // Reset VIC logic -// *************************************************************************** -// ** TIMER3 -// *************************************************************************** -// RTOS system timer - T3IR = 0x000000FF; // clear int requests - T3TCR = (1<<0); // CE = 1, enable timer - T3PR = 0; - - T3MR0 = PCLK / RTOS_TICK_RATE; // int at TICK_RATE - T3MCR = TMCR_MR0_I | TMCR_MR0_R; }