Permalink
Browse files

Merge branches 'next/generic', 'next/alchemy', 'next/bcm63xx', 'next/…

…cavium', 'next/jz4740', 'next/lantiq', 'next/loongson1b' and 'next/netlogic' into mips-for-linux-next
  • Loading branch information...
9 parents 28a33cb + 71a1c77 + 6c2be5c + 2f74b77 + b59b284 + f9c9aff + 6cd3c7e + 9afd408 + 7e6507a commit 68d8848567ef03eb2c2303173934428d0bf0a531 @ralfbaechle ralfbaechle committed Jul 25, 2012
Showing with 8,102 additions and 2,217 deletions.
  1. +30 −0 Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
  2. +49 −0 Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
  3. +34 −0 Documentation/devicetree/bindings/i2c/cavium-i2c.txt
  4. +126 −0 Documentation/devicetree/bindings/mips/cavium/bootbus.txt
  5. +26 −0 Documentation/devicetree/bindings/mips/cavium/ciu.txt
  6. +27 −0 Documentation/devicetree/bindings/mips/cavium/ciu2.txt
  7. +21 −0 Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
  8. +46 −0 Documentation/devicetree/bindings/mips/cavium/uctl.txt
  9. +27 −0 Documentation/devicetree/bindings/net/cavium-mdio.txt
  10. +39 −0 Documentation/devicetree/bindings/net/cavium-mix.txt
  11. +98 −0 Documentation/devicetree/bindings/net/cavium-pip.txt
  12. +19 −0 Documentation/devicetree/bindings/serial/cavium-uart.txt
  13. +1 −0 arch/mips/Kbuild.platforms
  14. +37 −1 arch/mips/Kconfig
  15. +2 −2 arch/mips/alchemy/board-mtx1.c
  16. +4 −6 arch/mips/alchemy/common/platform.c
  17. +1 −1 arch/mips/alchemy/devboards/Makefile
  18. +1 −4 arch/mips/alchemy/devboards/bcsr.c
  19. +2 −2 arch/mips/alchemy/devboards/pb1100.c
  20. +2 −2 arch/mips/alchemy/devboards/pb1500.c
  21. +30 −0 arch/mips/alchemy/devboards/platform.c
  22. +0 −69 arch/mips/alchemy/devboards/prom.c
  23. +4 −0 arch/mips/bcm63xx/Kconfig
  24. +2 −1 arch/mips/bcm63xx/Makefile
  25. +58 −49 arch/mips/bcm63xx/boards/board_bcm963xx.c
  26. +21 −5 arch/mips/bcm63xx/clk.c
  27. +55 −8 arch/mips/bcm63xx/cpu.c
  28. +1 −1 arch/mips/bcm63xx/dev-dsp.c
  29. +123 −0 arch/mips/bcm63xx/dev-flash.c
  30. +40 −0 arch/mips/bcm63xx/dev-rng.c
  31. +119 −0 arch/mips/bcm63xx/dev-spi.c
  32. +1 −1 arch/mips/bcm63xx/dev-wdt.c
  33. +21 −0 arch/mips/bcm63xx/irq.c
  34. +3 −1 arch/mips/bcm63xx/prom.c
  35. +10 −3 arch/mips/bcm63xx/setup.c
  36. +4 −0 arch/mips/boot/compressed/Makefile
  37. +5 −0 arch/mips/boot/compressed/uart-16550.c
  38. +2 −0 arch/mips/cavium-octeon/.gitignore
  39. +16 −0 arch/mips/cavium-octeon/Makefile
  40. +0 −183 arch/mips/cavium-octeon/executive/cvmx-fpa.c
  41. +0 −243 arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
  42. +314 −85 arch/mips/cavium-octeon/octeon-irq.c
  43. +12 −4 arch/mips/cavium-octeon/octeon-memcpy.S
  44. +522 −177 arch/mips/cavium-octeon/octeon-platform.c
  45. +571 −0 arch/mips/cavium-octeon/octeon_3xxx.dts
  46. +625 −0 arch/mips/cavium-octeon/octeon_68xx.dts
  47. +53 −81 arch/mips/cavium-octeon/serial.c
  48. +45 −0 arch/mips/cavium-octeon/setup.c
  49. +109 −0 arch/mips/configs/ls1b_defconfig
  50. +4 −0 arch/mips/configs/nlm_xlr_defconfig
  51. +1 −1 arch/mips/dec/prom/memory.c
  52. +2 −1 arch/mips/include/asm/cpu.h
  53. +140 −10 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  54. +12 −0 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
  55. +89 −0 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
  56. +2 −0 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
  57. +8 −0 arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
  58. +268 −18 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  59. +1 −0 arch/mips/include/asm/mach-bcm63xx/ioremap.h
  60. +5 −40 arch/mips/include/asm/mach-cavium-octeon/irq.h
  61. +4 −0 arch/mips/include/asm/mach-jz4740/jz4740_nand.h
  62. +2 −1 arch/mips/include/asm/mach-loongson/loongson.h
  63. +73 −0 arch/mips/include/asm/mach-loongson1/irq.h
  64. +44 −0 arch/mips/include/asm/mach-loongson1/loongson1.h
  65. +23 −0 arch/mips/include/asm/mach-loongson1/platform.h
  66. +24 −0 arch/mips/include/asm/mach-loongson1/prom.h
  67. +33 −0 arch/mips/include/asm/mach-loongson1/regs-clk.h
  68. +22 −0 arch/mips/include/asm/mach-loongson1/regs-wdt.h
  69. +25 −0 arch/mips/include/asm/mach-loongson1/war.h
  70. +0 −1 arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
  71. +1 −1 arch/mips/include/asm/mach-tx49xx/mangle-port.h
  72. +13 −0 arch/mips/include/asm/mipsmtregs.h
  73. +2 −0 arch/mips/include/asm/module.h
  74. +3 −1 arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
  75. +4 −1 arch/mips/include/asm/netlogic/xlp-hal/iomap.h
  76. +76 −0 arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
  77. +4 −0 arch/mips/include/asm/netlogic/xlp-hal/pic.h
  78. +64 −0 arch/mips/include/asm/netlogic/xlp-hal/usb.h
  79. +15 −2 arch/mips/include/asm/netlogic/xlp-hal/xlp.h
  80. +104 −0 arch/mips/include/asm/netlogic/xlr/bridge.h
  81. +55 −0 arch/mips/include/asm/netlogic/xlr/flash.h
  82. +30 −29 arch/mips/include/asm/netlogic/xlr/gpio.h
  83. +0 −64 arch/mips/include/asm/octeon/cvmx-helper-fpa.h
  84. +0 −2 arch/mips/include/asm/octeon/cvmx-helper.h
  85. +0 −5 arch/mips/include/asm/octeon/octeon.h
  86. +0 −3 arch/mips/include/asm/prom.h
  87. +6 −0 arch/mips/include/asm/smtc.h
  88. +3 −3 arch/mips/include/asm/uaccess.h
  89. +51 −49 arch/mips/include/asm/uasm.h
  90. +1 −0 arch/mips/jz4740/board-qi_lb60.c
  91. +19 −1 arch/mips/jz4740/platform.c
  92. +44 −5 arch/mips/jz4740/reset.c
  93. +156 −143 arch/mips/kernel/cpu-probe.c
  94. +5 −0 arch/mips/kernel/perf_event_mipsxx.c
  95. +0 −29 arch/mips/kernel/prom.c
  96. +3 −1 arch/mips/kernel/smp.c
  97. +68 −8 arch/mips/kernel/smtc.c
  98. +1 −0 arch/mips/kernel/traps.c
  99. +1 −1 arch/mips/lib/Makefile
  100. +0 −451 arch/mips/lib/memcpy-inatomic.S
  101. +11 −0 arch/mips/lib/memcpy.S
  102. +21 −0 arch/mips/loongson1/Kconfig
  103. +11 −0 arch/mips/loongson1/Makefile
  104. +7 −0 arch/mips/loongson1/Platform
  105. +5 −0 arch/mips/loongson1/common/Makefile
  106. +165 −0 arch/mips/loongson1/common/clock.c
  107. +147 −0 arch/mips/loongson1/common/irq.c
  108. +124 −0 arch/mips/loongson1/common/platform.c
  109. +87 −0 arch/mips/loongson1/common/prom.c
  110. +45 −0 arch/mips/loongson1/common/reset.c
  111. +29 −0 arch/mips/loongson1/common/setup.c
  112. +5 −0 arch/mips/loongson1/ls1b/Makefile
  113. +33 −0 arch/mips/loongson1/ls1b/board.c
  114. +30 −32 arch/mips/mm/uasm.c
  115. +1 −1 arch/mips/netlogic/common/earlycons.c
  116. +102 −55 arch/mips/netlogic/common/smpboot.S
  117. +2 −0 arch/mips/netlogic/xlp/Makefile
  118. +52 −0 arch/mips/netlogic/xlp/nlm_hal.c
  119. +34 −0 arch/mips/netlogic/xlp/of.c
  120. +1 −1 arch/mips/netlogic/xlp/platform.c
  121. +16 −0 arch/mips/netlogic/xlp/setup.c
  122. +124 −0 arch/mips/netlogic/xlp/usb-init.c
  123. +1 −1 arch/mips/netlogic/xlr/Makefile
  124. +220 −0 arch/mips/netlogic/xlr/platform-flash.c
  125. +140 −0 arch/mips/netlogic/xlr/platform.c
  126. +1 −1 arch/mips/netlogic/xlr/setup.c
  127. +1 −0 arch/mips/oprofile/common.c
  128. +4 −6 arch/mips/oprofile/op_model_mipsxx.c
  129. +1 −0 arch/mips/pci/Makefile
  130. +4 −4 arch/mips/pci/fixup-cobalt.c
  131. +14 −0 arch/mips/pci/fixup-malta.c
  132. +1 −1 arch/mips/pci/fixup-rc32434.c
  133. +62 −1 arch/mips/pci/ops-bcm63xx.c
  134. +127 −6 arch/mips/pci/pci-bcm63xx.c
  135. +5 −0 arch/mips/pci/pci-bcm63xx.h
  136. +248 −0 arch/mips/pci/pci-xlp.c
  137. +0 −4 arch/mips/pci/pci-xlr.c
  138. +2 −2 arch/mips/pnx833x/stb22x/board.c
  139. +3 −3 arch/mips/txx9/generic/pci.c
  140. +5 −7 arch/mips/txx9/generic/setup.c
  141. +1 −1 arch/mips/txx9/generic/setup_tx4939.c
  142. +5 −6 arch/mips/txx9/rbtx4939/setup.c
  143. +14 −0 drivers/char/hw_random/Kconfig
  144. +1 −0 drivers/char/hw_random/Makefile
  145. +175 −0 drivers/char/hw_random/bcm63xx-rng.c
  146. +49 −43 drivers/i2c/busses/i2c-octeon.c
  147. +192 −36 drivers/mtd/nand/jz4740_nand.c
  148. +207 −105 drivers/net/ethernet/octeon/octeon_mgmt.c
  149. +58 −34 drivers/net/phy/mdio-octeon.c
  150. +9 −0 drivers/spi/Kconfig
  151. +1 −0 drivers/spi/Makefile
  152. +469 −0 drivers/spi/spi-falcon.c
  153. +15 −13 drivers/staging/octeon/ethernet-mdio.c
  154. +99 −54 drivers/staging/octeon/ethernet.c
  155. +3 −0 drivers/staging/octeon/octeon-ethernet.h
  156. +8 −0 include/linux/libfdt.h
  157. +13 −0 include/linux/libfdt_env.h
  158. +6 −0 lib/Kconfig
  159. +5 −0 lib/Makefile
  160. +2 −0 lib/fdt.c
  161. +2 −0 lib/fdt_ro.c
  162. +2 −0 lib/fdt_rw.c
  163. +2 −0 lib/fdt_strerror.c
  164. +2 −0 lib/fdt_sw.c
  165. +2 −0 lib/fdt_wip.c
@@ -0,0 +1,30 @@
+* Compact Flash
+
+The Cavium Compact Flash device is connected to the Octeon Boot Bus,
+and is thus a child of the Boot Bus device. It can read and write
+industry standard compact flash devices.
+
+Properties:
+- compatible: "cavium,ebt3000-compact-flash";
+
+ Compatibility with many Cavium evaluation boards.
+
+- reg: The base address of the the CF chip select banks. Depending on
+ the device configuration, there may be one or two banks.
+
+- cavium,bus-width: The width of the connection to the CF devices. Valid
+ values are 8 and 16.
+
+- cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
+
+- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
+ to this device.
+
+Example:
+ compact-flash@5,0 {
+ compatible = "cavium,ebt3000-compact-flash";
+ reg = <5 0 0x10000>, <6 0 0x10000>;
+ cavium,bus-width = <16>;
+ cavium,true-ide;
+ cavium,dma-engine-handle = <&dma0>;
+ };
@@ -0,0 +1,49 @@
+* General Purpose Input Output (GPIO) bus.
+
+Properties:
+- compatible: "cavium,octeon-3860-gpio"
+
+ Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the GPIO unit's register bank.
+
+- gpio-controller: This is a GPIO controller.
+
+- #gpio-cells: Must be <2>. The first cell is the GPIO pin.
+
+- interrupt-controller: The GPIO controller is also an interrupt
+ controller, many of its pins may be configured as an interrupt
+ source.
+
+- #interrupt-cells: Must be <2>. The first cell is the GPIO pin
+ connected to the interrupt source. The second cell is the interrupt
+ triggering protocol and may have one of four values:
+ 1 - edge triggered on the rising edge.
+ 2 - edge triggered on the falling edge
+ 4 - level triggered active high.
+ 8 - level triggered active low.
+
+- interrupts: Interrupt routing for each pin.
+
+Example:
+
+ gpio-controller@1070000000800 {
+ #gpio-cells = <2>;
+ compatible = "cavium,octeon-3860-gpio";
+ reg = <0x10700 0x00000800 0x0 0x100>;
+ gpio-controller;
+ /* Interrupts are specified by two parts:
+ * 1) GPIO pin number (0..15)
+ * 2) Triggering (1 - edge rising
+ * 2 - edge falling
+ * 4 - level active high
+ * 8 - level active low)
+ */
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ /* The GPIO pin connect to 16 consecutive CUI bits */
+ interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
+ <0 20>, <0 21>, <0 22>, <0 23>,
+ <0 24>, <0 25>, <0 26>, <0 27>,
+ <0 28>, <0 29>, <0 30>, <0 31>;
+ };
@@ -0,0 +1,34 @@
+* Two Wire Serial Interface (TWSI) / I2C
+
+- compatible: "cavium,octeon-3860-twsi"
+
+ Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the TWSI/I2C bus controller register bank.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>. I2C addresses have no size component.
+
+- interrupts: A single interrupt specifier.
+
+- clock-frequency: The I2C bus clock rate in Hz.
+
+Example:
+ twsi0: i2c@1180000001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cavium,octeon-3860-twsi";
+ reg = <0x11800 0x00001000 0x0 0x200>;
+ interrupts = <0 45>;
+ clock-frequency = <100000>;
+
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
+ tmp@4c {
+ compatible = "ti,tmp421";
+ reg = <0x4c>;
+ };
+ };
@@ -0,0 +1,126 @@
+* Boot Bus
+
+The Octeon Boot Bus is a configurable parallel bus with 8 chip
+selects. Each chip select is independently configurable.
+
+Properties:
+- compatible: "cavium,octeon-3860-bootbus"
+
+ Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the Boot Bus' register bank.
+
+- #address-cells: Must be <2>. The first cell is the chip select
+ within the bootbus. The second cell is the offset from the chip select.
+
+- #size-cells: Must be <1>.
+
+- ranges: There must be one one triplet of (child-bus-address,
+ parent-bus-address, length) for each active chip select. If the
+ length element for any triplet is zero, the chip select is disabled,
+ making it inactive.
+
+The configuration parameters for each chip select are stored in child
+nodes.
+
+Configuration Properties:
+- compatible: "cavium,octeon-3860-bootbus-config"
+
+- cavium,cs-index: A single cell indicating the chip select that
+ corresponds to this configuration.
+
+- cavium,t-adr: A cell specifying the ADR timing (in nS).
+
+- cavium,t-ce: A cell specifying the CE timing (in nS).
+
+- cavium,t-oe: A cell specifying the OE timing (in nS).
+
+- cavium,t-we: A cell specifying the WE timing (in nS).
+
+- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
+
+- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
+
+- cavium,t-pause: A cell specifying the PAUSE timing (in nS).
+
+- cavium,t-wait: A cell specifying the WAIT timing (in nS).
+
+- cavium,t-page: A cell specifying the PAGE timing (in nS).
+
+- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
+
+- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
+ = 2 bytes, 2 = 4 bytes, 3 = 8 bytes).
+
+- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected.
+
+- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected.
+
+- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of
+ the bus for this chip select.
+
+- cavium,ale-mode: Optional. If present, ALE mode is selected.
+
+- cavium,sam-mode: Optional. If present, SAM mode is selected.
+
+- cavium,or-mode: Optional. If present, OR mode is selected.
+
+Example:
+ bootbus: bootbus@1180000000000 {
+ compatible = "cavium,octeon-3860-bootbus";
+ reg = <0x11800 0x00000000 0x0 0x200>;
+ /* The chip select number and offset */
+ #address-cells = <2>;
+ /* The size of the chip select region */
+ #size-cells = <1>;
+ ranges = <0 0 0x0 0x1f400000 0xc00000>,
+ <1 0 0x10000 0x30000000 0>,
+ <2 0 0x10000 0x40000000 0>,
+ <3 0 0x10000 0x50000000 0>,
+ <4 0 0x0 0x1d020000 0x10000>,
+ <5 0 0x0 0x1d040000 0x10000>,
+ <6 0 0x0 0x1d050000 0x10000>,
+ <7 0 0x10000 0x90000000 0>;
+
+ cavium,cs-config@0 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <0>;
+ cavium,t-adr = <20>;
+ cavium,t-ce = <60>;
+ cavium,t-oe = <60>;
+ cavium,t-we = <45>;
+ cavium,t-rd-hld = <35>;
+ cavium,t-wr-hld = <45>;
+ cavium,t-pause = <0>;
+ cavium,t-wait = <0>;
+ cavium,t-page = <35>;
+ cavium,t-rd-dly = <0>;
+
+ cavium,pages = <0>;
+ cavium,bus-width = <8>;
+ };
+ .
+ .
+ .
+ cavium,cs-config@6 {
+ compatible = "cavium,octeon-3860-bootbus-config";
+ cavium,cs-index = <6>;
+ cavium,t-adr = <5>;
+ cavium,t-ce = <300>;
+ cavium,t-oe = <270>;
+ cavium,t-we = <150>;
+ cavium,t-rd-hld = <100>;
+ cavium,t-wr-hld = <70>;
+ cavium,t-pause = <0>;
+ cavium,t-wait = <0>;
+ cavium,t-page = <320>;
+ cavium,t-rd-dly = <0>;
+
+ cavium,pages = <0>;
+ cavium,wait-mode;
+ cavium,bus-width = <16>;
+ };
+ .
+ .
+ .
+ };
@@ -0,0 +1,26 @@
+* Central Interrupt Unit
+
+Properties:
+- compatible: "cavium,octeon-3860-ciu"
+
+ Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.
+
+- interrupt-controller: This is an interrupt controller.
+
+- reg: The base address of the CIU's register bank.
+
+- #interrupt-cells: Must be <2>. The first cell is the bank within
+ the CIU and may have a value of 0 or 1. The second cell is the bit
+ within the bank and may have a value between 0 and 63.
+
+Example:
+ interrupt-controller@1070000000000 {
+ compatible = "cavium,octeon-3860-ciu";
+ interrupt-controller;
+ /* Interrupts are specified by two parts:
+ * 1) Controller register (0 or 1)
+ * 2) Bit within the register (0..63)
+ */
+ #interrupt-cells = <2>;
+ reg = <0x10700 0x00000000 0x0 0x7000>;
+ };
@@ -0,0 +1,27 @@
+* Central Interrupt Unit
+
+Properties:
+- compatible: "cavium,octeon-6880-ciu2"
+
+ Compatibility with 68XX SOCs.
+
+- interrupt-controller: This is an interrupt controller.
+
+- reg: The base address of the CIU's register bank.
+
+- #interrupt-cells: Must be <2>. The first cell is the bank within
+ the CIU and may have a value between 0 and 63. The second cell is
+ the bit within the bank and may also have a value between 0 and 63.
+
+Example:
+ interrupt-controller@1070100000000 {
+ compatible = "cavium,octeon-6880-ciu2";
+ interrupt-controller;
+ /* Interrupts are specified by two parts:
+ * 1) Controller register (0..63)
+ * 2) Bit within the register (0..63)
+ */
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x10701 0x00000000 0x0 0x4000000>;
+ };
@@ -0,0 +1,21 @@
+* DMA Engine.
+
+The Octeon DMA Engine transfers between the Boot Bus and main memory.
+The DMA Engine will be refered to by phandle by any device that is
+connected to it.
+
+Properties:
+- compatible: "cavium,octeon-5750-bootbus-dma"
+
+ Compatibility with all cn52XX, cn56XX and cn6XXX SOCs.
+
+- reg: The base address of the DMA Engine's register bank.
+
+- interrupts: A single interrupt specifier.
+
+Example:
+ dma0: dma-engine@1180000000100 {
+ compatible = "cavium,octeon-5750-bootbus-dma";
+ reg = <0x11800 0x00000100 0x0 0x8>;
+ interrupts = <0 63>;
+ };
@@ -0,0 +1,46 @@
+* UCTL USB controller glue
+
+Properties:
+- compatible: "cavium,octeon-6335-uctl"
+
+ Compatibility with all cn6XXX SOCs.
+
+- reg: The base address of the UCTL register bank.
+
+- #address-cells: Must be <2>.
+
+- #size-cells: Must be <2>.
+
+- ranges: Empty to signify direct mapping of the children.
+
+- refclk-frequency: A single cell containing the reference clock
+ frequency in Hz.
+
+- refclk-type: A string describing the reference clock connection
+ either "crystal" or "external".
+
+Example:
+ uctl@118006f000000 {
+ compatible = "cavium,octeon-6335-uctl";
+ reg = <0x11800 0x6f000000 0x0 0x100>;
+ ranges; /* Direct mapping */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ /* 12MHz, 24MHz and 48MHz allowed */
+ refclk-frequency = <24000000>;
+ /* Either "crystal" or "external" */
+ refclk-type = "crystal";
+
+ ehci@16f0000000000 {
+ compatible = "cavium,octeon-6335-ehci","usb-ehci";
+ reg = <0x16f00 0x00000000 0x0 0x100>;
+ interrupts = <0 56>;
+ big-endian-regs;
+ };
+ ohci@16f0000000400 {
+ compatible = "cavium,octeon-6335-ohci","usb-ohci";
+ reg = <0x16f00 0x00000400 0x0 0x100>;
+ interrupts = <0 56>;
+ big-endian-regs;
+ };
+ };
@@ -0,0 +1,27 @@
+* System Management Interface (SMI) / MDIO
+
+Properties:
+- compatible: "cavium,octeon-3860-mdio"
+
+ Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the MDIO bus controller register bank.
+
+- #address-cells: Must be <1>.
+
+- #size-cells: Must be <0>. MDIO addresses have no size component.
+
+Typically an MDIO bus might have several children.
+
+Example:
+ mdio@1180000001800 {
+ compatible = "cavium,octeon-3860-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11800 0x00001800 0x0 0x40>;
+
+ ethernet-phy@0 {
+ ...
+ reg = <0>;
+ };
+ };
Oops, something went wrong.

0 comments on commit 68d8848

Please sign in to comment.