diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 1025647..28e5c01 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -32,8 +32,16 @@ jobs: runs-on: ubuntu-24.04 steps: - uses: actions/checkout@v4 - - name: Install KiCad CLI + - name: Install KiCad 8 CLI run: | + # Ubuntu 24.04 ships KiCad 7.0.11 in the default repos, which + # lacks `kicad-cli sch erc` and `kicad-cli pcb drc` (added in + # KiCad 8.0). Pull KiCad 8 from the official kicad-developers + # PPA (ppa:kicad/kicad-8.0-releases) so the ERC/DRC commands + # below resolve. Sail rev-A KiCad project files declare KiCad + # 8 sexpr versions (20231120 / 20240108) and KiCad 7 cannot + # parse them. + sudo add-apt-repository --yes ppa:kicad/kicad-8.0-releases sudo apt-get update sudo apt-get install -y --no-install-recommends kicad kicad-cli --version diff --git a/.gitignore b/.gitignore index a8683cd..107c7b9 100644 --- a/.gitignore +++ b/.gitignore @@ -3,9 +3,11 @@ *.kicad_pcb-bak *~ *.lck +*-backups/ gerbers/ fp-info-cache *-cache.lib +_autosave-* # Python venvs / caches .venv/ diff --git a/kicad/innerjib7ea-rev-a/README.md b/kicad/innerjib7ea-rev-a/README.md index af8e8a7..45c461d 100644 --- a/kicad/innerjib7ea-rev-a/README.md +++ b/kicad/innerjib7ea-rev-a/README.md @@ -4,12 +4,28 @@ ## Status -**Skeleton.** KiCad project files not yet committed (no -`.kicad_pro` in this directory yet). This README precedes the -KiCad project to (a) document the intended scope, (b) make -ADR-001's locked decision visible at the directory root, and -(c) enumerate the sequence of follow-up PRs that fill this -directory. +**Skeleton landed.** Empty-but-valid KiCad 8 project files are +now in this directory: + +- `innerjib7ea.kicad_pro` — project envelope (JSON, KiCad 8 schema). +- `innerjib7ea.kicad_sch` — empty root schematic (sexpr, version + 20231120 / KiCad 8.0). +- `innerjib7ea.kicad_pcb` — empty board (sexpr, version 20240108 / + KiCad 8.0), 2-layer copper stack with the canonical KiCad 8 + user-layer enumeration; net 0 declared per spec; a placeholder + 100 mm × 100 mm square outline on `Edge.Cuts` (KiCad 8 DRC + rejects boards with no Edge.Cuts edges — the placeholder + satisfies that rule). The real mini-ITX 170 mm × 170 mm + envelope replaces it in roadmap item #6 (Layout pass). +- `fp-lib-table` / `sym-lib-table` — empty per-project library + tables (version 7) so the project is library-isolated and + contributors don't depend on each other's global KiCad config. + +The schematic and PCB are intentionally empty: the goal of this +PR is a project KiCad 8 opens cleanly and that the +`kicad-erc-drc` CI job reports clean against. Schematic capture, +DDR3 SO-DIMM connector, inter-card connector, layer stackup, and +layout fill the remaining roadmap items below in subsequent PRs. ## Spec (locked by ADR-001, with 2026-05-05 amendments) @@ -54,9 +70,13 @@ card, but it must be on the board. Sequential PRs land in this directory in approximately this order, one PR per step: -1. **KiCad project skeleton.** Coherent `.kicad_pro` + - empty-but-valid `.kicad_sch` + empty-but-valid `.kicad_pcb`, - produced with `kicad-cli` so files round-trip cleanly. +1. **KiCad project skeleton.** ✅ Landed — see Status above. + Files were authored against the published KiCad 8 file-format + spec (sexpr-pcb / sexpr-schematic / fp-lib-table / + sym-lib-table) because `kicad-cli` is not installed on the + contributor workstation; the CI `kicad-erc-drc` job is the + round-trip authority and runs `kicad-cli sch erc` and + `kicad-cli pcb drc` on the PR. 2. **Schematic capture.** ECP5-85F symbol; full power tree (12 V → 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.35 V / 1.0 V / 0.75 V, including the 2.5 V analog and 1.0 V digital rails for the diff --git a/kicad/innerjib7ea-rev-a/fp-lib-table b/kicad/innerjib7ea-rev-a/fp-lib-table new file mode 100644 index 0000000..807e065 --- /dev/null +++ b/kicad/innerjib7ea-rev-a/fp-lib-table @@ -0,0 +1,3 @@ +(fp_lib_table + (version 7) +) diff --git a/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_pcb b/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_pcb new file mode 100644 index 0000000..34fa89b --- /dev/null +++ b/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_pcb @@ -0,0 +1,123 @@ +(kicad_pcb + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + (setup + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (viasonmask no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plotreference yes) + (plotvalue yes) + (plotfptext yes) + (plotinvisibletext no) + (sketchpadsonfab no) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (gr_line + (start 0 0) + (end 100 0) + (stroke + (width 0.1) + (type default) + ) + (layer "Edge.Cuts") + (uuid "00000000-0000-0000-0000-000000000001") + ) + (gr_line + (start 100 0) + (end 100 100) + (stroke + (width 0.1) + (type default) + ) + (layer "Edge.Cuts") + (uuid "00000000-0000-0000-0000-000000000002") + ) + (gr_line + (start 100 100) + (end 0 100) + (stroke + (width 0.1) + (type default) + ) + (layer "Edge.Cuts") + (uuid "00000000-0000-0000-0000-000000000003") + ) + (gr_line + (start 0 100) + (end 0 0) + (stroke + (width 0.1) + (type default) + ) + (layer "Edge.Cuts") + (uuid "00000000-0000-0000-0000-000000000004") + ) +) diff --git a/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_pro b/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_pro new file mode 100644 index 0000000..43fa395 --- /dev/null +++ b/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_pro @@ -0,0 +1,169 @@ +{ + "board": { + "3dviewports": [], + "design_settings": { + "defaults": { + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, + "copper_text_size_h": 1.5, + "copper_text_size_v": 1.5, + "copper_text_thickness": 0.3, + "other_line_width": 0.15, + "silk_line_width": 0.15, + "silk_text_size_h": 1.0, + "silk_text_size_v": 1.0, + "silk_text_thickness": 0.15 + }, + "diff_pair_dimensions": [], + "drc_exclusions": [], + "rules": { + "min_clearance": 0.0, + "min_track_width": 0.0, + "min_via_diameter": 0.0, + "min_via_drill": 0.0 + }, + "track_widths": [], + "via_dimensions": [] + }, + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "erc": { + "erc_exclusions": [], + "meta": { + "version": 0 + }, + "pin_map": [], + "rule_severities": {}, + "rule_severitieses": {} + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "innerjib7ea.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.2, + "via_diameter": 0.6, + "via_drill": 0.3, + "wire_width": 6 + } + ], + "meta": { + "version": 3 + }, + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [] + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "plot": "", + "pos_files": "", + "specctra_dsn": "", + "step": "", + "svg": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [], + "filter_string": "", + "group_symbols": true, + "name": "Grouped By Value", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, + "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, + "default_line_thickness": 6.0, + "default_text_size": 50.0, + "field_names": [], + "intersheets_ref_own_page": false, + "intersheets_ref_prefix": "", + "intersheets_ref_short": false, + "intersheets_ref_show": false, + "intersheets_ref_suffix": "", + "junction_size_choice": 3, + "label_size_ratio": 0.375, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, + "pin_symbol_size": 25.0, + "text_offset_ratio": 0.15 + }, + "legacy_lib_dir": "", + "legacy_lib_list": [], + "meta": { + "version": 1 + }, + "net_format_name": "", + "page_layout_descr_file": "", + "plot_directory": "", + "spice_current_sheet_as_root": false, + "spice_external_command": "spice \"%I\"", + "spice_model_current_sheet_as_root": true, + "spice_save_all_currents": false, + "spice_save_all_dissipations": false, + "spice_save_all_voltages": false, + "subpart_first_id": 65, + "subpart_id_separator": 0 + }, + "sheets": [ + [ + "00000000-0000-0000-0000-000000000000", + "Root" + ] + ], + "text_variables": {} +} diff --git a/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_sch b/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_sch new file mode 100644 index 0000000..a27aa74 --- /dev/null +++ b/kicad/innerjib7ea-rev-a/innerjib7ea.kicad_sch @@ -0,0 +1,14 @@ +(kicad_sch + (version 20231120) + (generator "eeschema") + (generator_version "8.0") + (uuid "00000000-0000-0000-0000-000000000000") + (paper "A4") + (lib_symbols) + (symbol_instances) + (sheet_instances + (path "/" + (page "1") + ) + ) +) diff --git a/kicad/innerjib7ea-rev-a/sym-lib-table b/kicad/innerjib7ea-rev-a/sym-lib-table new file mode 100644 index 0000000..a468f5e --- /dev/null +++ b/kicad/innerjib7ea-rev-a/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (version 7) +)