From 0bec70400a04f0efb6811b112f9c4d4b5ce060ef Mon Sep 17 00:00:00 2001 From: "Marcos (Agent 4)" Date: Wed, 6 May 2026 13:01:55 -0300 Subject: [PATCH] docs(hw): rev-A schematic capture day-1 planning (page breakdown + symbol inventory + decoupling topology) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Day-1 planning artefacts only. Schematic page authoring follows in PR #6b, #6c, etc. with one page per PR for reviewability. Adds three planning docs under `docs/hw/` that the placement-step PRs will follow: 1. **`schematic-page-breakdown.md`** — enumerates the eight pages the rev-A KiCad project grows to (P1 block diagram, P2 ECP5-85F core, P3 DDR3L SO-DIMM, P4 GbE host link, P5 inter-card connector, P6 USB-UART debug + JTAG, P7 power tree, P8 boot flash). One page per PR for ~150-250-net review chunks. Approx. 555 placed nets total across the eight pages. 2. **`symbol-library-inventory.md`** — every symbol the rev-A schematic needs, classified by source: KiCad std libs (resistors, caps, USB connector, JTAG header), vendor portals (SnapEDA / Ultra- Librarian for FT232HL, RJ45+magnetics, SO-DIMM connector, VTT regulator, SPI flash), or hand-authored (ECP5-85F BG756 split by power domain, optionally 88E1512 SGMII PHY). Library strategy keeps `kicad/innerjib7ea-rev-a/lib/` library-isolated per the PR #23 bootstrap convention. CERN-OHL-S v2 license-compatibility matrix per vendor source. Cross-check rules before any vendor symbol merges. 3. **`decoupling-topology.md`** — per-rail decoupling spec for the ECP5-85F per **FPGA-TN-02038** (hardware checklist) and **FPGA-TN-02206** (SerDes / PCS usage guide §4 power filter). Topology only — bulk + mid + bypass + high-frequency tier sets per rail (VCC core, VCCAUX/VCCAUXA, VCCA/VCCHTX SerDes with ferrite-bead filter isolation per TN-02206, VCCHRX SerDes RX bias, VCCIO0..7 per bank with DDR3L-bank tightening). Exact capacitor counts and footprints deferred to placement. Day-1 decisions made (concrete because externally visible — BOM, board outline, software): - **SGMII PHY: Marvell 88E1512** as primary (KSZ9031RNX is documented substitute). Decision matrix in P4 covers distributor stocking (LATAM importers), datasheet open access, package size. Both PHYs fit the 2.5 V analog / 1.0 V digital rail topology already locked in `PCB_DESIGN.md`. - **USB-UART bridge: FTDI FT232HL** as primary (CP2102N is documented cost-down substitute). FT232HL chosen for MPSSE — lets a user without a J-Link program the FPGA bitstream over USB via OpenOCD. - **Inter-card connector: Hirose FX18-40P-0.8SH** per PR #11 (the inter-card connector ADR / footprint PR that lands separately). P5 placement PR cannot land before PR #11 lands. Out of scope deliberately: - Drawing the schematic in KiCad (multi-week, one page per PR). - Exact regulator part numbers (decision matrix in P7 placement PR). - BOM file (generated from placed schematic by `kicad-cli sch export bom` — separate PR consuming the union of P2-P8). - Layer stackup decisions (already locked in `PCB_DESIGN.md`). `kicad/innerjib7ea-rev-a/README.md` updated to point at the three new planning docs in roadmap step 2 (Schematic capture). References: ADR-001, `PCB_DESIGN.md`, `hw/ddr3l-decision.md`, FPGA-DS-02012-3.3, FPGA-TN-02038, FPGA-TN-02206, FPGA-TN-02018, JEDEC MO-244, IPC-7351B, CERN-OHL-S v2. Refs #6, #11 Authored by Agent 2 (FPGA Hardware). Signed-off-by: Marcos (Agent 2) Co-authored-by: Marcos (Agent 2) --- docs/hw/decoupling-topology.md | 294 +++++++++++++++++++ docs/hw/schematic-page-breakdown.md | 426 ++++++++++++++++++++++++++++ docs/hw/symbol-library-inventory.md | 255 +++++++++++++++++ kicad/innerjib7ea-rev-a/README.md | 33 ++- 4 files changed, 1001 insertions(+), 7 deletions(-) create mode 100644 docs/hw/decoupling-topology.md create mode 100644 docs/hw/schematic-page-breakdown.md create mode 100644 docs/hw/symbol-library-inventory.md diff --git a/docs/hw/decoupling-topology.md b/docs/hw/decoupling-topology.md new file mode 100644 index 0000000..f11f568 --- /dev/null +++ b/docs/hw/decoupling-topology.md @@ -0,0 +1,294 @@ + + +# rev-A decoupling topology — ECP5-85F per FPGA-TN-02038 / FPGA-TN-02206 + +**Status:** Day-1 planning (2026-05-06). Companion to +[`schematic-page-breakdown.md`](schematic-page-breakdown.md) and +[`symbol-library-inventory.md`](symbol-library-inventory.md). + +> **Scope.** Per-rail decoupling **topology** for the ECP5-85F +> (LFE5UM5G-85F-8BG756I). What capacitor classes go on which rail, +> in what tier (bulk / mid / bypass / high-frequency), with the +> rationale tied to Lattice's hardware checklist (FPGA-TN-02038) +> and SerDes / PCS usage guide (FPGA-TN-02206). **Exact counts and +> exact placement geometry are deferred to placement PR P2.** This +> doc is the spec; the placement PR is the implementation. + +## What "topology only" means here + +For each FPGA power rail, this document specifies: + +1. **The capacitor tiers** to provide (bulk / mid-frequency / + bypass / high-frequency). +2. **The capacitance values per tier** (e.g. 22 µF bulk + 4.7 µF + mid + 100 nF bypass). +3. **The dielectric class** required (X7R / X5R / NP0 / aluminium + polymer). +4. **The placement priority** within the BGA fanout (innermost / + outermost ring relative to the BGA balls). + +This document does **not** specify: + +1. The exact **count** of bypass caps per rail (deferred to + placement so the actual ball count and pour geometry can be + measured). +2. The exact **footprint** size (0201 / 0402 / 0603 — deferred to + placement; depends on JLCPCB minimum-feature class chosen). +3. The exact **part number** (ESL / ESR figures available from + datasheets at placement time will drive the choice; same + capacitor class can be sourced from many vendors). +4. The **PDN simulation results** — analytical SPICE / S-parameter + verification of the PDN impedance is a separate post-layout + activity, not part of schematic capture. + +## Lattice reference documents that bound this spec + +| Doc | Title | What it constrains | +|---|---|---| +| **FPGA-DS-02012-3.3** | ECP5 / ECP5-5G Family Data Sheet | Recommended operating voltages, max ripple, supply current per rail (Table 3.2). | +| **FPGA-TN-02038** | ECP5 Hardware Checklist | Decoupling capacitance values, tier counts per VCC / VCCAUX / VCCIO, ground / power return path rules. **Primary reference for the bulk / mid / bypass tier topology below.** | +| **FPGA-TN-02206** | ECP5 SerDes / PCS Usage Guide | Filtering of `VCCA`, `VCCHTX`, `VCCHRX` (the SerDes power rails). Topology differs from generic VCC because SerDes is more sensitive to phase noise. **Primary reference for the SerDes-specific filtering below.** | +| **FPGA-TN-02018** | ECP5 sysCONFIG Usage Guide | Configuration-pin power-up requirements; sets the lower bound on the decoupling for the configuration domain (typically shares VCCAUX). | + +Where this document cites a tier value, it follows TN-02038 unless +explicitly overridden by TN-02206 for a SerDes rail. + +## Per-rail topology + +The ECP5-5G has the following power domains (FPGA-DS-02012-3.3 +§3.2 Table 3.2). For each one this section names the rail +voltage, the source rail in the rev-A power tree, the decoupling +tier set, and the placement priority. + +### `VCC` — FPGA core (1.20 V) + +- **Source.** 1.20 V buck on power-tree page P7 (shared with + SerDes `VCCA` / `VCCHTX` per `PCB_DESIGN.md` power tree, with + the SerDes filter network described in + [`#vcca-and-vcchtx--serdes-power-12v`](#vcca-and-vcchtx--serdes-power-12-v) below). +- **Tier set:** + - **Bulk** — 1× 47 µF or 100 µF aluminium polymer, near the + regulator output, before the inductor de-Q if any. + - **Mid** — 4× 22 µF X5R MLCC at the BGA core perimeter + (rough count; deferred to placement). + - **Bypass** — 1× 4.7 µF X5R MLCC and 1× 100 nF X7R MLCC per + `VCC` ball cluster in the BGA fanout. + - **High-frequency** — 1× 1 nF X7R or 100 pF NP0 MLCC adjacent + to the cluster bypass when the cluster sits on a high-activity + bank (deferred to placement; per-cluster decision). +- **Placement priority.** 100 nF bypass innermost (closest ball + fanout); 4.7 µF behind it; 22 µF at the BGA perimeter; bulk at + the regulator. This is the ascending-frequency tier ladder + TN-02038 §3.2 prescribes. +- **Dielectric.** X7R for sub-µF bypass, X5R for ≥ 4.7 µF mid / + bulk MLCCs, aluminium polymer for the regulator-output bulk. +- **Notes.** Core current at 85F worst case is sub-1 A typical + for inference workloads and ~1.5 A peak under heavy SerDes + + DSP block use; the bulk + mid + bypass ladder above is + conservative for that load. + +### `VCCAUX` and `VCCAUXA` — auxiliary (2.5 V) + +- **Source.** 2.5 V buck on P7. `VCCAUX` and `VCCAUXA` are tied + per FPGA-DS-02012-3.3 Table 3.2 footnote 2. +- **Tier set:** + - **Bulk** — 1× 22 µF aluminium polymer or X5R at the regulator + output. + - **Bypass** — 1× 100 nF X7R MLCC per VCCAUX / VCCAUXA ball + (count exact at placement). +- **Placement priority.** 100 nF closest to the BGA balls; bulk at + the regulator. +- **Notes.** This rail also supplies the SGMII PHY analog domain + (88E1512 VDDA_2V5 if KSZ9031 substituted, VDDA_2V5 likewise) — + add a **ferrite bead + 10 µF** filter on the PHY-side trace to + isolate PHY analog noise from FPGA VCCAUX. Filter lives on P4, + not on P2. + +### `VCCA` and `VCCHTX` — SerDes power (1.2 V) + +- **Source.** 1.20 V buck on P7, **filtered separately from + `VCC`**. Per FPGA-TN-02206 §4 (Power Filter), SerDes rails + must be isolated from the noisy core supply by a low-resistance + ferrite or LC filter. +- **Tier set:** + - **Pre-filter bulk** — 1× 22 µF X5R MLCC on the trunk side + (shared with VCC core supply rail). + - **Filter element** — ferrite bead (BLM18AG471 class — 470 Ω + @ 100 MHz, low DCR) **or** small LC filter (1 µH + 10 µF X5R) + between the VCC core trunk and the SerDes branch. Choice + deferred to placement; ferrite is standard for ECP5. + - **Post-filter bulk** — 1× 10 µF X5R MLCC on the SerDes side + of the filter. + - **Bypass** — 1× 100 nF X7R MLCC per `VCCA` / `VCCHTX` ball. + - **High-frequency** — 1× 1 nF X7R MLCC adjacent to each + bypass. +- **Placement priority.** Filter element placed on the trunk + trace, close to the regulator output. Post-filter bulk + immediately after the filter. Bypass + high-frequency caps + innermost on the BGA fanout. +- **Notes.** **TN-02206 §4 explicitly requires filter isolation + for SerDes power.** Sharing the regulator with VCC core is + acceptable; sharing the post-filter copper pour is not. The + filter component must carry the SerDes channel current + (~50 mA worst-case per active channel) without saturating its + ferrite — verify against datasheet at placement. + +### `VCCHRX` — SerDes RX bias (0.30–1.26 V) + +- **Source.** Tied to the same post-filter SerDes node as `VCCA` + / `VCCHTX` for rev-A simplicity (FPGA-TN-02206 §4 lists this + as the reference topology for ECP5 designs that don't need + per-channel RX bias programming). A separate `VCCHRX` LDO is + available as a placement-time substitute if a particular link's + margin requires it. +- **Tier set:** Same as `VCCA` / `VCCHTX` — share the post-filter + bulk, add 1× 100 nF + 1× 1 nF bypass per `VCCHRX` ball. +- **Placement priority.** Inherits from the SerDes filter; + `VCCHRX` balls join the post-filter pour by short trace. +- **Notes.** Per FPGA-TN-02206 §4, biasing `VCCHRX` separately + with an LDO is only required for very-high-jitter applications + (PCIe Gen3 and above). Rev-A SGMII at 1.25 GBaud and MAST-link + at PCIe-Gen2 / Gen3 class are within the shared-rail tolerance. + +### `VCCIO0..7` — IO bank rails (1.35 V / 2.5 V / 3.3 V depending on bank) + +- **Source.** Per-bank, from the corresponding rail on P7: + - DDR3L byte-lane banks: 1.35 V (`SSTL135`). + - SGMII bank: 2.5 V or 3.3 V (decision on P2). + - General-purpose IO banks: 3.3 V. +- **Tier set (per VCCIO bank):** + - **Bulk** — 1× 10 µF X5R MLCC at the bank perimeter. + - **Bypass** — 1× 100 nF X7R MLCC per VCCIO ball pair (count + exact at placement; TN-02038 §3.2 recommends ≥ 1 per 4 IO + pins as a starting point, tightened to 1 per 2 pins for + high-toggle banks like DDR byte lanes). + - **High-frequency** — for DDR3L banks only: 1× 1 nF X7R MLCC + distributed every other VCCIO ball to suppress strobe-edge + noise. +- **Placement priority.** 100 nF closest to the BGA balls; bulk + at the bank perimeter; high-frequency caps interleaved between + the 100 nFs on DDR banks. +- **Notes.** The 1.35 V VCCIO bank carries the DDR3L SO-DIMM byte + lanes; per `hw/ddr3l-decision.md` this rail is shared with the + SO-DIMM module VDD. Decoupling on the SO-DIMM side is the + module's responsibility; decoupling on the FPGA side is per + this spec. + +## SerDes-specific filter detail (FPGA-TN-02206 §4) + +``` + 1.20 V buck (P7) + │ + ├──── VCC core trunk ──── (caps as VCC topology) ──── BGA core + │ + └──── ferrite bead ──── post-filter pour ──── BGA SerDes balls + │ + ├──── 10 µF post-filter bulk + ├──── 1× 100 nF / VCCA ball + ├──── 1× 100 nF / VCCHTX ball + ├──── 1× 100 nF / VCCHRX ball (shared rail) + └──── 1× 1 nF HF cap / cluster +``` + +The filter element selection depends on the worst-case SerDes +current draw. For two-channel use (SGMII + MAST-link single lane +active per direction in rev-A) the trunk current is small; a +470 Ω @ 100 MHz ferrite (BLM18AG471SN1D class) is the default +recommendation. For four-channel use (rev-A future bring-up of all +four MAST-link lanes simultaneously), verify the ferrite DCR +saturation margin at placement. + +## DDR3L-specific decoupling on the FPGA side + +`hw/ddr3l-decision.md` and `PCB_DESIGN.md` lock the DDR3L IO bank +at 1.35 V (SSTL135). The decoupling topology on the FPGA side of +the DDR3L byte lanes is per the VCCIO general spec above, with +this addition: + +- **VTT termination decoupling** (lives on P3, not P2) — + 4× 10 µF X5R MLCC near the VTT regulator output, plus 1× + 100 nF X7R MLCC per termination resistor pack near each + group of 4–8 termination resistors. +- **VREF decoupling** — 1× 100 nF X7R MLCC at the VREF generator + output (resistor divider or VTT-IC reference output). + +## Bulk decoupling at the power-input connector + +P7 (the power tree page) carries its own bulk decoupling at the +12 V input: + +- 1× 470 µF aluminium polymer at the connector. +- 1× 100 nF X7R MLCC at the connector. +- 1× TVS clamp (SMBJ15A or SMAJ15A) for transient suppression. + +Each downstream buck regulator has its own input + output +decoupling per the regulator's reference design (lands at +placement when the exact regulator is selected — the regulator +data sheet's "typical application" schematic is the source of +record for that page's decoupling). + +## High-frequency-cap deferral + +TN-02038 §3.2 lists 1 nF / 100 pF / 10 pF "high-frequency caps" +as an optional outermost tier. Whether to populate that tier at +all depends on: + +1. The board's PDN impedance target (set by the worst-case + simultaneous switching output count on a single bank). +2. Whether the SerDes link sees jitter margin issues during + bring-up. + +**Decision for rev-A.** Plan the topology with placeholder +positions for high-frequency caps on DDR3L banks and SerDes +clusters; populate them only if bring-up shows a measurable need. +The 0402 / 0201 footprints reserved for them carry zero-Ω +"jumper" or DNP markings on the schematic until placement +verifies population. + +## What lands in the placement PR P2 (and PR P7) + +The schematic capture for P2 (ECP5 page) implements: + +- One bypass cap per VCC / VCCAUX / VCCIO / SerDes ball cluster + per the topology spec above, drawn next to the ball it serves. +- Bulk caps drawn at the bank or trunk perimeter. +- Filter element (ferrite or LC) drawn on the SerDes branch trunk. +- VTT decoupling drawn on P3, not P2. + +The schematic capture for P7 (power tree page) implements: + +- Per-rail input + output decoupling for each buck regulator + per the regulator's data sheet typical application schematic. +- Power-good chain for sequencing. +- Bulk filtering at the 12 V input. + +## What lands in placement layout (post-schematic) + +- Exact decoupling-cap **placement geometry** (distance from + ball, orientation relative to the GND via, via-stitch density + on the GND return path) — driven by FPGA-TN-02038 §3.3 + guidance. +- **PDN impedance simulation** — analytical SPICE / S-parameter + verification (pi-PDN, Sigrity, or open tools like KiCad's + upcoming PDN analyser) lives in the layout PR or a follow-up + bring-up validation PR. + +## References + +- ADR-001 — [`../adr/0001-fpga-target.md`](../adr/0001-fpga-target.md) +- `PCB_DESIGN.md` power tree — + [`../PCB_DESIGN.md`](../PCB_DESIGN.md) +- DDR3L decision — [`ddr3l-decision.md`](ddr3l-decision.md) +- Schematic page breakdown — + [`schematic-page-breakdown.md`](schematic-page-breakdown.md) +- Symbol library inventory — + [`symbol-library-inventory.md`](symbol-library-inventory.md) +- Lattice **FPGA-DS-02012-3.3** — ECP5 / ECP5-5G Family Data + Sheet (Recommended Operating Conditions, Table 3.2). +- Lattice **FPGA-TN-02038** — ECP5 Hardware Checklist + (decoupling tier counts and placement guidance). +- Lattice **FPGA-TN-02206** — ECP5 SerDes / PCS Usage Guide + (SerDes power filter §4). +- Lattice **FPGA-TN-02018** — ECP5 sysCONFIG Usage Guide. + +Authored by Agent 2 (FPGA Hardware). diff --git a/docs/hw/schematic-page-breakdown.md b/docs/hw/schematic-page-breakdown.md new file mode 100644 index 0000000..a827c69 --- /dev/null +++ b/docs/hw/schematic-page-breakdown.md @@ -0,0 +1,426 @@ + + +# rev-A schematic page breakdown — InnerJib7EA POPC_16A + +**Status:** Day-1 planning (2026-05-06). Closes Stays issue #6 +*planning artefact only* — actual schematic placement lands in +follow-up PRs `#6b`, `#6c`, … one page per PR for reviewability. + +> **Scope.** This document enumerates the eight schematic pages +> that the rev-A KiCad project (`kicad/innerjib7ea-rev-a/`) will +> grow to. It is the contract that subsequent placement PRs honour. +> No actual symbol placement, no wire routing, no part-number +> commitments beyond what ADR-001, `PCB_DESIGN.md`, and +> `hw/ddr3l-decision.md` already lock. + +## Why eight pages + +KiCad 8 hierarchical schematics scale comfortably to ~10 pages of +≤ A3 sheet size before the eye loses the block diagram. Eight pages +maps cleanly onto the rev-A functional partitioning: one page per +major subsystem, plus a top-level block diagram. Each page becomes +its own PR so reviewers can inspect ~150–250 nets of context at a +time rather than the full ~1.5k-net board. + +## Page map + +| Page | Title | PR target | Approx. nets | Critical references | +|---|---|---|---|---| +| P1 | Block diagram (top sheet) | #6b | hierarchical only | this doc | +| P2 | ECP5-85F core | #6c | ~250 (BGA-756 power + ground + decoupling stubs) | FPGA-DS-02012-3.3, FPGA-TN-02038, FPGA-TN-02206 | +| P3 | DDR3L SO-DIMM | #6d | ~100 (address / data / strobe / VTT) | `hw/ddr3l-decision.md`, `PCB_DESIGN.md` | +| P4 | GbE host link | #6e | ~40 (SGMII + MDIO + RJ45 + magnetics) | `PCB_DESIGN.md` GbE chain | +| P5 | Inter-card connector | #6f | ~50 (MAST-link diff pairs + sideband) | PR #11 (Hirose FX18-40P) | +| P6 | USB-UART debug + JTAG | #6g | ~20 (USB D±, UART TXD/RXD, JTAG 2x5) | `PCB_DESIGN.md` connectors table | +| P7 | Power tree | #6h | ~80 (12 V → 7 rails + sequencing) | `PCB_DESIGN.md` power tree, `hw/decoupling-topology.md` | +| P8 | Boot flash | #6i | ~15 (SPI x4 + CS# + WP# + HOLD#) | ECP5 sysCONFIG (FPGA-TN-02018) | + +Total: ~555 placed nets across the eight pages, plus power-rail +nets that span pages via the global `pwr` netclass. + +--- + +## P1 — Block diagram (top sheet) + +**Purpose.** Single-page mental map: anyone opening the project sees +the rev-A architecture in one frame, with arrows pointing into each +sub-sheet. This is the only page that contains no real components — +it is hierarchical sheet symbols only. + +**Contents.** + +- One sheet symbol per page P2–P8. +- Inter-sheet labels: + - `VCC_*` rails (drawn as wide buses). + - DDR3L byte-lane buses (`DQ[15:0]`, `DQS[1:0]`, `ADDR[14:0]`, + `BA[2:0]`, `CTRL`). + - SGMII pair (`SGMII_TX_p/n`, `SGMII_RX_p/n`). + - Inter-card MAST-link pairs (`MAST_TX[3:0]_p/n`, + `MAST_RX[3:0]_p/n`). + - SPI flash bus (`SPI_*`). + - JTAG (`TCK`, `TMS`, `TDI`, `TDO`). + - UART (`DBG_TXD`, `DBG_RXD`). +- A title block citing ADR-001 and the date of the most recent + amendment. + +**Author cost.** Trivial once P2–P8 are placed; hierarchical sheet +symbols are auto-stubbed by KiCad as P2–P8 land. + +--- + +## P2 — ECP5-85F core (BGA-756 power pins, decoupling spec) + +**Purpose.** Place the FPGA symbol(s) and wire every power and +ground pin to the appropriate rail with the spec'd decoupling +network adjacent to each pin group. Signal pins (DDR3 byte lanes, +SGMII, MAST-link) terminate at hierarchical labels that the +sub-sheets pick up. + +**Contents.** + +- **U1 — LFE5UM5G-85F-8BG756I** (Lattice ECP5-5G, 85k LUT, 756-ball + BGA). Single symbol or split-into-units (one unit per power + domain) — author's choice when the page is drawn. Splitting by + bank is the convention used by OrangeCrab and Versa-ECP5 + reference schematics; we follow that to ease cross-reference. +- **Power pin groupings** (per FPGA-DS-02012-3.3 §3.2 Table 3.2): + - `VCC` (1.20 V) — FPGA core. + - `VCCAUX` + `VCCAUXA` (2.5 V) — auxiliary, shared per Table + 3.2 footnote 2. + - `VCCA` + `VCCHTX` (1.20 V) — SerDes power; can share the core + rail or be filtered separately (decision deferred to placement + PR per `PCB_DESIGN.md`). + - `VCCHRX` (0.30–1.26 V) — SerDes RX bias; routing per + FPGA-TN-02206. + - `VCCIO0..7` — IO bank rails. Bank assignments: + - DDR3L byte-lane banks: **1.35 V (`SSTL135`)** per + `hw/ddr3l-decision.md`. + - GbE SGMII bank: 2.5 V or 3.3 V per Lattice MIPI / SGMII app + note (final decision lives on this page). + - General-purpose IO: 3.3 V. + - `GND` — single net, star-tied at the BGA fanout. +- **Decoupling network** per `hw/decoupling-topology.md`. P2 carries + the topology stubs (one bulk + N bypass per pin group); exact + capacitor counts and footprints land at placement. +- **Configuration pin strapping** (`CFG_0..2`, `MODE`, `INIT_B`, + `DONE`, `PROGRAM_B`). SPI master mode strap for boot from flash + on P8. + +**Cross-page hierarchical labels.** + +- DDR3L: `DDR_DQ[15:0]`, `DDR_DQS[1:0]_p/n`, `DDR_ADDR[14:0]`, + `DDR_BA[2:0]`, `DDR_CTRL`, `DDR_CK_p/n`, `DDR_ODT`, `DDR_RESET#`. +- SGMII: `SGMII_TX_p/n`, `SGMII_RX_p/n`, `MDIO`, `MDC`, `PHY_INT#`. +- MAST-link: `MAST_TX[3:0]_p/n`, `MAST_RX[3:0]_p/n`, sideband. +- Boot flash: `SPI_CLK`, `SPI_CS#`, `SPI_MOSI`, `SPI_MISO`, + `SPI_WP#`, `SPI_HOLD#`. +- JTAG / UART / debug. + +**Author note.** The Lattice symbol for BG756 is the largest single +symbol on the board. Inventory is in +[`symbol-library-inventory.md`](symbol-library-inventory.md). + +--- + +## P3 — DDR3L SO-DIMM (CT4G3S160BM, address/data/strobe groups, VTT termination) + +**Purpose.** Wire the 204-pin SO-DIMM connector to the ECP5 IO +banks via length-grouped buses, with the VTT termination network +on this page for locality. + +**Contents.** + +- **J1 — Molex 78171 series** (or TE 1473005 — equivalent) 204-pin + DDR3 / DDR3L SO-DIMM connector. +- Reference module: **Crucial CT4G3S160BM** (4 GB DDR3L-1600, + single-rank, 1.35 V) per `hw/ddr3l-decision.md`. The schematic + encodes the connector pinout, not the module — the module is a + BOM-only entry. +- **Pin groups:** + - **Address**: A0–A14, BA0–BA2, CKE0, CS0#, RAS#, CAS#, WE#, + ODT0. IO standard `SSTL135_I`. + - **Data lane 0**: DQ0–DQ7, DQS0_p/n (`SSTL135D_I`), DM0. + - **Data lane 1**: DQ8–DQ15, DQS1_p/n (`SSTL135D_I`), DM1. + - **Clock**: CK0_p/n (`SSTL135D_I`). + - **Power**: 1.35 V VDD pins (J1 pins per JEDEC MO-244 SO-DIMM + pinout) tied to the 1.35 V plane on layer 5. + - **VTT termination**: 0.675 V (= VDD/2) tied via per-line + series Rs to the address-group rail. VTT generator (LDO or + dedicated VTT IC such as TPS51200) on this page. + - **VREF**: 0.675 V reference for the SSTL135 receivers. +- **Hierarchical labels** import from P2: + `DDR_DQ[15:0]`, `DDR_DQS[1:0]_p/n`, `DDR_ADDR[14:0]`, + `DDR_BA[2:0]`, `DDR_CTRL`, `DDR_CK_p/n`, `DDR_ODT`, `DDR_RESET#`. +- **Length-match annotation** per `PCB_DESIGN.md` routing rules: + ±5 mil within byte lane, ±10 mil across address. Annotation only + on the schematic — actual matched routing happens at layout. +- **SPD I²C** (J1 SPD pins → I²C bus to ECP5 for SPD readout + during bring-up). + +**Note.** The Trellis Board "1.5 V module under-volted to 1.35 V" +hack is **not** an option — see `hw/ddr3l-decision.md`. The 1.35 V +rail feeds both the module VDD and the ECP5 VCCIO bank. + +--- + +## P4 — GbE host link (Marvell 88E1512 SGMII PHY + RJ45 + magnetics) + +**Purpose.** Wire the SGMII pair from the ECP5 SerDes through an +external SGMII PHY chip into the magnetics + RJ45 jack. + +**Contents.** + +- **U2 — Marvell Alaska 88E1512** (32-pin QFN, SGMII ↔ 1000BASE-T + PHY). See "PHY chip selection" below for rationale. +- **T1 — Magnetics**, integrated into the RJ45 jack (HanRun + HR911105A or Bel Fuse 0826-1G1T-23-F per `PCB_DESIGN.md`). +- **J2 — RJ45** with integrated magnetics + LEDs. +- **SGMII pair** from ECP5 SerDes channel B (or A — channel + decision deferred to P2 placement) AC-coupled (0.1 µF series + caps) into the 88E1512 SGMII pins. +- **MDIO + MDC** management bus to ECP5. +- **PHY power**: 2.5 V analog (shares `VCCAUX` rail per + `PCB_DESIGN.md` power tree), 1.0 V digital core (dedicated rail + off the buck on P7), 3.3 V IO (shares the FPGA general-purpose + 3.3 V). +- **Strap pins** for PHY mode (SGMII slave, auto-negotiation + enabled, MDIO PHY address) per the 88E1512 datasheet hardware + configuration table. +- **Reset and clock**: PHY 25 MHz reference crystal (or shared + with FPGA reference clock — decision lives at placement); + PHY_RESET# to ECP5 GPIO. + +### PHY chip selection (decision made for this PR) + +`PCB_DESIGN.md` previously named **Microchip KSZ9031RNX** in the +`### GbE PHY chain` block but called for **2.5 V** analog and +**1.0 V** digital rails. Both KSZ9031RNX and the **Marvell +88E1512** are commonly cited SGMII PHYs in the open-FPGA +community. + +**This PR selects the Marvell 88E1512** as the rev-A reference. +Rationale: + +| Criterion | KSZ9031RNX | 88E1512 | Outcome | +|---|---|---|---| +| LiteEth integration | tested, multiple boards | tested, multiple boards | tie | +| Open-source PHY init code | yes (`liteeth/phy/ks*`) | yes (`liteeth/phy/marvell*` style) | tie | +| Distributor stocking (LATAM importers) | uneven | broad (Mouser, Digi-Key, Arrow) | 88E1512 | +| Datasheet open access | NDA-free | NDA-free public datasheet (`88E151x_PB.pdf`) | tie | +| Package | 48-pin QFN, 7×7 mm | 32-pin QFN, 5×5 mm | 88E1512 (smaller, fewer balls) | +| Default 25 MHz crystal | yes | yes | tie | +| Hardware-strap auto-negotiation | yes | yes | tie | + +The KSZ9031RNX remains an acceptable substitute for builders who +have it in stock; placement PR P4 documents the swap procedure +inline. The 1.0 V digital core rail and 2.5 V analog rail are +fungible between the two chips at this voltage class — no power +tree change needed if a builder swaps. + +> **Cross-check.** `PCB_DESIGN.md` will be updated in a follow-up +> documentation PR (out of scope for this planning artefact) to +> normalise on 88E1512 as the primary reference and KSZ9031RNX as +> the documented substitute. This page-breakdown doc is the leading +> edge of that change. + +--- + +## P5 — Inter-card connector (Hirose FX18-40P-0.8SH per PR #11) + +**Purpose.** Wire the inter-card MAST-link diff pairs from the +ECP5 SerDes (other channel) plus sideband signals into the +40-pin inter-card connector. Multi-card aggregation requires this +connector be physically present on rev-A even if rev-A ships +single-card. + +**Contents.** + +- **J3 — Hirose FX18-40P-0.8SH** (40-pin 0.8 mm pitch board-to-board + connector, low-profile, mezzanine-style). Reference from PR #11 + (the inter-card connector ADR / footprint PR — to land before P5 + placement; tracked separately). +- **MAST-link diff pairs** (4 lanes TX + 4 lanes RX): + - `MAST_TX[3:0]_p/n` — ECP5 SerDes channel A (or B — decision + on P2). + - `MAST_RX[3:0]_p/n` — ECP5 SerDes paired with the TX channel. + - AC coupling caps (0.1 µF) on each pair, on this page. +- **Sideband** (single-ended, slow): + - `MAST_PRESENT#` — bus presence detect. + - `MAST_INT#` — wake / interrupt to neighbouring card. + - `MAST_RESET#` — synchronised reset propagation. + - `MAST_I2C_SCL` / `MAST_I2C_SDA` — out-of-band management. + - 4 reserved sideband pins. +- **Power forwarding**: 3.3 V_AUX rail for the receiving card's + housekeeping MCU (1 A budget). The data card does not draw its + main 12 V across this connector. +- **Mechanical-only edge fingers** per `PCB_DESIGN.md` connectors + table — note this row in the table treats inter-card link as + PCIe-style edge fingers; PR #11 may revise to the FX18-40P + mezzanine option. The schematic page authors against whatever + PR #11 lands. + +> **Dependency.** P5 cannot land before PR #11 lands. P5's PR +> description must reference PR #11 explicitly. + +--- + +## P6 — USB-UART debug + JTAG + +**Purpose.** Bring-up debug surface: a USB-to-UART bridge for +console output and a 2x5 0.05" JTAG header for FPGA bitstream +debugging. + +**Contents.** + +- **U3 — FT232HL** (or **CP2102N** — see PHY-style decision matrix + below). USB-to-UART (and FT232HL also offers MPSSE for JTAG + bit-banging in a pinch). +- **J4 — Micro-USB B** receptacle. ESD diode array on D+/D- pair. +- **J5 — JTAG 2x5 header**, 0.05" pitch, shrouded, Tigard / + Black Magic Probe / J-Link compatible pinout. +- **Decoupling**: per FT232HL datasheet (10 µF + 100 nF on + 3.3 V_USB rail; 100 nF on 1.8 V VCCIO). +- **Power**: USB 5 V comes in on J4; the LDO inside FT232HL + provides 3.3 V locally. The board's 3.3 V_AUX rail is **not** + fed from USB — keep them isolated so that an unplugged USB + cable does not collapse the board's 3.3 V_AUX. + +### Bridge IC selection (decision made for this PR) + +`PCB_DESIGN.md` lists "FT232H or CP2102N bridge" as tentative +("revisit when bring-up scripts land"). This planning doc +selects the primary chip: + +| Criterion | FT232HL | CP2102N | Outcome | +|---|---|---|---| +| Cost (single units) | $5–7 | $2–3 | CP2102N | +| MPSSE for JTAG bit-bang | yes (load via OpenOCD) | no | FT232HL | +| Driver maturity (Linux mainline) | yes | yes | tie | +| Package | LQFP-48 | QFN-24 | tie | +| Distributor stocking | broad | broad (Silicon Labs) | tie | + +**Selection: FT232HL** as the primary bring-up bridge, because +the MPSSE feature lets a user without a J-Link or Tigard still +program the FPGA bitstream over USB via OpenOCD. CP2102N is the +documented BOM substitute for cost-sensitive builds that already +have a JTAG probe. + +--- + +## P7 — Power tree (12 V → buck → 1.2 V / 2.5 V / 3.3 V / 1.35 V / 0.675 V / 1.0 V / 1.8 V) + +**Purpose.** Convert the 12 V ATX / barrel jack input into the +seven secondary rails with the topology, sequencing, and bulk +filtering called for by the power tree in `PCB_DESIGN.md`. + +**Contents.** + +- **J6 — power input.** 4-pin Molex KK254 (ATX-style) per + `PCB_DESIGN.md` connectors table; barrel jack as alternate + population. +- **Bulk input filtering**: 470 µF aluminium polymer + 100 nF + ceramic at the connector. TVS clamp (SMBJ15A) for 12 V transient + protection. +- **Inrush current limit**: NTC thermistor (or soft-start + buck-converter feature) on the 12 V rail. +- **Seven rails** per `PCB_DESIGN.md` power tree: + 1. **3.3 V** — buck step-down, ~3 A. Feeds FPGA `VCCIO` 3.3 V + banks, USB-UART bridge, sideband logic. + 2. **2.5 V** — buck step-down, ~1 A. Feeds FPGA `VCCAUX` / + `VCCAUXA` (shared per Table 3.2 footnote 2), 88E1512 analog + supply. + 3. **1.8 V** — buck step-down, ~0.5 A. General-purpose 1.8 V + auxiliary; **not** VCCAUX (which is 2.5 V) — see + `PCB_DESIGN.md` rev-A subsection note. + 4. **1.35 V** — buck step-down, ~3 A. Feeds DDR3L SO-DIMM VDD + **and** the ECP5 IO bank VCCIO for SSTL135 byte lanes + (single rail per `hw/ddr3l-decision.md`). + 5. **1.20 V** — buck step-down, ~5 A. Feeds FPGA core `VCC` + **and** SerDes `VCCA` / `VCCHTX` per `PCB_DESIGN.md` power + tree (corrected from the earlier 1.35 V LDO entry — see + `PCB_DESIGN.md` "1.2 V step-down" bullet). + 6. **1.0 V** — buck step-down, ~0.3 A. Feeds 88E1512 digital + core. + 7. **0.675 V** — LDO or dedicated VTT regulator (TPS51200 or + equivalent), ~0.5 A. DDR3L VTT termination (= VDD/2 of the + 1.35 V module rail). +- **Sequencing**: power-good chain (12 V_PG → 3.3 V_PG → 2.5 V_PG + → 1.35 V_PG → 1.2 V_PG → 1.0 V_PG → board reset deasserted). + Sequencing logic: discrete (3-input AND) or a power-management + IC (TPS65086, LTC2937 — decision lives at placement). + +> **Out of scope for this planning doc.** Exact regulator part +> numbers (e.g. TPS54302 vs LMR33630 for the 3.3 V buck) — the +> placement PR (P7) authors a decision matrix similar to the PHY +> matrix above and the BOM lands with that PR. + +--- + +## P8 — Boot flash (SPI for ECP5 bitstream) + +**Purpose.** Non-volatile bitstream storage for the ECP5. The +ECP5 sysCONFIG (FPGA-TN-02018) supports SPI master, SPIm x1 / x2 +/ x4, and SlaveSPI / SlaveSerial / JTAG. rev-A uses SPIm x4 +(quad-SPI) for fastest configuration. + +**Contents.** + +- **U4 — Cypress S25FL128SAGMFI001** (or equivalent) — 128 Mb + (16 MB) quad-SPI NOR flash, 3.3 V, 8-pin SOIC. 16 MB is sized + for the full 85F bitstream (~3 MB compressed) plus headroom for + multi-config / golden-image schemes. +- **8 SPI lines**: CLK, CS#, IO0 (MOSI), IO1 (MISO), IO2 (WP#), + IO3 (HOLD#) — quad-SPI uses all four. Strapping: ECP5 sysCONFIG + configured for SPIm x4. +- **Decoupling**: 100 nF ceramic at the flash; 10 µF bulk on the + 3.3 V rail near the chip. +- **Pull-ups** on CS# (10 kΩ) and HOLD# (10 kΩ) so the flash is + deselected during ECP5 reset. + +> **Out of scope.** Multi-config golden-image SPI flash layout +> (one SPI flash with two bitstream slots, ECP5 watchdog falls +> back to slot 0 if slot 1 is bad). That feature is rev-B+ +> material; rev-A is single-image. + +--- + +## What this doc deliberately does **not** specify + +- **Exact regulator part numbers.** The PHY and bridge IC + decisions above are concrete because they are externally + visible (BOM, board outline, software). Regulator selection is + a decision matrix authored in P7's placement PR. +- **Exact decoupling capacitor counts.** Topology only — see + [`decoupling-topology.md`](decoupling-topology.md). Counts + land at placement. +- **Net naming convention details.** Convention is "ALL_CAPS with + underscores; signed-end suffix `_p` / `_n`; active-low suffix + `#`". The placement PRs follow this convention without further + discussion. +- **Layer stackup decisions.** Already locked in `PCB_DESIGN.md` + (8-layer); revisited only if a placement PR finds a constraint + that breaks the locked stackup. +- **BOM file.** Generated from the placed schematic by `kicad-cli + sch export bom`; not in scope for any of the page-placement PRs + individually. A separate BOM PR consumes the union of P2–P8. + +## References + +- ADR-001 — [`../adr/0001-fpga-target.md`](../adr/0001-fpga-target.md) +- `PCB_DESIGN.md` — [`../PCB_DESIGN.md`](../PCB_DESIGN.md) +- DDR3L decision — [`ddr3l-decision.md`](ddr3l-decision.md) +- Symbol library inventory — + [`symbol-library-inventory.md`](symbol-library-inventory.md) +- Decoupling topology — + [`decoupling-topology.md`](decoupling-topology.md) +- Lattice **FPGA-DS-02012-3.3** — ECP5 / ECP5-5G Family Data Sheet. +- Lattice **FPGA-TN-02038** — ECP5 Hardware Checklist (decoupling). +- Lattice **FPGA-TN-02206** — ECP5 SerDes / PCS Usage Guide. +- Lattice **FPGA-TN-02018** — ECP5 sysCONFIG Usage Guide. +- Marvell **88E151x Public Brief** (`88E151x_PB.pdf`) — SGMII PHY. +- Microchip **KSZ9031RNX** datasheet — SGMII PHY substitute. +- FTDI **FT232HL** datasheet (DS_FT232H) — USB-UART bridge. +- Silicon Labs **CP2102N** datasheet — USB-UART bridge substitute. +- JEDEC **MO-244** — DDR3 / DDR3L SO-DIMM mechanical / pinout. + +Authored by Agent 2 (FPGA Hardware). diff --git a/docs/hw/symbol-library-inventory.md b/docs/hw/symbol-library-inventory.md new file mode 100644 index 0000000..25d2fdc --- /dev/null +++ b/docs/hw/symbol-library-inventory.md @@ -0,0 +1,255 @@ + + +# rev-A schematic symbol library inventory + +**Status:** Day-1 planning (2026-05-06). Companion to +[`schematic-page-breakdown.md`](schematic-page-breakdown.md). + +> **Scope.** Catalogue every symbol the rev-A schematic needs and +> name where each one comes from: KiCad 8 standard libraries, a +> vendor portal (Lattice / SnapEDA / Ultra-Librarian), or +> hand-authored. The placement PRs (#6c–#6i) source their symbols +> from this inventory. No symbols are checked into the project +> library at this stage — this doc is a manifest, not a binary blob. + +## Library strategy + +The KiCad project under `kicad/innerjib7ea-rev-a/` ships with +**empty per-project library tables** (`sym-lib-table` and +`fp-lib-table` at version 7) per PR #23. This is deliberate: + +- The project is **library-isolated** so contributors do not need + to align their global KiCad config to ours. +- Each placement PR adds **only the symbols and footprints it + uses** to the per-project library, keeping the diff reviewable. +- Standard KiCad symbols (resistors, capacitors, diodes, + connectors with KiCad-canonical footprints) are referenced from + the user's globally-installed KiCad 8 libraries — they are not + re-vendored into the project library, because every KiCad 8 + install ships with them. +- Vendor and hand-authored symbols **are vendored** into + `kicad/innerjib7ea-rev-a/lib/` so the build is reproducible + without external network access. + +### Library directory layout (target, lands per PR) + +``` +kicad/innerjib7ea-rev-a/ +├── innerjib7ea.kicad_pro +├── innerjib7ea.kicad_sch +├── innerjib7ea.kicad_pcb +├── sym-lib-table ← updated as symbols land +├── fp-lib-table ← updated as footprints land +└── lib/ + ├── innerjib7ea.kicad_sym ← hand-authored symbols + ├── innerjib7ea.pretty/ ← hand-authored footprints + ├── vendor-lattice.kicad_sym + ├── vendor-marvell.kicad_sym + ├── vendor-snapeda.kicad_sym + ├── vendor-ultralibrarian.kicad_sym + └── vendor-*.pretty/ ← matching vendor footprints +``` + +Vendor library files are split by source so any one vendor's licence +or terms-of-use can be honoured independently. + +## License compatibility (vendor symbol provenance) + +| Vendor source | Typical licence | Compatible with CERN-OHL-S v2 hardware? | Notes | +|---|---|---|---| +| KiCad standard libraries | CC-BY-SA 4.0 | yes | distributed with KiCad | +| Lattice (direct from vendor) | varies — usually free-to-use, no redistribution clause | yes for the ECP5 page once we re-author the symbol from the published pinout in the datasheet | Pinout is factual, not copyrightable; we author the symbol ourselves and cite the datasheet | +| SnapEDA | SnapEDA EULA — free for commercial use, attribution required, redistribution allowed | yes with attribution | each symbol's provenance recorded inline in the symbol's `Description` and `Footprint` filter fields | +| Ultra-Librarian | similar to SnapEDA — free with attribution | yes with attribution | same | +| Hand-authored | CERN-OHL-S v2 (project licence) | yes | author this only when no vendor symbol exists | + +The cooperative's hardware licence is **CERN-OHL-S v2** per +`PCB_DESIGN.md`. That is the strongly-reciprocal copyleft licence +for hardware. Vendor symbols whose licence forbids redistribution +are **not** acceptable; this inventory blocks any such symbol with +an "avoid" tag below. + +## Symbol inventory by page + +### P1 — Block diagram + +Hierarchical sheet symbols are KiCad primitives — no external +symbol library needed. + +### P2 — ECP5-85F core + +| Ref | Part | Source | Status | +|---|---|---|---| +| U1 | LFE5UM5G-85F-8BG756I (Lattice ECP5-5G, 756-ball BGA) | **Hand-authored** | author from FPGA-DS-02012-3.3 §4 (Pinout). Lattice publishes a Symbol Generator service for some KiCad-compatible formats but coverage of ECP5-5G in the BG756 package is incomplete; safer to hand-author and split by power domain. | +| | Bypass / decoupling caps (0.1 µF, 1 nF, 4.7 µF, 10 µF, 22 µF) | KiCad std (`Device:C`) | use `C_Small` for schematic clarity | +| | Bulk caps (47 µF, 100 µF aluminium polymer) | KiCad std (`Device:CP`) | polarised | +| | Pull-up / pull-down resistors (10 kΩ, 4.7 kΩ, 1 kΩ) | KiCad std (`Device:R`) | | +| | Configuration mode straps (DIP switch or zero-Ω jumpers) | KiCad std (`Switch:SW_DIP_x04`) | one strap bank per CFG[2:0] line | + +**Decision.** Hand-author the ECP5 symbol rather than pull from a +vendor portal. Split by power domain (one symbol unit per VCCIO +bank, one for VCC core, one for VCCAUX, one for SerDes, one for +GND, one for IO) following the OrangeCrab / Versa-ECP5 +convention. This split makes each schematic page easier to read +and matches how the placement PR P2 partitions the work. + +### P3 — DDR3L SO-DIMM + +| Ref | Part | Source | Status | +|---|---|---|---| +| J1 | 204-pin SO-DIMM connector (Molex 78171 / TE 1473005) | **SnapEDA** (preferred) or hand-author | SnapEDA hosts both Molex 78171-2042 and TE 1473005-1; either is acceptable. Footprint mechanical drawing is in JEDEC MO-244 — we cross-check the SnapEDA footprint against MO-244 before merge. | +| | VTT regulator (TPS51200 or equivalent) | **SnapEDA** | TI publishes KiCad symbols on its product pages via Ultra-Librarian; SnapEDA mirrors them. | +| | Series termination Rs (33 Ω 0402 / 0603) | KiCad std (`Device:R`) | | +| | Decoupling caps for VTT, VREF | KiCad std (`Device:C`) | | +| | I²C pull-ups for SPD bus | KiCad std (`Device:R`) | 4.7 kΩ | + +### P4 — GbE host link + +| Ref | Part | Source | Status | +|---|---|---|---| +| U2 | Marvell Alaska 88E1512 SGMII PHY (32-pin QFN) | **Hand-authored** (preferred) or SnapEDA | the public 88E151x_PB does not include a vendor KiCad symbol; SnapEDA has community-uploaded variants of varying quality. Hand-author from the public-brief pinout for safety. | +| T1 | RJ45 with integrated magnetics (HanRun HR911105A) | **SnapEDA** | well-stocked symbol on SnapEDA; verify the magnetics tap topology against HanRun datasheet before merge. | +| J2 | RJ45 jack with integrated LEDs | bundled into T1 | | +| | AC-coupling caps (0.1 µF, 0402 X7R) | KiCad std (`Device:C`) | series in SGMII pair | +| | Termination Rs for SGMII pair | KiCad std (`Device:R`) | | +| | Bob Smith network (75 Ω + 1 kV cap) | KiCad std (`Device:R`, `Device:C`) | EMI termination on RJ45 unused pins | +| | 25 MHz crystal for PHY | **SnapEDA** | crystal symbol straight from SnapEDA; verify load-cap rating | +| | 22 pF crystal load caps | KiCad std (`Device:C`) | NP0 dielectric required | + +> **Substitute.** If SnapEDA's 88E1512 symbol is acceptable upon +> cross-check at placement time (verify all 32 pins against +> 88E151x_PB, verify package footprint against datasheet land +> pattern), it can replace the hand-authored entry. Provenance +> field in the symbol records the decision. + +### P5 — Inter-card connector + +| Ref | Part | Source | Status | +|---|---|---|---| +| J3 | Hirose FX18-40P-0.8SH (40-pin 0.8 mm pitch board-to-board) | **Hirose** (vendor portal) → typically distributed via SnapEDA / Ultra-Librarian | Hirose publishes 3D STEP and PCB land patterns on its product page; SnapEDA mirrors KiCad libraries for FX18-series connectors. Pull from SnapEDA, cross-check against Hirose's published land pattern. | +| | AC-coupling caps for MAST diff pairs | KiCad std (`Device:C`) | 0.1 µF X7R | +| | Pull-ups for sideband signals (`MAST_PRESENT#`, `MAST_INT#`, `MAST_RESET#`) | KiCad std (`Device:R`) | 10 kΩ | +| | I²C pull-ups for `MAST_I2C_*` | KiCad std (`Device:R`) | 4.7 kΩ | + +### P6 — USB-UART debug + JTAG + +| Ref | Part | Source | Status | +|---|---|---|---| +| U3 | FTDI FT232HL (LQFP-48) | **SnapEDA** | FTDI publishes KiCad symbols via Ultra-Librarian; SnapEDA mirrors. | +| J4 | Micro-USB B receptacle | KiCad std (`Connector:USB_B_Micro`) | KiCad ships canonical Micro-USB symbols and footprints | +| | ESD diode array on USB D± | **SnapEDA** | TPD2E001 or USBLC6-2SC6 — both are stock SnapEDA | +| J5 | JTAG 2x5 0.05" pitch shrouded header | KiCad std (`Connector:Conn_02x05_Odd_Even`) | KiCad ships the canonical 2x5 SMD JTAG footprint | +| | FT232HL decoupling, ferrite bead | KiCad std (`Device:C`, `Device:FerriteBead`) | | + +### P7 — Power tree + +| Ref | Part | Source | Status | +|---|---|---|---| +| J6 | Molex KK254 4-pin power input | KiCad std (`Connector:Conn_01x04`) | KK254 footprint in `Connector_Molex.pretty` | +| | Buck regulator ICs (placeholder — exact part deferred to placement) | **Ultra-Librarian** mirrored via TI / Analog Devices product pages | both TI and ADI publish KiCad-compatible symbols; pull-at-placement | +| | LDO for 0.675 V VTT (TPS51200 or alternative) | **SnapEDA** / **Ultra-Librarian** | shared with P3 (the VTT generator could live on either page; placement decides) | +| | Inductors (1 µH–22 µH, low-DCR power inductors) | KiCad std (`Device:L`) | exact value follows regulator selection | +| | Bulk + ceramic caps for 7 rails | KiCad std (`Device:C`, `Device:CP`) | | +| | TVS clamp (SMBJ15A or SMAJ15A) | **SnapEDA** | | +| | Power-good IC (TPS65086 or LTC2937) optional | **Ultra-Librarian** | optional component; deferred | +| | Sequencing logic (3-input AND `74LVC1G11` or PMIC-internal) | KiCad std (`74xx:74LVC1G11`) | KiCad has the 74xx family stocked | + +### P8 — Boot flash + +| Ref | Part | Source | Status | +|---|---|---|---| +| U4 | Cypress S25FL128SAGMFI001 (128 Mb quad-SPI NOR, SOIC-8) | **SnapEDA** | well-stocked symbol; SOIC-8 footprint is KiCad std | +| | SPI bus pull-ups | KiCad std (`Device:R`) | 10 kΩ on CS#, HOLD# | +| | Decoupling caps | KiCad std (`Device:C`) | | + +## Hand-authored symbols — authoring rules + +When a symbol is hand-authored (per the table above: U1 ECP5, +optionally U2 88E1512), the following rules apply, codified in +the project's symbol-template file (lands with PR #6c): + +1. **Pin numbering** matches the package datasheet exactly. +2. **Pin name** matches the datasheet's pin name (do not abbreviate). +3. **Pin type** classification: + - Power pins: `power_in`. + - Ground pins: `power_in`, named `GND`. + - Configuration pins: `input` if always driven, `bidirectional` + if can be both input and output. + - Reserved pins: `unconnected` (KiCad ERC will then complain + loudly if anyone wires to them). +4. **Symbol field `Description`** cites the datasheet section that + was the source: e.g. `FPGA-DS-02012-3.3 §4.2 BG756 pinout + (2024-Q4)`. +5. **Symbol field `Datasheet`** is a stable URL (Lattice document + number + version) so future editors can re-fetch the source. +6. **Multi-unit split**: power, IO bank, SerDes, configuration each + on their own unit, in that order. + +## Footprint inventory (paired with symbol inventory) + +Every symbol above maps to one of these footprint sources: + +- **KiCad std `*.pretty`** — `Resistor_SMD`, `Capacitor_SMD`, + `Inductor_SMD`, `Connector_USB`, `Connector_PinHeader_2.54mm`, + `Connector_Molex`, `Package_BGA`, `Package_QFP`, `Package_SO`. +- **SnapEDA-provided footprints** — paired with the symbol; + cross-checked against the datasheet land pattern recommendation + before merge. Ball-pad / pad-stack adjustments (for JLCPCB + fab-class minimum trace/space) recorded inline. +- **Hand-authored** (only U1 BG756 if no vendor footprint passes + cross-check) — author from the IPC-7351B nominal land pattern + using the BG756 package mechanical drawing in FPGA-DS-02012-3.3 + §3.5. + +## Cross-checks before any vendor symbol is merged + +Each placement PR that pulls a SnapEDA / Ultra-Librarian symbol +must run these checks in the PR description: + +1. **Pin count + pin order** — visually compare every pin against + the published datasheet pinout. +2. **Pin type** — check power, ground, NC, IO, OD pins are typed + correctly so KiCad ERC catches violations. +3. **Footprint land pattern** — overlay the imported footprint on + the datasheet's recommended land pattern and confirm to within + IPC-7351B Class B (general) or Class C (high-reliability) + tolerance. +4. **3D model** — if SnapEDA ships a STEP file, render it in KiCad + 3D viewer and confirm height + orientation match datasheet. +5. **License attribution** — if SnapEDA / Ultra-Librarian license + requires attribution, record it in the PR description and the + symbol's `Description` field. + +## What this doc deliberately does **not** do + +- **Vendor any symbols.** All symbol files land in the placement + PRs that use them. This doc is a manifest only. +- **Pick exact regulator parts.** P7's placement PR authors the + regulator decision matrix. +- **Author the ECP5 symbol.** That happens in PR #6c when the FPGA + page is placed. This doc commits to the *strategy* of + hand-authoring it. +- **Mandate a specific SnapEDA account.** The cooperative's + account is one option; any contributor may pull symbols under + their own account as long as the SnapEDA EULA's attribution + requirement is honoured. + +## References + +- ADR-001 — [`../adr/0001-fpga-target.md`](../adr/0001-fpga-target.md) +- Schematic page breakdown — + [`schematic-page-breakdown.md`](schematic-page-breakdown.md) +- Decoupling topology — + [`decoupling-topology.md`](decoupling-topology.md) +- DDR3L decision — [`ddr3l-decision.md`](ddr3l-decision.md) +- KiCad 8 library file format — `sym-lib-table` v7 spec. +- IPC-7351B — Generic Requirements for Surface Mount Design and + Land Pattern Standard. +- JEDEC MO-244 — DDR3 / DDR3L SO-DIMM mechanical / pinout. +- Lattice **FPGA-DS-02012-3.3** — ECP5 / ECP5-5G Family Data Sheet. +- SnapEDA EULA — https://www.snapeda.com/about/terms/ (attribution + + redistribution terms — checked at every symbol pull). +- Ultra-Librarian terms-of-use — https://www.ultralibrarian.com/. +- CERN-OHL-S v2 — project hardware licence. + +Authored by Agent 2 (FPGA Hardware). diff --git a/kicad/innerjib7ea-rev-a/README.md b/kicad/innerjib7ea-rev-a/README.md index 056d1ba..9b184a7 100644 --- a/kicad/innerjib7ea-rev-a/README.md +++ b/kicad/innerjib7ea-rev-a/README.md @@ -77,13 +77,32 @@ one PR per step: contributor workstation; the CI `kicad-erc-drc` job is the round-trip authority and runs `kicad-cli sch erc` and `kicad-cli pcb drc` on the PR. -2. **Schematic capture.** ECP5-85F symbol; full power tree - (12 V → 3.3 V / 2.5 V / 1.8 V / 1.35 V / 1.0 V / 0.675 V, - including the 2.5 V analog and 1.0 V digital rails for the - SGMII PHY); GbE chain (LiteEth → ECP5 SerDes → KSZ9031RNX SGMII - PHY → magnetics → RJ45); JTAG header; USB-UART bridge. - **Note:** the 1.5 V DDR3 main rail and 0.75 V VTT termination - (which earlier drafts of this list assumed) are removed — see +2. **Schematic capture.** Multi-week effort split into one PR per + schematic page for reviewability. Day-1 planning artefacts (the + contract that the placement PRs honour) live in: + - [`../../docs/hw/schematic-page-breakdown.md`](../../docs/hw/schematic-page-breakdown.md) + — the eight pages (P1 block diagram, P2 ECP5-85F core, P3 + DDR3L SO-DIMM, P4 GbE host link, P5 inter-card connector, P6 + USB-UART debug + JTAG, P7 power tree, P8 boot flash) and what + each page owns. + - [`../../docs/hw/symbol-library-inventory.md`](../../docs/hw/symbol-library-inventory.md) + — every symbol by source: KiCad std libs vs vendor (Lattice + / SnapEDA / Ultra-Librarian) vs hand-authored. + - [`../../docs/hw/decoupling-topology.md`](../../docs/hw/decoupling-topology.md) + — per-rail decoupling spec for the ECP5-85F per FPGA-TN-02038 + and FPGA-TN-02206 (bulk + bypass + SerDes-specific filter). + Topology only; exact counts deferred to placement. + + Power tree summary (12 V → 3.3 V / 2.5 V / 1.8 V / 1.35 V / + 1.20 V / 1.0 V / 0.675 V, including the 2.5 V analog and 1.0 V + digital rails for the SGMII PHY); GbE chain (LiteEth → ECP5 + SerDes → SGMII PHY → magnetics → RJ45); JTAG header; USB-UART + bridge. Day-1 planning selects **Marvell 88E1512** as the + primary SGMII PHY (KSZ9031RNX is the documented substitute) and + **FT232HL** as the primary USB-UART bridge (CP2102N is the + documented cost-down substitute). **Note:** the 1.5 V DDR3 main + rail and 0.75 V VTT termination (which earlier drafts of this + list assumed) are removed — see [`../../docs/hw/ddr3l-decision.md`](../../docs/hw/ddr3l-decision.md); rev-A is DDR3L only, so the module rail is 1.35 V and VTT is 0.675 V (VDD/2).