diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml
index edeadd0..5cf79a1 100644
--- a/.github/workflows/build.yaml
+++ b/.github/workflows/build.yaml
@@ -37,6 +37,7 @@ jobs:
 
           make_platform stm32f4discovery
           make_platform nucleo-f767zi
+          make_platform nucleo-f207zg
 
     - name: Build for emulation on QEMU
       shell: nix develop .#ci -c bash -e {0}
diff --git a/flake.nix b/flake.nix
index 9776601..136c18d 100644
--- a/flake.nix
+++ b/flake.nix
@@ -19,7 +19,7 @@
       perSystem = { pkgs, ... }:
         let
           libopencm3 = pkgs.callPackage ./libopencm3.nix {
-            targets = [ "stm32/f4" "stm32/f7" ];
+            targets = [ "stm32/f2" "stm32/f4" "stm32/f7" ];
           };
           core = builtins.attrValues {
             libopencm3 = libopencm3;
@@ -56,7 +56,7 @@
             shellHook = ''
               export OPENCM3_DIR=${libopencm3}
               export PATH=$PWD/scripts:$PWD/scripts/ci:$PATH
-              eval "$(_TESTS_COMPLETE=source tests)"
+              eval "$(_TESTS_COMPLETE=bash_source tests)"
             '';
           };
 
diff --git a/hal/hal-opencm3.c b/hal/hal-opencm3.c
index c784c8b..bdc92eb 100644
--- a/hal/hal-opencm3.c
+++ b/hal/hal-opencm3.c
@@ -12,7 +12,15 @@
 #include <libopencm3/stm32/usart.h>
 #include <libopencm3/stm32/flash.h>
 
-#if defined(STM32F407VG)
+#if defined(STM32F207ZG)
+#include <libopencm3/stm32/rng.h>
+
+#define SERIAL_GPIO GPIOD
+#define SERIAL_USART USART3
+#define SERIAL_PINS (GPIO8 | GPIO9)
+#define STM32
+#define NUCLEO_BOARD
+#elif defined(STM32F407VG)
 #include <libopencm3/stm32/rng.h>
 #define SERIAL_GPIO GPIOA
 #define SERIAL_USART USART2
@@ -91,13 +99,70 @@ static void clock_setup(enum clock_mode clock) {
     rcc_periph_clock_enable(RCC_RNG);
     flash_art_enable();
     flash_prefetch_enable();
+    #elif defined(STM32F2)
+    /* Some STM32 Platform */
+    rcc_periph_clock_enable(RCC_RNG);
+    rcc_periph_clock_enable(RCC_GPIOH);
+    /* All of them use an external oscillator with bypass. */
+    rcc_osc_off(RCC_HSE);
+    rcc_osc_bypass_enable(RCC_HSE);
+    rcc_osc_on(RCC_HSE);
+    rcc_wait_for_osc_ready(RCC_HSE);
+    # if defined(NUCLEO_BOARD)
+    /* NUCLEO-STM32F2 Board */
+    switch (clock) {
+    case CLOCK_BENCHMARK:
+        rcc_ahb_frequency = 30000000;
+        rcc_apb1_frequency = 30000000;
+        rcc_apb2_frequency = 30000000;
+        _clock_freq = 30000000;
+        rcc_set_hpre(RCC_CFGR_HPRE_DIV_4);
+        rcc_set_ppre1(RCC_CFGR_PPRE_DIV_NONE);
+        rcc_set_ppre2(RCC_CFGR_PPRE_DIV_NONE);
+        rcc_osc_off(RCC_PLL);
+        /* Configure the PLL oscillator (use CUBEMX tool). */
+        rcc_set_main_pll_hse(8, 240, 2, 5);
+        /* Enable PLL oscillator and wait for it to stabilize. */
+        rcc_osc_on(RCC_PLL);
+        rcc_wait_for_osc_ready(RCC_PLL);
+        flash_dcache_enable();
+        flash_icache_enable();
+        flash_set_ws(FLASH_ACR_LATENCY_0WS);
+        flash_prefetch_enable();
+        break;
+    case CLOCK_FAST:
+    default:
+        rcc_ahb_frequency = 120000000;
+        rcc_apb1_frequency = 30000000;
+        rcc_apb2_frequency = 60000000;
+        _clock_freq = 120000000;
+        rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE);
+        rcc_set_ppre1(RCC_CFGR_PPRE_DIV_4);
+        rcc_set_ppre2(RCC_CFGR_PPRE_DIV_2);
+        rcc_osc_off(RCC_PLL);
+        /* Configure the PLL oscillator (use CUBEMX tool). */
+        rcc_set_main_pll_hse(8, 240, 2, 5);
+        /* Enable PLL oscillator and wait for it to stabilize. */
+        rcc_osc_on(RCC_PLL);
+        rcc_wait_for_osc_ready(RCC_PLL);
+        flash_dcache_enable();
+        flash_icache_enable();
+        flash_set_ws(FLASH_ACR_LATENCY_3WS);
+        flash_prefetch_enable();
+        break;
+    }
+    rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
+    rcc_wait_for_sysclk_status(RCC_PLL);
+    # else
+# error Unsupported STM32F2 Board
+    # endif
     #else
 #error Unsupported platform
     #endif
 }
 
 void usart_setup() {
-    #if defined(STM32F7)
+    #if defined(STM32F207ZG) || defined(STM32F7)
     rcc_periph_clock_enable(RCC_GPIOD);
     rcc_periph_clock_enable(RCC_USART3);
     #elif defined(DISCOVERY_BOARD)
diff --git a/hal/stm32f4discovery.cfg b/hal/nucleo_f207zg.cfg
similarity index 79%
rename from hal/stm32f4discovery.cfg
rename to hal/nucleo_f207zg.cfg
index 8f491f7..0949395 100644
--- a/hal/stm32f4discovery.cfg
+++ b/hal/nucleo_f207zg.cfg
@@ -3,6 +3,6 @@ source [find interface/stlink-dap.cfg]
 
 transport select dapdirect_swd
 
-source [find target/stm32f4x.cfg]
+source [find target/stm32f2x.cfg]
 
 reset_config trst_only
diff --git a/mk/nucleo-f207zg.mk b/mk/nucleo-f207zg.mk
new file mode 100644
index 0000000..37d48ed
--- /dev/null
+++ b/mk/nucleo-f207zg.mk
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+DEVICE=stm32f207zg
+OPENCM3_TARGET=lib/stm32/f2
+
+include mk/opencm3.mk
diff --git a/scripts/tests b/scripts/tests
index a7f3cd9..c383e6b 100755
--- a/scripts/tests
+++ b/scripts/tests
@@ -11,6 +11,7 @@ import click
 import logging
 import sys
 import re
+import os.path
 from enum import Enum
 from types import SimpleNamespace
 from functools import reduce
@@ -110,6 +111,7 @@ class PLATFORM(Enum):
     STM32F4DISCOVERY = 1
     MPS2_AN386 = 2
     NUCLEO_F767ZI = 3
+    NUCLEO_F207ZG = 4
 
     def __str__(self):
         return self.name.lower().replace("_", "-")
@@ -133,8 +135,12 @@ class RecursiveNamespace(SimpleNamespace):
                 setattr(self, key, list(map(self.map_entry, val)))
 
 
+ROOT = os.path.dirname(os.path.dirname(__file__))
 platform_map = RecursiveNamespace(
     **{
+        f"{PLATFORM.NUCLEO_F207ZG}": {
+            "openocd_cfg": f"{ROOT}/hal/nucleo_f207zg.cfg",
+        },
         f"{PLATFORM.STM32F4DISCOVERY}": {
             "openocd_cfg": "board/stm32f4discovery.cfg",
         },