another release with complete hw design (still with older RISC-V priv…

… spec)

Makefile

@@ -57,8 +57,7 @@ include config.mk
 
 # Construct core configuration string (used for directory naming).
 # Note: '?=' not used so string is only constructed once.
-CORE_CONFIG := $(THREADS)tf-$(ISPM_KBYTES)i-$(DSPM_KBYTES)d
-#CORE_CONFIG := $(THREADS)t$(if $(findstring true, $(FLEX)),f)-$(ISPM_KBYTES)i-$(DSPM_KBYTES)d-$(MUL_STAGES)smul$(if $(findstring true, $(STATS)),-stats)$(if $(findstring true, $(EXCEPTIONS)),-exc)$(if $(findstring true, $(GET_TIME)),-gt)$(if $(findstring true, $(DELAY_UNTIL)),-du)$(if $(findstring true, $(EXCEPTION_ON_EXPIRE)),-ee)
+CORE_CONFIG := $(THREADS)t$(if $(findstring true, $(FLEXPRET)),f)-$(ISPM_KBYTES)i-$(DSPM_KBYTES)d$(if $(findstring true, $(MUL)),-mul)-$(SUFFIX)
 
 # Default will build target and selected programs.
 all: $(TARGET)
@@ -117,26 +116,20 @@ prog: $(PROG:%=$(PROG_BUILD_DIR)/%.inst.mem) $(PROG:%=$(PROG_BUILD_DIR)/%.data.m
 
 ifeq ($(TARGET),emulator)
 
-# TODO: force STATS=true?
-# TODO: debug?
-#MAX_CYCLES ?= 20000000
-MAX_CYCLES ?= 200000
+MAX_CYCLES ?= 20000000
 ifeq ($(DEBUG), true)
-CONFIG = $(CORE_CONFIG)-debug
-SBT_ARGS = --debug --vcd
-SIM_DEBUG = --vcd=$(@:%.out=%.vcd)
 else
-CONFIG = $(CORE_CONFIG)
+SIM_DEBUG = --vcdstart=$(MAX_CYCLES)
 endif
 
 $(PROG:%=$(PROG_RESULTS_DIR)/%.out): $(PROG_RESULTS_DIR)/%.out: $(PROG_BUILD_DIR)/%.inst.mem $(PROG_BUILD_DIR)/%.data.mem $(EMULATOR)
 	mkdir -p $(PROG_RESULTS_DIR)
-	./$(EMULATOR) --maxcycles=$(MAX_CYCLES) --ispm=$(PROG_BUILD_DIR)/$*.inst.mem --dspm=$(PROG_BUILD_DIR)/$*.data.mem --vcd=$(@:.out=.vcd) > $@ 2>&1
+	./$(EMULATOR) --maxcycles=$(MAX_CYCLES) --ispm=$(PROG_BUILD_DIR)/$*.inst.mem --dspm=$(PROG_BUILD_DIR)/$*.data.mem --vcd=$(@:.out=.vcd) $(SIM_DEBUG) $(EMULATOR_OPTS) > $@ 2>&1
 	echo $@ $^
 
 # Possible targets are emulator and fpga.
 run: $(PROG:%=$(PROG_RESULTS_DIR)/%.out)
-	@echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+	@echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.*)\*{3}(.*)/' \
 	$^; echo;
 
 CLEAN_TARGET = $(EMULATOR_SRC_DIR) $(EMULATOR_BUILD_DIR) $(PROG_RESULTS_DIR) $(PROG_BUILD_DIR)
@@ -150,15 +143,13 @@ endif
 clean:
 	rm -rf $(CLEAN_TARGET)
 
-#rm -rf $(PROG_BUILD_DIR) $(CLEAN_TARGET)
 
 # Clean for all configurations and targets.
 cleanall:
 	rm -rf $(EMULATOR_DIR)/generated-src
 	rm -rf $(EMULATOR_DIR)/build
 	rm -rf $(FGPA_DIR)/generated-src
-	find $(TESTS_DIR) -type d -name "results" -exec rm -rf {} \;
-
-#find $(TESTS_DIR) -type d -name "build" -exec rm -rf {} \;
+	find $(TESTS_DIR) -type d -name "results" -exec rm -rf {} \; \
+		find $(TESTS_DIR) -type d -name "build" -exec rm -rf {} \;
 
 .PHONY: run emulator fpga prog clean cleanall

README.md

@@ -5,6 +5,9 @@ This README will not be completely correct while this branch is under developmen
 `make run` should compile the ISA test suite and run it on the C++ emulator
 generated by Chisel.
 
+RISC-V toolchain version:
+https://github.com/riscv/riscv-gnu-toolchain/commit/9a8a0aa98571c97291702e2e283fc1056f3ce2e2
+
 FlexPRET
 ================================================================================
 __FlexPRET__ is a 5-stage, fine-grained multithreaded [RISC-V*](http://riscv.org) processor designed specifically for _mixed-criticality (real-time embedded) systems_ and written in [Chisel**](https://chisel.eecs.berkeley.edu/). A hardware thread scheduler decides which hardware thread to start executing each cycle, regulated by configuration and status registers. Each hardware thread is either classified as a _hard real-time thread (HRTT)_ or _soft real-time thread (SRTT)_: HRTTs are only scheduled at a constant rate for _hardware-based isolation and predictability_ (enabling independent formal verification), and SRTTs share remaining cycles (including when a HRTT doesn't need prescribed cycles) for _efficient processor utilization_. For comparison purposes, both single-threaded and round-robin multithreaded 5-stage RISC-V processors can also be generated. FlexPRET is developed at UC Berkeley as part of the [PRET](http://chess.eecs.berkeley.edu/pret/) project.

config.mk

@@ -7,36 +7,31 @@
 # FLEXPRET=[true/false]: Use flexible thread scheduling
 # ISPM_KBYTES=[]: Size of instruction scratchpad memory (32 bit words)
 # DSPM_KBYTES=[]: Size of instruction scratchpad memory (32 bit words)
-# STATS=[true/false]: Count instructions and cycles for each thread
-# EXCEPTIONS=[true/false]: Allow exception to interrupt execution
-# GET_TIME=[true/false]: Enable instruction to get current time in nanoseconds
-# DELAY_UNTIL=[true/false]: Enable instruction to stall until future time
-# EXCEPTION_ON_EXPIRE=[true/false]: Enable instruction to interrupt execution at certain time
+# MUL=[true/false]: multiplier
+# SUFFIX=[min,ex,ti,all]:
+# 	min: base RV32I
+# 	ex: min+exceptions (necessary)
+# 	ti: ex+timing instructions
+# 	all: ti+ all exception causes and stats
 
 THREADS ?= 4
-#FLEX ?= true
+FLEXPRET ?= true
 ISPM_KBYTES ?= 16
 DSPM_KBYTES ?= 16
-#MUL_STAGES ?= 2
-#STATS ?= false
-EXCEPTIONS ?= false
-#GET_TIME ?= false
-#DELAY_UNTIL ?= false
-#EXCEPTION_ON_EXPIRE ?= false
+MUL ?= false
+SUFFIX ?= ti
 
 # Target
-# TARGET=[emulator/fpga]: Select default target
+# TARGET=[emulator/fpga]: Select target
 # DEBUG=[true/false]: Generate waveform dump.
 TARGET ?= emulator
 DEBUG ?= true
 
 # Default program compilation
 # PROG_DIR=[path]: Directory of programs in tests/ to compile and/or run
 # PROG_CONFIG=[]: Program configuration, start with target name
-#PROG_DIR ?= complex-mc
-#PROG_DIR ?= simple-mc
-#PROG_DIR = examples
 PROG_DIR ?= isa
+#PROG_DIR = examples
 PROG_CONFIG ?= $(TARGET)