A bare-metal pure hardware implementation of the Tetris game for FPGA
VHDL Batchfile
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PLL.ppf
PLL.qip
PLL.vhd
README.md
Tetris_Controller.vhd
Tetris_DE1.qpf
Tetris_DE1.qsf
Tetris_DE1.sdc
Tetris_DE1.srf
Tetris_DE1.vhd
Tetris_Datapath.vhd
Tetris_View.vhd
VGA_FrameBuffer.vhd
VGA_RAMDAC.vhd
VGA_Timing.vhd
clean.bat
ram.qip
tetris_package.vhd
vga_package.vhd

README.md

Tetris-VHDL is a bare-metal pure hardware implementation of the Tetris game for FPGA

This project has been developed while teaching a course of laboratory of digital systems in University of Bologna and is intended as a drive-through use case for basic hardware design principles and common VHDL patterns. The VHDL code is not particularly platform specific, however the entire project is tested and guaranteed to run on Altera DE1 development boards.

Teaching material

Together with the VHDL of the project itself, I wrote down to the years some teaching material related to the project. Unfortunately, at the moment, the slides are available only in Italian.

License

The applications are released under the terms of the GNU GPL