Tetris-VHDL is a bare-metal pure hardware implementation of the Tetris game for FPGA
This project has been developed while teaching a course of laboratory of digital systems in University of Bologna and is intended as a drive-through use case for basic hardware design principles and common VHDL patterns. The VHDL code is not particularly platform specific, however the entire project is tested and guaranteed to run on Altera DE1 development boards.
Together with the VHDL of the project itself, I wrote down to the years some teaching material related to the project. Unfortunately, at the moment, the slides are available only in Italian.
- Introduction to FPGAs, design principles and quick VHDL summary
- Introduction to the DE1 FPGAs board and Altera development environment
- Introduction to Tetris projects: requirements and architecture
- Tetris project: data-path architecture and RTL VHDL
- Tetris project: user interface and VGA framebuffer
- Tetris project: control unit
The applications are released under the terms of the GNU GPL