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3C120_uart_comm_Test UART Comm module added. Work in progress.
BeMicro Added project for BeMicro SDK.
DE2_115_NIOS_Ethernet_Test Cleaned out DE2_115_NIOS_Ethernet project.
DE2_115_Unoptimized_Pipelined Reorganizing directory structure and cleaning some of the old project…
DE2_115_makomk_mod Many improvements to the Altera mining script. Split pool information…
DE2_115_makomk_serial startup message
DE2_70_Unoptimized_Pipelined Added a DE2-70 compatible project, and a little work on BSCAN_SPARTAN…
KC705_experimental Removed WebTalk data from KC705_experimental project.
Kintex7_160T_experimental Forgot to add a note to the Kintex7_160T_experimental project. Code i…
LX150_Test Added LX150_makomk_Test. Tests makomk's code on a Xilinx Spartan 6 LX…
LX150_comm_Test Tweaked comments.
LX150_comm_tweaks Another code rev for the X6000 boards.
LX150_makomk_Test Working on a new JTAG communication method for Spartan-6 devices. See…
LX150_makomk_dualcore Created an experimental dual-core miner.
LX150_makomk_multicore_Test Added LX150_makomk_multicore_Test project, which attempts to fit two …
LX150_makomk_speed_Test Reorganizing directory structure and cleaning some of the old project…
VC707_experimental Fix for the VC707 project. UART pins were backwards. Firmware appears…
VHDL_StratixIV_OrphanedGland Removed the greybox_tmp folder, which is Quartus generated temporary …
VHDL_Xilinx_Port Added VHDL re-implementation by TheSeven.
Verilog_Xilinx_Port Updated the TODO list in Verilog_Xilinx_Port/README.md
X5000_ztexmerge Reorganizing directory structure and cleaning some of the old project…
X6000_ztex_comm4 Patched checksum calculation for multi-FPGA device chains in jtag_comm.v
README.md Directory structure reorganized to better suit storing multiple varia…

README.md

These folders contain many different projects, each with different approaches to FPGA mining. Different types of SHA-256 designs, optimized versions, built-in controller versions, and different target platforms.

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