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Just experimenting with Open Source SoCs on my Altera dev kit.
Verilog C Assembly
branch: master

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boards/C120/rtl
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README.md
lm32_test.qpf
lm32_test.qsf
lm32_test.sdc
stp1.stp

README.md

Experimentation with Open Source SoCs on an Altera FPGA.

Uses numerous components from Milkymist SoC. http://milkymist.org

Currently uses:

  • LM32 CPU core
  • Wishbone BUS
  • CSR BUS
  • GDBstub for debugging
  • JTAG Atlantic for a JTAG-UART bridge
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