diff --git a/src/main/scala/riscv/Core.scala b/src/main/scala/riscv/Core.scala
index 7fc29ea..23d69ec 100644
--- a/src/main/scala/riscv/Core.scala
+++ b/src/main/scala/riscv/Core.scala
@@ -297,7 +297,7 @@ object CoreDynamicSim {
 
 object CoreDynamicExtMem {
   def main(args: Array[String]) {
-    SpinalVerilog(SoC.dynamic(RamType.ExternalAxi4(10 MiB), 32))
+    SpinalVerilog(SoC.dynamic(RamType.ExternalAxi4(10 MiB), 64))
   }
 }