Implemented 32-bit MIPS processor in Verilog, integrating gate-level, dataflow & behavioral modeling techniques. Orchestrated a 5-stage pipeline architecture encompassing stages like Instruction Fetch, Decode, Execute, Memory Access, and Writeback, effectively optimizing processor performance.
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Implemented 32-bit MIPS processor in Verilog,integrating gate-level,dataflow & behavioral modeling techniques – Orchestrated a 5-stage pipeline architecture encompassing stages like Instruction Fetch, Decode, Execute, Memory Access, and Writeback, effectively optimizing processor performance.
psjsptcoder/Design_and_Simulation_of_32-bit_MIPS_Processor
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Implemented 32-bit MIPS processor in Verilog,integrating gate-level,dataflow & behavioral modeling techniques – Orchestrated a 5-stage pipeline architecture encompassing stages like Instruction Fetch, Decode, Execute, Memory Access, and Writeback, effectively optimizing processor performance.
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