diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def index 8cc765eab1de8..88fef105f7fd0 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.def +++ b/clang/include/clang/Basic/BuiltinsRISCV.def @@ -148,22 +148,22 @@ TARGET_BUILTIN(__builtin_pulp_CoreId, "i", "n", "xpulpv") TARGET_BUILTIN(__builtin_pulp_ClusterId, "i", "n", "xpulpv") TARGET_BUILTIN(__builtin_pulp_IsFc, "i", "n", "xpulpv") TARGET_BUILTIN(__builtin_pulp_HasFc, "i", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mac, "iiii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_machhs, "iiii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_machhu, "UiUiUii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_macs, "iiii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_macu, "UiUiUii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_msu, "iiii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_bset, "iiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_bset_r, "iiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_clb, "ii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_cnt, "ii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_ff1, "ii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_fl1, "ii", "nc", "xpulpv") +TARGET_BUILTIN(__builtin_pulp_mac, "iiii", "nc", "xpulpv|xpulpmacsi") +TARGET_BUILTIN(__builtin_pulp_msu, "iiii", "nc", "xpulpv|xpulpmacsi") +TARGET_BUILTIN(__builtin_pulp_machhs, "iiii", "nc", "xpulpv|xpulppartmac") +TARGET_BUILTIN(__builtin_pulp_machhu, "UiUiUii", "nc", "xpulpv|xpulppartmac") +TARGET_BUILTIN(__builtin_pulp_macs, "iiii", "nc", "xpulpv|xpulppartmac") +TARGET_BUILTIN(__builtin_pulp_macu, "UiUiUii", "nc", "xpulpv|xpulppartmac") +TARGET_BUILTIN(__builtin_pulp_bset, "iiUIi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_bset_r, "iiUi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_clb, "ii", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_cnt, "ii", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_ff1, "ii", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_fl1, "ii", "nc", "xpulpv|xpulpbitop") TARGET_BUILTIN(__builtin_pulp_parity, "ii", "nc", "xpulpv") TARGET_BUILTIN(__builtin_pulp_rotr, "iii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_read_base_off, "ii*i", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_write_base_off, "vii*i", "n", "xpulpv") +TARGET_BUILTIN(__builtin_pulp_read_base_off, "ii*i", "n", "xpulpv|xpulppostmod") +TARGET_BUILTIN(__builtin_pulp_write_base_off, "vii*i", "n", "xpulpv|xpulppostmod") TARGET_BUILTIN(__builtin_pulp_read_base_off_v, "ii*i", "n", "xpulpv") TARGET_BUILTIN(__builtin_pulp_write_base_off_v, "vii*i", "n", "xpulpv") TARGET_BUILTIN(__builtin_pulp_read_then_spr_bit_clr, "iIiIi", "n", "xpulpv") @@ -174,130 +174,130 @@ TARGET_BUILTIN(__builtin_pulp_spr_bit_set, "vIiIi", "n", "xpulpv") TARGET_BUILTIN(__builtin_pulp_spr_read, "iIi", "n", "xpulpv") TARGET_BUILTIN(__builtin_pulp_spr_read_vol, "iIi", "n", "xpulpv") TARGET_BUILTIN(__builtin_pulp_spr_write, "vIii", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_event_unit_read, "Uii*Ui", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_abs, "Uii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_addN, "iiiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_addN_r, "iiiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_addRN, "iiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_addRN_r, "UiiiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_adduN, "UiUiUiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_adduN_r, "UiUiUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_adduRN, "UiUiUiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_adduRN_r, "UiUiUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_clip, "iiIiIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_clip_r, "iii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_clipu, "UiiIiIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_clipu_r, "UiiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_maxsi, "iii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_machhsN, "iiiiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_machhsRN, "iiiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_machhuN, "UiUiUiiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_machhuRN, "UiUiUiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_macsN, "iiiiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_macsRN, "iiiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_macuN, "UiUiUiiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_macuRN, "UiUiUiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_maxusi, "UiUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_minsi, "iii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_minusi, "UiUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulhhs, "iii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulhhsN, "iiiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulhhsRN, "iiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulhhu, "UiUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulhhuN, "UiUiUiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulhhuRN, "UiUiUiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_muls, "iii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulsN, "iiiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulsRN, "iiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_mulu, "UiUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_muluN, "UiUiUiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_muluRN, "UiUiUiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_subN, "iiiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_subN_r, "iiiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_subRN, "iiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_subRN_r, "UiUiUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_subuN, "UiUiUiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_subuN_r, "UiUiUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_subuRN, "UiUiUiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_subuRN_r, "UiiiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_bclr, "iiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_bclr_r, "iiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_bextract, "iiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_bextract_r, "iiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_bextractu, "iiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_bextractu_r, "iiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_binsert, "iiUIiiUIiUIi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_binsert_r, "iiiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotsp2, "iV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotsp4, "iV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotspsc2, "iV2si", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotspsc4, "iV4ci", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotup2, "UiUV2sUV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotup4, "UiUV4cUV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotupsc2, "UiUV2sUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotupsc4, "UiUV4cUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotusp2, "iUV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotusp4, "iUV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotuspsc2, "iUV2si", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_dotuspsc4, "iUV4ci", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotsp2, "iV2sV2si", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotsp4, "iV4cV4ci", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotspsc2, "iV2sii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotspsc4, "iV4cii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotup2, "UiUV2sUV2sUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotup4, "UiUV4cUV4cUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotupsc2, "UiUV2sUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotupsc4, "UiUV4cUiUi", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotusp2, "iUV2sV2si", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotusp4, "iUV4cV4ci", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotuspsc2, "iUV2sii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sdotuspsc4, "iUV4cii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_abs2, "UV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_abs4, "UV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_add2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_add4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_and2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_and4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_avg2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_avg4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_avgu2, "V2sUV2sUV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_avgu4, "V4cUV4cUV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_exor2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_exor4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_max2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_max4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_maxu2, "UV2sUV2sUV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_maxu4, "UV4cUV4cUV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_min2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_min4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_minu2, "UV2sUV2sUV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_minu4, "UV4cUV4cUV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_neg2, "V2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_neg4, "V4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_or2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_or4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sll2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sll4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sra2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sra4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_srl2, "UV2sUV2sUV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_srl4, "UV4cUV4cUV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sub2, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_sub4, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_pack2, "V2sii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_pack4, "V4ciiii", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_pack4_hi, "V4ciiV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_pack4_lo, "V4ciiV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_shuffle2h, "V2sV2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_shuffle4b, "V4cV4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_shuffleh, "V2sV2sV2s", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_shuffleb, "V4cV4cV4c", "nc", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_OffsetedRead, "ii*i", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_OffsetedReadByte, "ic*i", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_OffsetedReadHalf, "is*i", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_OffsetedWrite, "vii*i", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_OffsetedWriteByte, "vic*i", "n", "xpulpv") -TARGET_BUILTIN(__builtin_pulp_OffsetedWriteHalf, "vis*i", "n", "xpulpv") +TARGET_BUILTIN(__builtin_pulp_event_unit_read, "Uii*Ui", "n", "xpulpv|xpulpelw") +TARGET_BUILTIN(__builtin_pulp_abs, "Uii", "nc", "xpulpv|xpulpabs") +TARGET_BUILTIN(__builtin_pulp_addN, "iiiUIi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_addN_r, "iiiUi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_addRN, "iiiUIiUIi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_addRN_r, "UiiiUi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_adduN, "UiUiUiUIi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_adduN_r, "UiUiUiUi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_adduRN, "UiUiUiUIiUIi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_adduRN_r, "UiUiUiUi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_clip, "iiIiIi", "nc", "xpulpv|xpulpclip") +TARGET_BUILTIN(__builtin_pulp_clip_r, "iii", "nc", "xpulpv|xpulpclip") +TARGET_BUILTIN(__builtin_pulp_clipu, "UiiIiIi", "nc", "xpulpv|xpulpclip") +TARGET_BUILTIN(__builtin_pulp_clipu_r, "UiiUi", "nc", "xpulpv|xpulpclip") +TARGET_BUILTIN(__builtin_pulp_machhsN, "iiiiUIi", "nc", "xpulpv|xpulpmacrnhi") +TARGET_BUILTIN(__builtin_pulp_machhsRN, "iiiiUIiUIi", "nc", "xpulpv|xpulpmacrnhi") +TARGET_BUILTIN(__builtin_pulp_machhuN, "UiUiUiiUIi", "nc", "xpulpv|xpulpmacrnhi") +TARGET_BUILTIN(__builtin_pulp_machhuRN, "UiUiUiiUIiUIi", "nc", "xpulpv|xpulpmacrnhi") +TARGET_BUILTIN(__builtin_pulp_macsN, "iiiiUIi", "nc", "xpulpv|xpulpmacrnhi") +TARGET_BUILTIN(__builtin_pulp_macsRN, "iiiiUIiUIi", "nc", "xpulpv|xpulpmacrnhi") +TARGET_BUILTIN(__builtin_pulp_macuN, "UiUiUiiUIi", "nc", "xpulpv|xpulpmacrnhi") +TARGET_BUILTIN(__builtin_pulp_macuRN, "UiUiUiiUIiUIi", "nc", "xpulpv|xpulpmacrnhi") +TARGET_BUILTIN(__builtin_pulp_maxsi, "iii", "nc", "xpulpv|xpulpminmax") +TARGET_BUILTIN(__builtin_pulp_maxusi, "UiUiUi", "nc", "xpulpv|xpulpminmax") +TARGET_BUILTIN(__builtin_pulp_minsi, "iii", "nc", "xpulpv|xpulpminmax") +TARGET_BUILTIN(__builtin_pulp_minusi, "UiUiUi", "nc", "xpulpv|xpulpminmax") +TARGET_BUILTIN(__builtin_pulp_mulhhs, "iii", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_mulhhsN, "iiiUIi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_mulhhsRN, "iiiUIiUIi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_mulhhu, "UiUiUi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_mulhhuN, "UiUiUiUIi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_mulhhuRN, "UiUiUiUIiUIi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_muls, "iii", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_mulsN, "iiiUIi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_mulsRN, "iiiUIiUIi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_mulu, "UiUiUi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_muluN, "UiUiUiUIi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_muluRN, "UiUiUiUIiUIi", "nc", "xpulpv|xpulpmulrnhi") +TARGET_BUILTIN(__builtin_pulp_subN, "iiiUIi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_subN_r, "iiiUi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_subRN, "iiiUIiUIi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_subRN_r, "UiUiUiUi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_subuN, "UiUiUiUIi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_subuN_r, "UiUiUiUi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_subuRN, "UiUiUiUIiUIi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_subuRN_r, "UiiiUi", "nc", "xpulpv|xpulpaddsubrn") +TARGET_BUILTIN(__builtin_pulp_bclr, "iiUIi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_bclr_r, "iiUi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_bextract, "iiUIiUIi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_bextract_r, "iiUi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_bextractu, "iiUIiUIi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_bextractu_r, "iiUi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_binsert, "iiUIiiUIiUIi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_binsert_r, "iiiUi", "nc", "xpulpv|xpulpbitop") +TARGET_BUILTIN(__builtin_pulp_dotsp2, "iV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotsp4, "iV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotspsc2, "iV2si", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotspsc4, "iV4ci", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotup2, "UiUV2sUV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotup4, "UiUV4cUV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotupsc2, "UiUV2sUi", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotupsc4, "UiUV4cUi", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotusp2, "iUV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotusp4, "iUV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotuspsc2, "iUV2si", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_dotuspsc4, "iUV4ci", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotsp2, "iV2sV2si", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotsp4, "iV4cV4ci", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotspsc2, "iV2sii", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotspsc4, "iV4cii", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotup2, "UiUV2sUV2sUi", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotup4, "UiUV4cUV4cUi", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotupsc2, "UiUV2sUiUi", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotupsc4, "UiUV4cUiUi", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotusp2, "iUV2sV2si", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotusp4, "iUV4cV4ci", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotuspsc2, "iUV2sii", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sdotuspsc4, "iUV4cii", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_abs2, "UV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_abs4, "UV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_add2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_add4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_and2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_and4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_avg2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_avg4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_avgu2, "V2sUV2sUV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_avgu4, "V4cUV4cUV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_exor2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_exor4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_max2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_max4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_maxu2, "UV2sUV2sUV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_maxu4, "UV4cUV4cUV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_min2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_min4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_minu2, "UV2sUV2sUV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_minu4, "UV4cUV4cUV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_neg2, "V2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_neg4, "V4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_or2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_or4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sll2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sll4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sra2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sra4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_srl2, "UV2sUV2sUV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_srl4, "UV4cUV4cUV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sub2, "V2sV2sV2s", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_sub4, "V4cV4cV4c", "nc", "xpulpv|xpulpvect") +TARGET_BUILTIN(__builtin_pulp_pack2, "V2sii", "nc", "xpulpv|xpulpvectshufflepack") +TARGET_BUILTIN(__builtin_pulp_pack4, "V4ciiii", "nc", "xpulpv|xpulpvectshufflepack") +TARGET_BUILTIN(__builtin_pulp_pack4_hi, "V4ciiV4c", "nc", "xpulpv|xpulpvectshufflepack") +TARGET_BUILTIN(__builtin_pulp_pack4_lo, "V4ciiV4c", "nc", "xpulpv|xpulpvectshufflepack") +TARGET_BUILTIN(__builtin_pulp_shuffle2h, "V2sV2sV2sV2s", "nc", "xpulpv|xpulpvectshufflepack") +TARGET_BUILTIN(__builtin_pulp_shuffle4b, "V4cV4cV4cV4c", "nc", "xpulpv|xpulpvectshufflepack") +TARGET_BUILTIN(__builtin_pulp_shuffleh, "V2sV2sV2s", "nc", "xpulpv|xpulpvectshufflepack") +TARGET_BUILTIN(__builtin_pulp_shuffleb, "V4cV4cV4c", "nc", "xpulpv|xpulpvectshufflepack") +TARGET_BUILTIN(__builtin_pulp_OffsetedRead, "ii*i", "n", "xpulpv|xpulppostmod") +TARGET_BUILTIN(__builtin_pulp_OffsetedReadByte, "ic*i", "n", "xpulpv|xpulppostmod") +TARGET_BUILTIN(__builtin_pulp_OffsetedReadHalf, "is*i", "n", "xpulpv|xpulppostmod") +TARGET_BUILTIN(__builtin_pulp_OffsetedWrite, "vii*i", "n", "xpulpv|xpulppostmod") +TARGET_BUILTIN(__builtin_pulp_OffsetedWriteByte, "vic*i", "n", "xpulpv|xpulppostmod") +TARGET_BUILTIN(__builtin_pulp_OffsetedWriteHalf, "vis*i", "n", "xpulpv|xpulppostmod") #undef BUILTIN #undef TARGET_BUILTIN diff --git a/clang/test/CodeGen/RISCV/riscv-xpulpmacsi-intrinsics-diag.c b/clang/test/CodeGen/RISCV/riscv-xpulpmacsi-intrinsics-diag.c new file mode 100644 index 0000000000000..3b49eb56f80bc --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv-xpulpmacsi-intrinsics-diag.c @@ -0,0 +1,11 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 %s -triple=riscv32 -verify -S -o - + +#include + +void test_builtin_pulp_diag(int32_t *data) { + // clang-format off + (void) __builtin_pulp_mac(1, 2, 3); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulpmacsi'}} + (void) __builtin_pulp_msu(1, 2, 10); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulpmacsi'}} + // clang-format on +} diff --git a/clang/test/CodeGen/RISCV/riscv-xpulpmacsi-intrinsics.c b/clang/test/CodeGen/RISCV/riscv-xpulpmacsi-intrinsics.c new file mode 100644 index 0000000000000..f88404017c14d --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv-xpulpmacsi-intrinsics.c @@ -0,0 +1,39 @@ +// REQUIRES: riscv-registered-target +// Performing the same checks for each possible way to invoke clang +// for PULP extensions: +// 1. cc1 with unversioned group extension (+xpulpv instead of +xpulpv2) +// RUN: %clang_cc1 -triple riscv32 -target-feature +xpulpv -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// 2. clang with versioned group extension +// RUN: %clang --target=riscv32 -march=rv32imafcxpulpv2 -c -S -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// 3. clang with specific extension +// RUN: %clang --target=riscv32 -march=rv32imafcxpulpmacsi -c -S -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// 4. clang with a platform triple that is expected to provide PULP extensions +// RUN: %clang --target=riscv32-hero-unknown-elf -c -S -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +#include + +typedef int16_t v2s __attribute__((vector_size(4))); +typedef uint16_t v2u __attribute__((vector_size(4))); +typedef int8_t v4s __attribute__((vector_size(4))); +typedef uint8_t v4u __attribute__((vector_size(4))); + +// CHECK-LABEL: @test_builtin_pulp_mac( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.riscv.pulp.mac(i32 1, i32 2, i32 3) +// CHECK-NEXT: ret i32 [[RES]] +int32_t test_builtin_pulp_mac(void) { + return __builtin_pulp_mac(1, 2, 3); +} + +// CHECK-LABEL: @test_builtin_pulp_msu( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.riscv.pulp.msu(i32 1, i32 2, i32 10) +// CHECK-NEXT: ret i32 [[RES]] +// +int32_t test_builtin_pulp_msu(void) { + return __builtin_pulp_msu(1, 2, 10); +} diff --git a/clang/test/CodeGen/RISCV/riscv-xpulppostmod-intrinsics-diag.c b/clang/test/CodeGen/RISCV/riscv-xpulppostmod-intrinsics-diag.c new file mode 100644 index 0000000000000..4fcbd18da7fd7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv-xpulppostmod-intrinsics-diag.c @@ -0,0 +1,17 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 %s -triple=riscv32 -verify -S -o - + +#include + +void test_builtin_pulp_diag(int32_t *data) { + // clang-format off + (void) __builtin_pulp_OffsetedRead(data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}} + (void) __builtin_pulp_OffsetedReadHalf((int16_t *) data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}} + (void) __builtin_pulp_OffsetedReadByte((char *) data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}} + __builtin_pulp_OffsetedWrite(1, data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}} + __builtin_pulp_OffsetedWriteHalf(1, (int16_t *) data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}} + __builtin_pulp_OffsetedWriteByte(1, (char *) data, 4); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}} + (void) __builtin_pulp_read_base_off(data, 0xF); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}} + __builtin_pulp_write_base_off(0x1, data, 0xF); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'Xpulpv', 'Xpulppostmod'}} + // clang-format on +} diff --git a/clang/test/CodeGen/RISCV/riscv-xpulppostmod-intrinsics.c b/clang/test/CodeGen/RISCV/riscv-xpulppostmod-intrinsics.c new file mode 100644 index 0000000000000..f0265858f6ec9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/riscv-xpulppostmod-intrinsics.c @@ -0,0 +1,81 @@ +// REQUIRES: riscv-registered-target +// Performing the same checks for each possible way to invoke clang +// for PULP extensions: +// 1. cc1 with unversioned group extension (+xpulpv instead of +xpulpv2) +// RUN: %clang_cc1 -triple riscv32 -target-feature +xpulpv -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// 2. clang with versioned group extension +// RUN: %clang --target=riscv32 -march=rv32imafcxpulpv2 -c -S -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// 3. clang with specific extension +// RUN: %clang --target=riscv32 -march=rv32imafcxpulppostmod -c -S -emit-llvm %s -o - \ +// RUN: | FileCheck %s +// 4. clang with a platform triple that is expected to provide PULP extensions +// RUN: %clang --target=riscv32-hero-unknown-elf -c -S -emit-llvm %s -o - \ +// RUN: | FileCheck %s + +#include + +// CHECK-LABEL: @test_builtin_pulp_OffsetedRead( +// CHECK: [[PTR:%.*]] = load i32*, i32** %data.addr, align 4 +// CHECK: [[RES:%.*]] = call i32 @llvm.riscv.pulp.OffsetedRead(i32* [[PTR]], i32 4) +// +int32_t test_builtin_pulp_OffsetedRead(int32_t *data) { + return __builtin_pulp_OffsetedRead(data, 4); +} + +// CHECK-LABEL: @test_builtin_pulp_OffsetedWrite( +// CHECK: [[PTR:%.*]] = load i32*, i32** %data.addr, align 4 +// CHECK: call void @llvm.riscv.pulp.OffsetedWrite(i32 1, i32* [[PTR]], i32 4) +// +void test_builtin_pulp_OffsetedWrite(int32_t *data) { + __builtin_pulp_OffsetedWrite(1, data, 4); +} + +// CHECK-LABEL: @test_builtin_pulp_OffsetedReadHalf( +// CHECK: [[PTR:%.*]] = load i16*, i16** %data.addr, align 4 +// CHECK: [[RES:%.*]] = call i32 @llvm.riscv.pulp.OffsetedReadHalf(i16* [[PTR]], i32 4) +// +int16_t test_builtin_pulp_OffsetedReadHalf(int16_t *data) { + return __builtin_pulp_OffsetedReadHalf(data, 4); +} + +// CHECK-LABEL: @test_builtin_pulp_OffsetedWriteHalf( +// CHECK: [[PTR:%.*]] = load i16*, i16** %data.addr, align 4 +// CHECK: call void @llvm.riscv.pulp.OffsetedWriteHalf(i32 1, i16* [[PTR]], i32 4) +// +void test_builtin_pulp_OffsetedWriteHalf(int16_t *data) { + __builtin_pulp_OffsetedWriteHalf(1, data, 4); +} + +// CHECK-LABEL: @test_builtin_pulp_OffsetedReadByte( +// CHECK: [[PTR:%.*]] = load i8*, i8** %data.addr, align 4 +// CHECK: [[RES:%.*]] = call i32 @llvm.riscv.pulp.OffsetedReadByte(i8* [[PTR]], i32 4) +// +char test_builtin_pulp_OffsetedReadByte(char *data) { + return __builtin_pulp_OffsetedReadByte(data, 4); +} + +// CHECK-LABEL: @test_builtin_pulp_OffsetedWriteByte( +// CHECK: [[PTR:%.*]] = load i8*, i8** %data.addr, align 4 +// CHECK: call void @llvm.riscv.pulp.OffsetedWriteByte(i32 1, i8* [[PTR]], i32 4) +// +void test_builtin_pulp_OffsetedWriteByte(char *data) { + __builtin_pulp_OffsetedWriteByte(1, data, 4); +} + +// CHECK-LABEL: @test_builtin_pulp_read_base_off( +// CHECK: [[PTR:%.*]] = load i32*, i32** %data.addr, align 4 +// CHECK: call i32 @llvm.riscv.pulp.read.base.off(i32* [[PTR]], i32 15) +// +int32_t test_builtin_pulp_read_base_off(int32_t* data) { + return __builtin_pulp_read_base_off(data, 0xF); +} + +// CHECK-LABEL: @test_builtin_pulp_write_base_off( +// CHECK: [[PTR:%.*]] = load i32*, i32** %data.addr, align 4 +// CHECK: call void @llvm.riscv.pulp.write.base.off(i32 1, i32* [[PTR]], i32 15) +// +void test_builtin_pulp_write_base_off(int32_t* data) { + __builtin_pulp_write_base_off(0x1, data, 0xF); +} diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def b/llvm/include/llvm/Support/RISCVTargetParser.def index cc718eeb287b9..fcdaf3ade39e6 100644 --- a/llvm/include/llvm/Support/RISCVTargetParser.def +++ b/llvm/include/llvm/Support/RISCVTargetParser.def @@ -33,5 +33,6 @@ PROC(SIFIVE_S76, {"sifive-s76"}, FK_64BIT, {"rv64gc"}) PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"}) PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"}) PROC(SNITCH, {"snitch"}, FK_NONE, {"rv32imafd_zfh_xfrep_xssr_xdma_xcopift_xfalthalf_xfquarter_xfaltquarter_xfvecsingle_xfvechalf_xfvecalthalf_xfvecquarter_xfvecaltquarter_xfauxhalf_xfauxalthalf_xfauxquarter_xfauxaltquarter_xfauxvecsingle_xfauxvechalf_xfauxvecalthalf_xfauxvecquarter_xfauxvecaltquarter_xfexpauxvechalf_xfexpauxvecalthalf_xfexpauxvecquarter_xfexpauxvecaltquarter"}) +PROC(SNITCH_MEMPOOL, {"snitch-mempool"}, FK_NONE, {"rv32imafd_zfh_xfalthalf_xfquarter_xfaltquarter_xfvecsingle_xfvechalf_xfvecalthalf_xfvecquarter_xfvecaltquarter_xfauxhalf_xfauxalthalf_xfauxquarter_xfauxaltquarter_xfauxvecsingle_xfauxvechalf_xfauxvecalthalf_xfauxvecquarter_xfauxvecaltquarter_xfexpauxvechalf_xfexpauxvecalthalf_xfexpauxvecquarter_xfexpauxvecaltquarter_xpulpabs_xpulpbitop_xpulpbr_xpulpclip_xpulpmacsi_xpulpminmax_xpulppostmod_xpulpslet_xpulpvect_xpulpvectshufflepack"}) #undef PROC diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index f39c0b1c0b276..55a13b1bdf61b 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -125,6 +125,27 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"xfexpauxvecaltquarter", RISCVExtensionVersion{0, 1}}, // PULP extensions {"xpulpv", RISCVExtensionVersion{2, 0}}, + {"xpulphwloop", RISCVExtensionVersion{0, 1}}, + {"xpulppostmod", RISCVExtensionVersion{0, 1}}, + {"xpulpindregreg", RISCVExtensionVersion{0, 1}}, + {"xpulpelw", RISCVExtensionVersion{0, 1}}, + {"xpulpabs", RISCVExtensionVersion{0, 1}}, + {"xpulpslet", RISCVExtensionVersion{0, 1}}, + {"xpulpmacsi", RISCVExtensionVersion{0, 1}}, + {"xpulpmulrnhi", RISCVExtensionVersion{0, 1}}, + {"xpulpmacrnhi", RISCVExtensionVersion{0, 1}}, + {"xpulppartmac", RISCVExtensionVersion{0, 1}}, + {"xpulpminmax", RISCVExtensionVersion{0, 1}}, + {"xpulpbitop", RISCVExtensionVersion{0, 1}}, + {"xpulpvect", RISCVExtensionVersion{0, 1}}, + {"xpulpvectshufflepack", RISCVExtensionVersion{0, 1}}, + {"xpulpvectcomplex", RISCVExtensionVersion{0, 1}}, + {"xpulpclip", RISCVExtensionVersion{0, 1}}, + {"xpulpaddsubrn", RISCVExtensionVersion{0, 1}}, + {"xpulpbr", RISCVExtensionVersion{0, 1}}, + {"xpulpbitrev", RISCVExtensionVersion{0, 1}}, + {"xpulpvectgap8", RISCVExtensionVersion{0, 1}}, + {"xpulpvectgap9", RISCVExtensionVersion{0, 1}}, }; static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 5c4bd0baa6c55..52add14d5c60b 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1934,7 +1934,7 @@ RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) { return MatchOperand_ParseFail; } - if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtV2]) { + if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtPostmod]) { if (getLexer().is(AsmToken::Exclaim)){ getParser().Lex(); // Eat '!' Operands.push_back(RISCVOperand::createToken("!", getLoc(), isRV64())); @@ -2035,7 +2035,7 @@ bool RISCVAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { // Attempt to parse token as a register. if (parseRegister(Operands, true) == MatchOperand_Success) { - if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtV2]) { + if (getSTI().getFeatureBits()[RISCV::FeaturePULPExtPostmod]) { if (getLexer().is(AsmToken::LParen)) return parseMemOpBaseReg(Operands) != MatchOperand_Success; } diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 64bd6669d1f70..d53102d2a09f4 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -457,9 +457,19 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, } Insn = support::endian::read32le(Bytes.data()); - if (STI.getFeatureBits()[RISCV::FeaturePULPExtV2]) { - LLVM_DEBUG(dbgs() << "Trying RV32Xpulp table (PULP extensions):\n"); - Result = decodeInstruction(DecoderTableRV32Xpulp32, MI, Insn, Address, this, + // if (STI.getFeatureBits()[RISCV::FeaturePULPExtV2]) { + // LLVM_DEBUG(dbgs() << "Trying RV32Xpulp table (PULP extensions):\n"); + // Result = decodeInstruction(DecoderTableRV32Xpulp32, MI, Insn, Address, this, + // STI); + // if (Result != MCDisassembler::Fail) { + // Size = 4; + // return Result; + // } + // } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtHwloop]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulphwloop table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulphwloop32, MI, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -467,6 +477,206 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, } } + if (STI.getFeatureBits()[RISCV::FeaturePULPExtPostmod]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulppostmod table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulppostmod32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + // if (STI.getFeatureBits()[RISCV::FeaturePULPExtIndregreg]) { + // LLVM_DEBUG(dbgs() << "Trying RV32Xpulpindregreg table (PULP extensions):\n"); + // Result = decodeInstruction(DecoderTableRV32Xpulpindregreg32, MI, Insn, Address, this, + // STI); + // if (Result != MCDisassembler::Fail) { + // Size = 4; + // return Result; + // } + // } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtElw]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpelw table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpelw32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtAbs]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpabs table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpabs32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtSlet]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpslet table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpslet32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtMacsi]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpmacsi table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpmacsi32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtMulrnhi]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpmulrnhi table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpmulrnhi32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtMacrnhi]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpmacrnhi table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpmacrnhi32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtPartmac]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulppartmac table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulppartmac32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtMinmax]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpminmax table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpminmax32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtBitop]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpbitop table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpbitop32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtVect]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpvect table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpvect32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtVectshufflepack]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpvectshufflepack table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpvectshufflepack32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + // if (STI.getFeatureBits()[RISCV::FeaturePULPExtVectcomplex]) { + // LLVM_DEBUG(dbgs() << "Trying RV32Xpulpvectcomplex table (PULP extensions):\n"); + // Result = decodeInstruction(DecoderTableRV32Xpulpvectcomplex32, MI, Insn, Address, this, + // STI); + // if (Result != MCDisassembler::Fail) { + // Size = 4; + // return Result; + // } + // } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtClip]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpclip table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpclip32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtAddsubrn]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpaddsubrn table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpaddsubrn32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + if (STI.getFeatureBits()[RISCV::FeaturePULPExtBr]) { + LLVM_DEBUG(dbgs() << "Trying RV32Xpulpbr table (PULP extensions):\n"); + Result = decodeInstruction(DecoderTableRV32Xpulpbr32, MI, Insn, Address, this, + STI); + if (Result != MCDisassembler::Fail) { + Size = 4; + return Result; + } + } + + // if (STI.getFeatureBits()[RISCV::FeaturePULPExtBitrev]) { + // LLVM_DEBUG(dbgs() << "Trying RV32Xpulpbitrev table (PULP extensions):\n"); + // Result = decodeInstruction(DecoderTableRV32Xpulpbitrev32, MI, Insn, Address, this, + // STI); + // if (Result != MCDisassembler::Fail) { + // Size = 4; + // return Result; + // } + // } + + // if (STI.getFeatureBits()[RISCV::FeaturePULPExtVectgap8]) { + // LLVM_DEBUG(dbgs() << "Trying RV32Xpulpvectgap8 table (PULP extensions):\n"); + // Result = decodeInstruction(DecoderTableRV32Xpulpvectgap832, MI, Insn, Address, this, + // STI); + // if (Result != MCDisassembler::Fail) { + // Size = 4; + // return Result; + // } + // } + + // if (STI.getFeatureBits()[RISCV::FeaturePULPExtVectgap9]) { + // LLVM_DEBUG(dbgs() << "Trying RV32Xpulpvectgap9 table (PULP extensions):\n"); + // Result = decodeInstruction(DecoderTableRV32Xpulpvectgap932, MI, Insn, Address, this, + // STI); + // if (Result != MCDisassembler::Fail) { + // Size = 4; + // return Result; + // } + // } + if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] && !STI.getFeatureBits()[RISCV::Feature64Bit]) { LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and" diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 05e267ee1cc01..cf58fe5e22df9 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -401,11 +401,146 @@ def FeatureStdExtZvfh [FeatureStdExtZve32f]>; // TODO We should remove the "V2" part, since this is handled specially now. +// XPULP Extensions +def FeaturePULPExtHwloop + : SubtargetFeature<"xpulphwloop", "HasPULPExtHwloop", + "true", "'Xpulphwloop' (PULP extensions for hardware loops)">; +def HasPULPExtHwloop : Predicate<"Subtarget->hasPULPExtHwloop()">, + AssemblerPredicate<(all_of FeaturePULPExtHwloop)>; + +def FeaturePULPExtPostmod + : SubtargetFeature<"xpulppostmod", "HasPULPExtPostmod", + "true", "'Xpulppostmod' (PULP extensions for postmod load store)">; +def HasPULPExtPostmod : Predicate<"Subtarget->hasPULPExtPostmod()">, + AssemblerPredicate<(all_of FeaturePULPExtPostmod)>; + +def FeaturePULPExtIndregreg + : SubtargetFeature<"xpulpindregreg", "HasPULPExtIndregreg", + "true", "'Xpulpindregreg' (PULP extensions for register indirect stores and loads)">; +def HasPULPExtIndregreg : Predicate<"Subtarget->hasPULPExtIndregreg()">, + AssemblerPredicate<(all_of FeaturePULPExtIndregreg)>; + +def FeaturePULPExtElw + : SubtargetFeature<"xpulpelw", "HasPULPExtElw", + "true", "'Xpulpelw' (PULP extensions for event unit load)">; +def HasPULPExtElw : Predicate<"Subtarget->hasPULPExtElw()">, + AssemblerPredicate<(all_of FeaturePULPExtElw)>; + +def FeaturePULPExtAbs + : SubtargetFeature<"xpulpabs", "HasPULPExtAbs", + "true", "'Xpulpabs' (PULP extensions for abs)">; +def HasPULPExtAbs : Predicate<"Subtarget->hasPULPExtAbs()">, + AssemblerPredicate<(all_of FeaturePULPExtAbs)>; + +def FeaturePULPExtSlet + : SubtargetFeature<"xpulpslet", "HasPULPExtSlet", + "true", "'Xpulpslet' (PULP extensions for comparison)">; +def HasPULPExtSlet : Predicate<"Subtarget->hasPULPExtSlet()">, + AssemblerPredicate<(all_of FeaturePULPExtSlet)>; + +def FeaturePULPExtMacsi + : SubtargetFeature<"xpulpmacsi", "HasPULPExtMacsi", + "true", "'Xpulpmacsi' (PULP extensions for mac)">; +def HasPULPExtMacsi : Predicate<"Subtarget->hasPULPExtMacsi()">, + AssemblerPredicate<(all_of FeaturePULPExtMacsi)>; + +def FeaturePULPExtMulrnhi + : SubtargetFeature<"xpulpmulrnhi", "HasPULPExtMulrnhi", + "true", "'Xpulpmulrnhi' (PULP extensions for partial mul (16x16 into 32))">; +def HasPULPExtMulrnhi : Predicate<"Subtarget->hasPULPExtMulrnhi()">, + AssemblerPredicate<(all_of FeaturePULPExtMulrnhi)>; + +def FeaturePULPExtMacrnhi + : SubtargetFeature<"xpulpmacrnhi", "HasPULPExtMacrnhi", + "true", "'Xpulpmacrnhi' (PULP extensions for partial mac (16x16 into 32) with rounding and norm)">; +def HasPULPExtMacrnhi : Predicate<"Subtarget->hasPULPExtMacrnhi()">, + AssemblerPredicate<(all_of FeaturePULPExtMacrnhi)>; + +def FeaturePULPExtPartmac + : SubtargetFeature<"xpulppartmac", "HasPULPExtPartmac", + "true", "'Xpulppartmac' (PULP extensions for partial mac 16x16 into 32)">; +def HasPULPExtPartmac : Predicate<"Subtarget->hasPULPExtPartmac()">, + AssemblerPredicate<(all_of FeaturePULPExtPartmac)>; + +def FeaturePULPExtMinmax + : SubtargetFeature<"xpulpminmax", "HasPULPExtMinmax", + "true", "'Xpulpminmax' (PULP extensions for min/max functions)">; +def HasPULPExtMinmax : Predicate<"Subtarget->hasPULPExtMinmax()">, + AssemblerPredicate<(all_of FeaturePULPExtMinmax)>; + +def FeaturePULPExtBitop + : SubtargetFeature<"xpulpbitop", "HasPULPExtBitop", + "true", "'Xpulpbitop' (PULP extensions for bit manipulation)">; +def HasPULPExtBitop : Predicate<"Subtarget->hasPULPExtBitop()">, + AssemblerPredicate<(all_of FeaturePULPExtBitop)>; + +def FeaturePULPExtVect + : SubtargetFeature<"xpulpvect", "HasPULPExtVect", + "true", "'Xpulpvect' (PULP extensions for integer SIMD instructions)">; +def HasPULPExtVect : Predicate<"Subtarget->hasPULPExtVect()">, + AssemblerPredicate<(all_of FeaturePULPExtVect)>; + +def FeaturePULPExtVectshufflepack + : SubtargetFeature<"xpulpvectshufflepack", "HasPULPExtVectshufflepack", + "true", "'Xpulpvectshufflepack' (PULP extensions for SIMD shuffle and pack)">; +def HasPULPExtVectshufflepack : Predicate<"Subtarget->hasPULPExtVectshufflepack()">, + AssemblerPredicate<(all_of FeaturePULPExtVectshufflepack)>; + +def FeaturePULPExtVectcomplex + : SubtargetFeature<"xpulpvectcomplex", "HasPULPExtVectcomplex", + "true", "'Xpulpvectcomplex' (PULP extensions for SIMD complex instructions)">; +def HasPULPExtVectcomplex : Predicate<"Subtarget->hasPULPExtVectcomplex()">, + AssemblerPredicate<(all_of FeaturePULPExtVectcomplex)>; + +def FeaturePULPExtClip + : SubtargetFeature<"xpulpclip", "HasPULPExtClip", + "true", "'Xpulpclip' (PULP extensions for clip)">; +def HasPULPExtClip : Predicate<"Subtarget->hasPULPExtClip()">, + AssemblerPredicate<(all_of FeaturePULPExtClip)>; + +def FeaturePULPExtAddsubrn + : SubtargetFeature<"xpulpaddsubrn", "HasPULPExtAddsubrn", + "true", "'Xpulpaddsubrn' (PULP extensions for add/sub with norm/round)">; +def HasPULPExtAddsubrn : Predicate<"Subtarget->hasPULPExtAddsubrn()">, + AssemblerPredicate<(all_of FeaturePULPExtAddsubrn)>; + +def FeaturePULPExtBr + : SubtargetFeature<"xpulpbr", "HasPULPExtBr", + "true", "'Xpulpbr' (PULP extensions for immediate branching)">; +def HasPULPExtBr : Predicate<"Subtarget->hasPULPExtBr()">, + AssemblerPredicate<(all_of FeaturePULPExtBr)>; + +def FeaturePULPExtBitrev + : SubtargetFeature<"xpulpbitrev", "HasPULPExtBitrev", + "true", "'Xpulpbitrev' (PULP extensions for bitreversal)">; +def HasPULPExtBitrev : Predicate<"Subtarget->hasPULPExtBitrev()">, + AssemblerPredicate<(all_of FeaturePULPExtBitrev)>; + +def FeaturePULPExtVectgap8 + : SubtargetFeature<"xpulpvectgap8", "HasPULPExtVectgap8", + "true", "'Xpulpvectgap8' (PULP extensions for SIMD instructions in gap8)">; +def HasPULPExtVectgap8 : Predicate<"Subtarget->hasPULPExtVectgap8()">, + AssemblerPredicate<(all_of FeaturePULPExtVectgap8)>; + +def FeaturePULPExtVectgap9 + : SubtargetFeature<"xpulpvectgap9", "HasPULPExtVectgap9", + "true", "'Xpulpvectgap9' (PULP extensions for SIMD instructions in gap9)">; +def HasPULPExtVectgap9 : Predicate<"Subtarget->hasPULPExtVectgap9()">, + AssemblerPredicate<(all_of FeaturePULPExtVectgap9)>; + def FeaturePULPExtV2 : SubtargetFeature<"xpulpv", "HasPULPExtV2", - "true", "'pulpv2' (PULP extensions version 2)">; + "true", "'pulpv2' (PULP extensions version 2)", + [FeaturePULPExtHwloop, FeaturePULPExtPostmod, FeaturePULPExtIndregreg, + FeaturePULPExtElw, FeaturePULPExtAbs, FeaturePULPExtSlet, + FeaturePULPExtMacsi, FeaturePULPExtMulrnhi, FeaturePULPExtMacrnhi, + FeaturePULPExtPartmac, FeaturePULPExtMinmax, FeaturePULPExtBitop, + FeaturePULPExtVect, FeaturePULPExtVectshufflepack, FeaturePULPExtVectcomplex, + FeaturePULPExtClip, FeaturePULPExtAddsubrn, FeaturePULPExtBr, + FeaturePULPExtBitrev, FeaturePULPExtVectgap8, FeaturePULPExtVectgap9]>; def HasPULPExtV2 : Predicate<"Subtarget->hasPULPExtV2()">, AssemblerPredicate<(all_of FeaturePULPExtV2)>; +// END XPULP extensions def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; @@ -621,6 +756,43 @@ def : ProcessorModel<"snitch", SnitchModel, [FeatureStdExtM, FeatureExtXfexpauxvecquarter, FeatureExtXfexpauxvecaltquarter ]>; +def : ProcessorModel<"snitch-mempool", SnitchModel, [FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtZfh, + FeatureExtXfalthalf, + FeatureExtXfquarter, + FeatureExtXfaltquarter, + FeatureExtXfvecsingle, + FeatureExtXfvechalf, + FeatureExtXfvecalthalf, + FeatureExtXfvecquarter, + FeatureExtXfvecaltquarter, + FeatureExtXfauxhalf, + FeatureExtXfauxalthalf, + FeatureExtXfauxquarter, + FeatureExtXfauxaltquarter, + FeatureExtXfauxvecsingle, + FeatureExtXfauxvechalf, + FeatureExtXfauxvecalthalf, + FeatureExtXfauxvecquarter, + FeatureExtXfauxvecaltquarter, + FeatureExtXfexpauxvechalf, + FeatureExtXfexpauxvecalthalf, + FeatureExtXfexpauxvecquarter, + FeatureExtXfexpauxvecaltquarter, + FeaturePULPExtAbs, + FeaturePULPExtBitop, + FeaturePULPExtBr, + FeaturePULPExtClip, + FeaturePULPExtMacsi, + FeaturePULPExtMinmax, + FeaturePULPExtPostmod, + FeaturePULPExtSlet, + FeaturePULPExtVect, + FeaturePULPExtVectshufflepack ]>; + //===----------------------------------------------------------------------===// // Define the RISC-V target. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 7bd3dcb3de27a..3e3ccd66e5285 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -92,7 +92,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, addRegisterClass(MVT::f32, &RISCV::FPR32RegClass); if (Subtarget.hasStdExtD()) addRegisterClass(MVT::f64, &RISCV::FPR64RegClass); - if (Subtarget.hasPULPExtV2()) { + if (Subtarget.hasPULPExtV2() || Subtarget.hasPULPExtVect() || + Subtarget.hasPULPExtVectshufflepack() || Subtarget.hasPULPExtVectcomplex()) { addRegisterClass(MVT::v2i16, &RISCV::PulpV2RegClass); addRegisterClass(MVT::v4i8, &RISCV::PulpV4RegClass); } @@ -463,7 +464,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::UMIN, VT, Legal); setOperationAction(ISD::SMAX, VT, Legal); setOperationAction(ISD::UMAX, VT, Legal); - } setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal); @@ -517,7 +517,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, // If this is PULP with PULPv2 extensions, then we support post-incrementing // load/stores for 8-bit, 16-bit, and 32-bit values. - if (Subtarget.hasPULPExtV2()) { + if (Subtarget.hasPULPExtPostmod()) { setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXpulp.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXpulp.td index 34c2ed4699440..c5c105c248db5 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXpulp.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXpulp.td @@ -402,13 +402,13 @@ multiclass Pulp_Load funct7, bits<3> funct3, string opcodestr> { // Instructions //===----------------------------------------------------------------------===// -let Predicates = [IsRV32, HasPULPExtV2], DecoderNamespace = "RV32Xpulp" in { - +let Predicates = [IsRV32, HasPULPExtElw], DecoderNamespace = "RV32Xpulpelw" in { let hasSideEffects = 1, mayStore = 1 in def PULP_ELW : Load_ri<0b110, "p.elw">, Sched<[WriteLDW, ReadMemBase]>; +} // Predicates = [IsRV32, HasPULPExtElw], DecoderNamespace = "RV32Xpulpelw" // Hardware loops - +let Predicates = [IsRV32, HasPULPExtHwloop], DecoderNamespace = "RV32Xpulphwloop" in { def LOOP0setup : Instruction, Sched<[ReadIALU, WriteCSR]> { bits<32> Inst; @@ -733,7 +733,9 @@ def LOOP1count : Instruction, Sched<[ReadIALU, WriteCSR]> { let AsmString = "lp.count\tx1, $uimmS"; } +} // Predicates = [IsRV32, HasPULPExtHwloop], DecoderNamespace = "RV32Xpulphwloop" +let Predicates = [IsRV32, HasPULPExtBitop], DecoderNamespace = "RV32Xpulpbitop" in { // Bit manipulation operations def P_EXTRACT : Pulp_ALU_rii <0b11, 0b000, "p.extract">; def P_EXTRACTU : Pulp_ALU_rii <0b11, 0b001, "p.extractu">; @@ -753,24 +755,38 @@ def P_FL1 : Pulp_ALU_r <0b0001000, 0b001, OPC_OP, "p.fl1">; def P_CLB : Pulp_ALU_r <0b0001000, 0b010, OPC_OP, "p.clb">; def P_CNT : Pulp_ALU_r <0b0001000, 0b011, OPC_OP, "p.cnt">; +def P_EXTHS : Pulp_ALU_r <0b0001000, 0b100, OPC_OP, "p.exths">; +def P_EXTHZ : Pulp_ALU_r <0b0001000, 0b101, OPC_OP, "p.exthz">; +def P_EXTBS : Pulp_ALU_r <0b0001000, 0b110, OPC_OP, "p.extbs">; +def P_EXTBZ : Pulp_ALU_r <0b0001000, 0b111, OPC_OP, "p.extbz">; +} // Predicates = [IsRV32, HasPULPExtBitop], DecoderNamespace = "RV32Xpulpbitop" + + // General ALU operations +let Predicates = [IsRV32, HasPULPExtAbs], DecoderNamespace = "RV32Xpulpabs" in { def P_ABS : Pulp_ALU_r <0b0000010, 0b000, OPC_OP, "p.abs">; +} // Predicates = [IsRV32, HasPULPExtAbs], DecoderNamespace = "RV32Xpulpabs" + +let Predicates = [IsRV32, HasPULPExtSlet], DecoderNamespace = "RV32Xpulpslet" in { def P_SLET : Pulp_ALU_rr<0b0000010, 0b010, OPC_OP, "p.slet">; def P_SLETU : Pulp_ALU_rr<0b0000010, 0b011, OPC_OP, "p.sletu">; +} // Predicates = [IsRV32, HasPULPExtSlet], DecoderNamespace = "RV32Xpulpslet" + +let Predicates = [IsRV32, HasPULPExtMinmax], DecoderNamespace = "RV32Xpulpminmax" in { def P_MIN : Pulp_ALU_rr<0b0000010, 0b100, OPC_OP, "p.min">; def P_MINU : Pulp_ALU_rr<0b0000010, 0b101, OPC_OP, "p.minu">; def P_MAX : Pulp_ALU_rr<0b0000010, 0b110, OPC_OP, "p.max">; def P_MAXU : Pulp_ALU_rr<0b0000010, 0b111, OPC_OP, "p.maxu">; -def P_EXTHS : Pulp_ALU_r <0b0001000, 0b100, OPC_OP, "p.exths">; -def P_EXTHZ : Pulp_ALU_r <0b0001000, 0b101, OPC_OP, "p.exthz">; -def P_EXTBS : Pulp_ALU_r <0b0001000, 0b110, OPC_OP, "p.extbs">; -def P_EXTBZ : Pulp_ALU_r <0b0001000, 0b111, OPC_OP, "p.extbz">; +} // Predicates = [IsRV32, HasPULPExtMinmax], DecoderNamespace = "RV32Xpulpminmax" +let Predicates = [IsRV32, HasPULPExtClip], DecoderNamespace = "RV32Xpulpclip" in { def P_CLIP : Pulp_ALU_ri<0b0001010, 0b001, "p.clip">; def P_CLIPU : Pulp_ALU_ri<0b0001010, 0b010, "p.clipu">; def P_CLIPR : Pulp_ALU_rr<0b0001010, 0b101, OPC_OP, "p.clipr">; def P_CLIPUR : Pulp_ALU_rr<0b0001010, 0b110, OPC_OP, "p.clipur">; +} // Predicates = [IsRV32, HasPULPExtClip], DecoderNamespace = "RV32Xpulpclip" +let Predicates = [IsRV32, HasPULPExtAddsubrn], DecoderNamespace = "RV32Xpulpaddsubrn" in { def P_ADDN : Pulp_ALU_rri<0b00, 0b010, OPC_PULP_OP, "p.addn">; def P_ADDUN : Pulp_ALU_rri<0b10, 0b010, OPC_PULP_OP, "p.addun">; def P_ADDRN : Pulp_ALU_rri<0b00, 0b110, OPC_PULP_OP, "p.addrn">; @@ -787,15 +803,21 @@ def P_SUBNR : Pulp_ALU_rr_wb<0b0100000, 0b011, OPC_PULP_OP, "p.subnr">; def P_SUBUNR : Pulp_ALU_rr_wb<0b1100000, 0b011, OPC_PULP_OP, "p.subunr">; def P_SUBRNR : Pulp_ALU_rr_wb<0b0100000, 0b111, OPC_PULP_OP, "p.subrnr">; def P_SUBURNR : Pulp_ALU_rr_wb<0b1100000, 0b111, OPC_PULP_OP, "p.suburnr">; +} // Predicates = [IsRV32, HasPULPExtAddsubrn], DecoderNamespace = "RV32Xpulpaddsubrn" +let Predicates = [IsRV32, HasPULPExtBr], DecoderNamespace = "RV32Xpulpbr" in { // Instructions: immediate branches def P_BEQIMM : Pulp_Immediate_Branch<0b010, "p.beqimm">; def P_BNEIMM : Pulp_Immediate_Branch<0b011, "p.bneimm">; +} // Predicates = [IsRV32, HasPULPExtBr], DecoderNamespace = "RV32Xpulpbr" +let Predicates = [IsRV32, HasPULPExtMacsi], DecoderNamespace = "RV32Xpulpmacsi" in { // Instructions: MAC operations def P_MAC : Pulp_ALU_rr_wb<0b0100001, 0b000, OPC_OP, "p.mac">; def P_MSU : Pulp_ALU_rr_wb<0b0100001, 0b001, OPC_OP, "p.msu">; +} // Predicates = [IsRV32, HasPULPExtMacsi], DecoderNamespace = "RV32Xpulpmacsi" +let Predicates = [IsRV32, HasPULPExtMulrnhi], DecoderNamespace = "RV32Xpulpmulrnhi" in { def P_MULS : Pulp_ALU_rr <0b1000000, 0b000, OPC_PULP_OP, "p.muls">; def P_MULHHS : Pulp_ALU_rr <0b1100000, 0b000, OPC_PULP_OP, "p.mulhhs">; def P_MULSN : Pulp_ALU_rri <0b10, 0b000, OPC_PULP_OP, "p.mulsn">; @@ -808,19 +830,27 @@ def P_MULUN : Pulp_ALU_rri <0b00, 0b000, OPC_PULP_OP, "p.mulun">; def P_MULHHUN : Pulp_ALU_rri <0b01, 0b000, OPC_PULP_OP, "p.mulhhun">; def P_MULURN : Pulp_ALU_rri <0b00, 0b100, OPC_PULP_OP, "p.mulurn">; def P_MULHHURN : Pulp_ALU_rri <0b01, 0b100, OPC_PULP_OP, "p.mulhhurn">; -def P_MACS : Pulp_ALU_rr_wb<0b1000000, 0b001, OPC_PULP_OP, "p.macs">; -def P_MACHHS : Pulp_ALU_rr_wb<0b1100000, 0b001, OPC_PULP_OP, "p.machhs">; +} // Predicates = [IsRV32, HasPULPExtMulrnhi], DecoderNamespace = "RV32Xpulpmulrnhi" + +let Predicates = [IsRV32, HasPULPExtMacrnhi], DecoderNamespace = "RV32Xpulpmacrnhi" in { def P_MACSN : Pulp_ALU_rri_wb <0b10, 0b001, OPC_PULP_OP, "p.macsn">; def P_MACHHSN : Pulp_ALU_rri_wb <0b11, 0b001, OPC_PULP_OP, "p.machhsn">; def P_MACSRN : Pulp_ALU_rri_wb <0b10, 0b101, OPC_PULP_OP, "p.macsrn">; def P_MACHHSRN : Pulp_ALU_rri_wb <0b11, 0b101, OPC_PULP_OP, "p.machhsrn">; -def P_MACU : Pulp_ALU_rr_wb<0b0000000, 0b001, OPC_PULP_OP, "p.macu">; -def P_MACHHU : Pulp_ALU_rr_wb<0b0100000, 0b001, OPC_PULP_OP, "p.machhu">; def P_MACUN : Pulp_ALU_rri_wb <0b00, 0b001, OPC_PULP_OP, "p.macun">; def P_MACHHUN : Pulp_ALU_rri_wb <0b01, 0b001, OPC_PULP_OP, "p.machhun">; def P_MACURN : Pulp_ALU_rri_wb <0b00, 0b101, OPC_PULP_OP, "p.macurn">; def P_MACHHURN : Pulp_ALU_rri_wb <0b01, 0b101, OPC_PULP_OP, "p.machhurn">; +} // Predicates = [IsRV32, HasPULPExtMacrnhi], DecoderNamespace = "RV32Xpulpmacrnhi" + +let Predicates = [IsRV32, HasPULPExtPartmac], DecoderNamespace = "RV32Xpulppartmac" in { +def P_MACS : Pulp_ALU_rr_wb<0b1000000, 0b001, OPC_PULP_OP, "p.macs">; +def P_MACHHS : Pulp_ALU_rr_wb<0b1100000, 0b001, OPC_PULP_OP, "p.machhs">; +def P_MACU : Pulp_ALU_rr_wb<0b0000000, 0b001, OPC_PULP_OP, "p.macu">; +def P_MACHHU : Pulp_ALU_rr_wb<0b0100000, 0b001, OPC_PULP_OP, "p.machhu">; +} // Predicates = [IsRV32, HasPULPExtPartmac], DecoderNamespace = "RV32Xpulppartmac" +let Predicates = [IsRV32, HasPULPExtVect], DecoderNamespace = "RV32Xpulpvect" in { // Instructions: packed vector ALU defm PV_ADD : SC_SCI_H_B<0b00000, 0, simm6, "add">; defm PV_SUB : SC_SCI_H_B<0b00001, 0, simm6, "sub">; @@ -847,6 +877,14 @@ let hasSideEffects = 0, mayStore = 0, mayLoad = 0, rs2 = 0 in { "pv.abs.b", "$rd, $rs1">, Sched<[WriteIALU, ReadIALU]>; } +// Pseudos used to lower vector splat operations on packed SIMD data types +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { + def PseudoPV_ADD_SC_H_VL : Pseudo<(outs PulpV2:$dst), (ins GPR:$src1, GPR:$src2, AVL:$vl),[]>; + def PseudoPV_ADD_SC_B_VL : Pseudo<(outs PulpV4:$dst), (ins GPR:$src1, GPR:$src2, AVL:$vl),[]>; + def PseudoPV_ADD_SCI_H_VL : Pseudo<(outs PulpV2:$dst), (ins GPR:$src1, simm6:$imm, AVL:$vl),[]>; + def PseudoPV_ADD_SCI_B_VL : Pseudo<(outs PulpV4:$dst), (ins GPR:$src1, simm6:$imm, AVL:$vl),[]>; +} + def PV_EXTRACT_H : Pulp_ALU_vsci<0b01111, 0, 0b110, "pv.extract.h", PulpV2, uimm6, GPR>; def PV_EXTRACT_B : Pulp_ALU_vsci<0b01111, 0, 0b111, "pv.extract.b", PulpV4, uimm6, GPR>; def PV_EXTRACTU_H : Pulp_ALU_vsci<0b10010, 0, 0b110, "pv.extractu.h", PulpV2, uimm6, GPR>; @@ -861,6 +899,27 @@ defm PV_SDOTUP : SDOTP<0b10100, 0, uimm6, "sdotup">; defm PV_SDOTUSP : SDOTP<0b10101, 0, simm6, "sdotusp">; defm PV_SDOTSP : SDOTP<0b10111, 0, simm6, "sdotsp">; +// Vectorial comparison operations +defm PV_CMPEQ : SC_SCI_H_B<0b00000, 1, simm6, "cmpeq">; +defm PV_CMPNE : SC_SCI_H_B<0b00001, 1, simm6, "cmpne">; +defm PV_CMPGT : SC_SCI_H_B<0b00010, 1, simm6, "cmpgt">; +defm PV_CMPGE : SC_SCI_H_B<0b00011, 1, simm6, "cmpge">; +defm PV_CMPLT : SC_SCI_H_B<0b00100, 1, simm6, "cmplt">; +defm PV_CMPLE : SC_SCI_H_B<0b00101, 1, simm6, "cmple">; +defm PV_CMPGTU : SC_SCI_H_B<0b00110, 1, uimm6, "cmpgtu">; +defm PV_CMPGEU : SC_SCI_H_B<0b00111, 1, uimm6, "cmpgeu">; +defm PV_CMPLTU : SC_SCI_H_B<0b01000, 1, uimm6, "cmpltu">; +defm PV_CMPLEU : SC_SCI_H_B<0b01001, 1, uimm6, "cmpleu">; + +let isCodeGenOnly = 1 in { // Helper for Patterns + def P_INSERTR_v2 : Pulp_ALU_rr_wb<0b1000000, 0b010, OPC_OP, "p.insertr", GPR, GPR, PulpV2>; + def P_INSERTR_v4 : Pulp_ALU_rr_wb<0b1000000, 0b010, OPC_OP, "p.insertr", GPR, GPR, PulpV4>; + def PV_SHUFFLE_H_GPR : Pulp_ALU_rr<0b1100000, 0b000, OPC_OP_V, "pv.shuffle.h", PulpV2, GPR, GPR>; + def PV_SHUFFLE_B_GPR : Pulp_ALU_rr<0b1100000, 0b001, OPC_OP_V, "pv.shuffle.b", PulpV4, GPR, GPR>; +} +} // Predicates = [IsRV32, HasPULPExtVect], DecoderNamespace = "RV32Xpulpvect" + +let Predicates = [IsRV32, HasPULPExtVectshufflepack], DecoderNamespace = "RV32Xpulpvectshufflepack" in { def PV_SHUFFLE_H : Pulp_ALU_rr<0b1100000, 0b000, OPC_OP_V, "pv.shuffle.h", PulpV2>; def PV_SHUFFLE_SCI_H : Pulp_ALU_vsci<0b11000, 0, 0b110, "pv.shuffle.sci.h", PulpV2, uimm6>; def PV_SHUFFLE_B : Pulp_ALU_rr<0b1100000, 0b001, OPC_OP_V, "pv.shuffle.b", PulpV4>; @@ -877,19 +936,10 @@ def PV_PACKLO_B : Pulp_ALU_rr_wb<0b1110000, 0b001, OPC_OP_V, "pv.packlo.b", GPR, let isCodeGenOnly = 1 in def PV_PACKHI_B_nowb : Pulp_ALU_rr<0b1101100, 0b001, OPC_OP_V, "pv.packhi.b", GPR, GPR, PulpV4>; +} // Predicates = [IsRV32, HasPULPExtVectshufflepack], DecoderNamespace = "RV32Xpulpvectshufflepack" -// Vectorial comparison operations -defm PV_CMPEQ : SC_SCI_H_B<0b00000, 1, simm6, "cmpeq">; -defm PV_CMPNE : SC_SCI_H_B<0b00001, 1, simm6, "cmpne">; -defm PV_CMPGT : SC_SCI_H_B<0b00010, 1, simm6, "cmpgt">; -defm PV_CMPGE : SC_SCI_H_B<0b00011, 1, simm6, "cmpge">; -defm PV_CMPLT : SC_SCI_H_B<0b00100, 1, simm6, "cmplt">; -defm PV_CMPLE : SC_SCI_H_B<0b00101, 1, simm6, "cmple">; -defm PV_CMPGTU : SC_SCI_H_B<0b00110, 1, uimm6, "cmpgtu">; -defm PV_CMPGEU : SC_SCI_H_B<0b00111, 1, uimm6, "cmpgeu">; -defm PV_CMPLTU : SC_SCI_H_B<0b01000, 1, uimm6, "cmpltu">; -defm PV_CMPLEU : SC_SCI_H_B<0b01001, 1, uimm6, "cmpleu">; - +let Predicates = [IsRV32, HasPULPExtPostmod], DecoderNamespace = "RV32Xpulppostmod" in { +// Instructions: Postmod load and store instructions defm P_LB : Pulp_Load<0b0000000, 0b000, "p.lb">, Sched<[WriteLDB, ReadMemBase]>; defm P_LBU : Pulp_Load<0b0100000, 0b100, "p.lbu">, Sched<[WriteLDB, ReadMemBase]>; defm P_LH : Pulp_Load<0b0001000, 0b001, "p.lh">, Sched<[WriteLDH, ReadMemBase]>; @@ -899,23 +949,7 @@ defm P_LW : Pulp_Load<0b0010000, 0b010, "p.lw">, Sched<[WriteLDW, ReadMemBase] defm P_SB : Pulp_Store<0b00, "p.sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>; defm P_SH : Pulp_Store<0b01, "p.sh">, Sched<[WriteSTH, ReadStoreData, ReadMemBase]>; defm P_SW : Pulp_Store<0b10, "p.sw">, Sched<[WriteSTW, ReadStoreData, ReadMemBase]>; - -let isCodeGenOnly = 1 in { // Helper for Patterns - def P_INSERTR_v2 : Pulp_ALU_rr_wb<0b1000000, 0b010, OPC_OP, "p.insertr", GPR, GPR, PulpV2>; - def P_INSERTR_v4 : Pulp_ALU_rr_wb<0b1000000, 0b010, OPC_OP, "p.insertr", GPR, GPR, PulpV4>; - def PV_SHUFFLE_H_GPR : Pulp_ALU_rr<0b1100000, 0b000, OPC_OP_V, "pv.shuffle.h", PulpV2, GPR, GPR>; - def PV_SHUFFLE_B_GPR : Pulp_ALU_rr<0b1100000, 0b001, OPC_OP_V, "pv.shuffle.b", PulpV4, GPR, GPR>; -} - -// Pseudos used to lower vector splat operations on packed SIMD data types -let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { - def PseudoPV_ADD_SC_H_VL : Pseudo<(outs PulpV2:$dst), (ins GPR:$src1, GPR:$src2, AVL:$vl),[]>; - def PseudoPV_ADD_SC_B_VL : Pseudo<(outs PulpV4:$dst), (ins GPR:$src1, GPR:$src2, AVL:$vl),[]>; - def PseudoPV_ADD_SCI_H_VL : Pseudo<(outs PulpV2:$dst), (ins GPR:$src1, simm6:$imm, AVL:$vl),[]>; - def PseudoPV_ADD_SCI_B_VL : Pseudo<(outs PulpV4:$dst), (ins GPR:$src1, simm6:$imm, AVL:$vl),[]>; -} - -} // Predicates = [IsRV32, HasPULPExtV2], DecoderNamespace = "RV32Xpulp" +} // Predicates = [IsRV32, HasPULPExtPostmod], DecoderNamespace = "RV32Xpulppostmod" //===----------------------------------------------------------------------===// // Codegen pattern templates @@ -1092,9 +1126,8 @@ def dotsp_sc_b : dotp_sc_b; // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// -let Predicates = [IsRV32, HasPULPExtV2] in { - -multiclass int_mul_mac_N_RN { +let Predicates = [IsRV32, HasPULPExtMulrnhi] in { +multiclass int_mul_N_RN { // mulN: mul op with normalization factor as immediate def : Pat<(!cast("int_riscv_pulp_mul" # intrin # "N") GPR:$rs1, GPR:$rs2, tuimm5:$shift), @@ -1105,6 +1138,42 @@ multiclass int_mul_mac_N_RN { GPR:$rs1, GPR:$rs2, tuimm5:$shift, timm), (!cast("P_MUL" # instr # "RN") GPR:$rs1, GPR:$rs2, tuimm5:$shift)>; +} + +defm : int_mul_N_RN<"s", "S">; +defm : int_mul_N_RN<"u", "U">; +defm : int_mul_N_RN<"hhs", "HHS">; +defm : int_mul_N_RN<"hhu", "HHU">; + +def : Pat<(muls GPR:$rs1, GPR:$rs2), + (P_MULS GPR:$rs1, GPR:$rs2)>; +def : Pat<(mulhhs GPR:$rs1, GPR:$rs2), + (P_MULHHS GPR:$rs1, GPR:$rs2)>; +def : Pat<(sra (muls GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MULSN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(sra (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MULHHSN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(shiftRound (muls GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MULSRN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(shiftRound (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MULHHSRN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; + +def : Pat<(mulu GPR:$rs1, GPR:$rs2), + (P_MULU GPR:$rs1, GPR:$rs2)>; +def : Pat<(mulhhu GPR:$rs1, GPR:$rs2), + (P_MULHHU GPR:$rs1, GPR:$rs2)>; +def : Pat<(srl (mulu GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MULUN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(srl (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MULHHUN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(ushiftRound (mulu GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MULURN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(ushiftRound (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MULHHURN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +} // Predicates = [IsRV32, HasPULPExtMulrnhi] + +let Predicates = [IsRV32, HasPULPExtMacrnhi] in { +multiclass int_mac_N_RN { // macN: mac op with normalization factor as immediate def : Pat<(!cast("int_riscv_pulp_mac" # intrin # "N") GPR:$rs1, GPR:$rs2, GPR:$rd, tuimm5:$shift), @@ -1117,8 +1186,44 @@ multiclass int_mul_mac_N_RN { GPR:$rd, GPR:$rs1, GPR:$rs2, tuimm5:$shift)>; } -// Patterns for bit manipulation operations +defm : int_mac_N_RN<"s", "S">; +defm : int_mac_N_RN<"u", "U">; +defm : int_mac_N_RN<"hhs", "HHS">; +defm : int_mac_N_RN<"hhu", "HHU">; + +def : Pat<(sra (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MACSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(sra (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MACHHSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(shiftRound (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MACSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(shiftRound (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MACHHSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; + +def : Pat<(srl (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MACUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(srl (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MACHHUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(ushiftRound (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MACURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +def : Pat<(ushiftRound (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), + (P_MACHHURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +} // Predicates = [IsRV32, HasPULPExtMacrnhi] + +let Predicates = [IsRV32, HasPULPExtPartmac] in { +def : Pat<(macs GPR:$rd, GPR:$rs1, GPR:$rs2), + (P_MACS GPR:$rd, GPR:$rs1, GPR:$rs2)>; +def : Pat<(machhs GPR:$rd, GPR:$rs1, GPR:$rs2), + (P_MACHHS GPR:$rd, GPR:$rs1, GPR:$rs2)>; +def : Pat<(macu GPR:$rd, GPR:$rs1, GPR:$rs2), + (P_MACU GPR:$rd, GPR:$rs1, GPR:$rs2)>; +def : Pat<(machhu GPR:$rd, GPR:$rs1, GPR:$rs2), + (P_MACHHU GPR:$rd, GPR:$rs1, GPR:$rs2)>; +} // Predicates = [IsRV32, HasPULPExtPartmac] + +// Patterns for bit manipulation operations +let Predicates = [IsRV32, HasPULPExtBitop] in { // extract // widthMinus1 and shift immediates def : Pat<(extract:$extract GPR:$rs1, uimm5, uimm5:$shiftRight), @@ -1247,21 +1352,31 @@ def : Pat<(ctlz_zero_undef (xor GPR:$rs1, (sra GPR:$rs1, (i32 31)))), (P_CLB GPR def : Pat<(ctpop GPR:$rs1), (P_CNT GPR:$rs1)>; def : PatGprGpr; +def : Pat<(sext_inreg GPR:$rs1, i16), (P_EXTHS GPR:$rs1)>; +def : Pat<(sext_inreg GPR:$rs1, i8 ), (P_EXTBS GPR:$rs1)>; +def : Pat<(and GPR:$rs1, 0xffff), (P_EXTHZ GPR:$rs1)>; +def : Pat<(and GPR:$rs1, 0xff ), (P_EXTBZ GPR:$rs1)>; +} // Predicates = [IsRV32, HasPULPExtBitop] + // Patterns for general ALU operations +let Predicates = [IsRV32, HasPULPExtAbs] in { def : Pat<(abs GPR:$rs1), (P_ABS GPR:$rs1)>; +} // Predicates = [IsRV32, HasPULPExtAbs] + +let Predicates = [IsRV32, HasPULPExtSlet] in { def : PatGprGpr; def : PatGprGpr; +} // Predicates = [IsRV32, HasPULPExtSlet] + +let Predicates = [IsRV32, HasPULPExtMinmax] in { def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; +} // Predicates = [IsRV32, HasPULPExtMinmax] -def : Pat<(sext_inreg GPR:$rs1, i16), (P_EXTHS GPR:$rs1)>; -def : Pat<(sext_inreg GPR:$rs1, i8 ), (P_EXTBS GPR:$rs1)>; -def : Pat<(and GPR:$rs1, 0xffff), (P_EXTHZ GPR:$rs1)>; -def : Pat<(and GPR:$rs1, 0xff ), (P_EXTBZ GPR:$rs1)>; - +let Predicates = [IsRV32, HasPULPExtClip] in { def : Pat<(clip negativePowerOf2, powerOf2Minus1:$upperBound, GPR:$rs1), (P_CLIP GPR:$rs1, (trailing1sPlus1 imm:$upperBound))>; def : Pat<(between (not GPR:$rs2), GPR:$rs2, GPR:$rs1), @@ -1270,7 +1385,9 @@ def : Pat<(betweenu powerOf2Minus1:$upperBound, GPR:$rs1), (P_CLIPU GPR:$rs1, (trailing1sPlus1 imm:$upperBound))>; def : Pat<(betweenu GPR:$rs2, GPR:$rs1), (P_CLIPUR GPR:$rs1, GPR:$rs2)>; +} // Predicates = [IsRV32, HasPULPExtClip] +let Predicates = [IsRV32, HasPULPExtAddsubrn] in { def : Pat<(sra (add GPR:$rs1, GPR:$rs2), uimm5:$Is3), (P_ADDN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; def : Pat<(srl (add GPR:$rs1, GPR:$rs2), uimm5:$Is3), @@ -1306,71 +1423,25 @@ def : Pat<(sra (add (sub GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), GPR:$rs2), (P_SUBRNR GPR:$rd, GPR:$rs1, GPR:$rs2)>; def : Pat<(srl (add (sub GPR:$rd, GPR:$rs1), (roundBit GPR:$rs2)), GPR:$rs2), (P_SUBURNR GPR:$rd, GPR:$rs1, GPR:$rs2)>; +} // Predicates = [IsRV32, HasPULPExtAddsubrn] // Patterns for immediate branching Operations +let Predicates = [IsRV32, HasPULPExtBr] in { def : Pat<(brcond (XLenVT (seteq GPR:$rs1, simm5:$imm5)), bb:$imm12), (P_BEQIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>; def : Pat<(brcond (XLenVT (setne GPR:$rs1, simm5:$imm5)), bb:$imm12), (P_BNEIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>; +} // Predicates = [IsRV32, HasPULPExtBr] +let Predicates = [IsRV32, HasPULPExtMacsi] in { def : Pat<(add GPR:$rd, (mul GPR:$rs1, GPR:$rs2)), (P_MAC GPR:$rd, GPR:$rs1, GPR:$rs2)>; def : Pat<(sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2)), (P_MSU GPR:$rd, GPR:$rs1, GPR:$rs2)>; - -def : Pat<(muls GPR:$rs1, GPR:$rs2), - (P_MULS GPR:$rs1, GPR:$rs2)>; -def : Pat<(mulhhs GPR:$rs1, GPR:$rs2), - (P_MULHHS GPR:$rs1, GPR:$rs2)>; -def : Pat<(sra (muls GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MULSN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(sra (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MULHHSN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(shiftRound (muls GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MULSRN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(shiftRound (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MULHHSRN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; - -def : Pat<(mulu GPR:$rs1, GPR:$rs2), - (P_MULU GPR:$rs1, GPR:$rs2)>; -def : Pat<(mulhhu GPR:$rs1, GPR:$rs2), - (P_MULHHU GPR:$rs1, GPR:$rs2)>; -def : Pat<(srl (mulu GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MULUN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(srl (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MULHHUN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(ushiftRound (mulu GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MULURN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(ushiftRound (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MULHHURN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; - -def : Pat<(macs GPR:$rd, GPR:$rs1, GPR:$rs2), - (P_MACS GPR:$rd, GPR:$rs1, GPR:$rs2)>; -def : Pat<(machhs GPR:$rd, GPR:$rs1, GPR:$rs2), - (P_MACHHS GPR:$rd, GPR:$rs1, GPR:$rs2)>; -def : Pat<(sra (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MACSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(sra (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MACHHSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(shiftRound (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MACSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(shiftRound (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MACHHSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; - -def : Pat<(macu GPR:$rd, GPR:$rs1, GPR:$rs2), - (P_MACU GPR:$rd, GPR:$rs1, GPR:$rs2)>; -def : Pat<(machhu GPR:$rd, GPR:$rs1, GPR:$rs2), - (P_MACHHU GPR:$rd, GPR:$rs1, GPR:$rs2)>; -def : Pat<(srl (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MACUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(srl (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MACHHUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(ushiftRound (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MACURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; -def : Pat<(ushiftRound (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3), - (P_MACHHURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; +} // Predicates = [IsRV32, HasPULPExtMacsi] // Patterns for vectorial ALU operations +let Predicates = [IsRV32, HasPULPExtVect] in { class PatV2V2 : Pat<(OpNode PulpV2:$rs1, PulpV2:$rs2), (Inst PulpV2:$rs1, PulpV2:$rs2)>; @@ -1577,24 +1648,6 @@ def : Pat<(add GPR:$rd, (dotsp_sc_b PulpV4:$rs1, (sext_inreg GPR:$rs2, i8))), def : Pat<(add GPR:$rd, (dotsp_sc_b PulpV4:$rs1, simm6:$sci)), (PV_SDOTSP_SCI_B GPR:$rd, PulpV4:$rs1, simm6:$sci)>; -def : Pat<(v2i16 (build_vector (i32 (vector_extract PulpV2:$rs1, GPR:$index0)), - (i32 (vector_extract PulpV2:$rs1, GPR:$index1)))), - (PV_SHUFFLE_H PulpV2:$rs1, (PV_PACK_H GPR:$index1, GPR:$index0))>; - -def : Pat<(v4i8 (build_vector (i32 (vector_extract PulpV4:$rs1, GPR:$index0)), - (i32 (vector_extract PulpV4:$rs1, GPR:$index1)), - (i32 (vector_extract PulpV4:$rs1, GPR:$index2)), - (i32 (vector_extract PulpV4:$rs1, GPR:$index3)))), - (PV_SHUFFLE_B PulpV4:$rs1, (PV_PACKLO_B (PV_PACKHI_B_nowb GPR:$index3, - GPR:$index2), GPR:$index1, GPR:$index0))>; - - -def : Pat<(v2i16 (build_vector GPR:$rs1, GPR:$rs2)), - (PV_PACK_H GPR:$rs2, GPR:$rs1)>; -def : Pat<(v4i8 (build_vector GPR:$rs1, GPR:$rs2, GPR:$rs3, GPR:$rs4)), - (PV_PACKLO_B (PV_PACKHI_B_nowb GPR:$rs4, GPR:$rs3), GPR:$rs2, GPR:$rs1)>; - -def : Pat<(v2i16 (splat_vector GPR:$rs1)), (PV_PACK_H GPR:$rs1, GPR:$rs1)>; def : Pat<(v4i8 (splat_vector GPR:$rs1)), (PV_ADD_SC_B X0, GPR:$rs1)>; @@ -1624,7 +1677,30 @@ def : Pat<(v2i16 (bitconvert GPR:$rs1)), (v2i16 PulpV2:$rs1)>; def : Pat<(v4i8 (bitconvert GPR:$rs1)), (v4i8 PulpV4:$rs1)>; def : Pat<(i32 (bitconvert PulpV2:$rs1)), (i32 GPR:$rs1)>; def : Pat<(i32 (bitconvert PulpV4:$rs1)), (i32 GPR:$rs1)>; +} // Predicates = [IsRV32, HasPULPExtVect] + +let Predicates = [IsRV32, HasPULPExtVectshufflepack] in { +def : Pat<(v2i16 (build_vector (i32 (vector_extract PulpV2:$rs1, GPR:$index0)), + (i32 (vector_extract PulpV2:$rs1, GPR:$index1)))), + (PV_SHUFFLE_H PulpV2:$rs1, (PV_PACK_H GPR:$index1, GPR:$index0))>; + +def : Pat<(v4i8 (build_vector (i32 (vector_extract PulpV4:$rs1, GPR:$index0)), + (i32 (vector_extract PulpV4:$rs1, GPR:$index1)), + (i32 (vector_extract PulpV4:$rs1, GPR:$index2)), + (i32 (vector_extract PulpV4:$rs1, GPR:$index3)))), + (PV_SHUFFLE_B PulpV4:$rs1, (PV_PACKLO_B (PV_PACKHI_B_nowb GPR:$index3, + GPR:$index2), GPR:$index1, GPR:$index0))>; + + +def : Pat<(v2i16 (build_vector GPR:$rs1, GPR:$rs2)), + (PV_PACK_H GPR:$rs2, GPR:$rs1)>; +def : Pat<(v4i8 (build_vector GPR:$rs1, GPR:$rs2, GPR:$rs3, GPR:$rs4)), + (PV_PACKLO_B (PV_PACKHI_B_nowb GPR:$rs4, GPR:$rs3), GPR:$rs2, GPR:$rs1)>; + +def : Pat<(v2i16 (splat_vector GPR:$rs1)), (PV_PACK_H GPR:$rs1, GPR:$rs1)>; +} // Predicates = [IsRV32, HasPULPExtVectshufflepack] +let Predicates = [IsRV32, HasPULPExtPostmod] in { // Patterns for load/store instructions // post increment loads need custom selection, because tablegen can't deal with @@ -1661,44 +1737,81 @@ def : Pat<(truncstorei16 GPR:$val, (add GPR:$base, GPR:$offset)), (P_SH_rr GPR:$val, GPR:$base, GPR:$offset)>; def : Pat<(store GPR:$val, (add GPR:$base, GPR:$offset)), (P_SW_rr GPR:$val, GPR:$base, GPR:$offset)>; +} // Predicates = [IsRV32, HasPULPExtPostmod] //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns //===----------------------------------------------------------------------===// +let Predicates = [IsRV32, HasPULPExtElw] in { def : Pat<(int_riscv_pulp_event_unit_read GPR:$rs, simm12:$simm12), (PULP_ELW GPR:$rs, simm12:$simm12)>; def : Pat<(int_riscv_pulp_event_unit_read GPR:$rs, GPR:$off), (PULP_ELW (ADD GPR:$rs, GPR:$off), 0)>; -def : Pat<(int_riscv_pulp_bitinsert GPR:$rd, GPR:$rs1, uimm5:$ls2, uimm5:$ls3), - (P_INSERT GPR:$rd, GPR:$rs1, uimm5:$ls2, uimm5:$ls3)>; +} // Predicates = [IsRV32, HasPULPExtElw] class UnaryBuiltin : Pat<(intrinsic GPR:$rs1), (instruction GPR:$rs1)>; +let Predicates = [IsRV32, HasPULPExtBitop] in { +def : Pat<(int_riscv_pulp_bitinsert GPR:$rd, GPR:$rs1, uimm5:$ls2, uimm5:$ls3), + (P_INSERT GPR:$rd, GPR:$rs1, uimm5:$ls2, uimm5:$ls3)>; + def : UnaryBuiltin; def : UnaryBuiltin; def : UnaryBuiltin; def : UnaryBuiltin; def : Pat<(int_riscv_pulp_parity GPR:$rs1), (P_BCLR (P_CNT GPR:$rs1), 30, 1)>; +def : PatGprGpr; + +def : Pat<(int_riscv_pulp_bclr GPR:$rs1, shiftedFlippedMask:$mask), + (P_BCLR GPR:$rs1, (flippedMaskWidthMinus1 imm:$mask), (trailing1s imm:$mask))>; +def : PatGprGpr; + +def : Pat<(int_riscv_pulp_bset GPR:$rs1, shiftedMask:$mask), + (P_BSET GPR:$rs1, (maskWidthMinus1 imm:$mask), (trailing0s imm:$mask))>; +def : PatGprGpr; + +def : Pat<(int_riscv_pulp_bextract GPR:$rs1, tuimm5:$size, tuimm5:$shift), + (P_EXTRACT GPR:$rs1, tuimm5:$size, tuimm5:$shift)>; +def : PatGprGpr; + +def : Pat<(int_riscv_pulp_bextractu GPR:$rs1, tuimm5:$size, tuimm5:$shift), + (P_EXTRACTU GPR:$rs1, tuimm5:$size, tuimm5:$shift)>; +def : PatGprGpr; + +def : Pat<(int_riscv_pulp_binsert GPR:$rd, shiftedFlippedMask, + GPR:$rs1, shiftedMask:$srcMask, tuimm5:$shift), + (P_INSERT GPR:$rd, GPR:$rs1, (maskWidthMinus1 imm:$srcMask), tuimm5:$shift)>; +def : Pat<(int_riscv_pulp_binsert_r GPR:$rd, GPR:$rs1, GPR:$rs2), + (P_INSERTR GPR:$rd, GPR:$rs1, GPR:$rs2)>; +} // Predicates = [IsRV32, HasPULPExtBitop] + +let Predicates = [IsRV32, HasPULPExtAbs] in { def : UnaryBuiltin; +} // Predicates = [IsRV32, HasPULPExtAbs] +let Predicates = [IsRV32, HasPULPExtMacsi] in { def : Pat<(int_riscv_pulp_mac GPR:$rs1, GPR:$rs2, GPR:$rd), (P_MAC GPR:$rd, GPR:$rs1, GPR:$rs2)>; def : Pat<(int_riscv_pulp_msu GPR:$rs1, GPR:$rs2, GPR:$rd), (P_MSU GPR:$rd, GPR:$rs1, GPR:$rs2)>; +} // Predicates = [IsRV32, HasPULPExtMacsi] +let Predicates = [IsRV32, HasPULPExtPartmac] in { def : Pat<(int_riscv_pulp_macs GPR:$rs1, GPR:$rs2, GPR:$rd), (P_MACS GPR:$rd, GPR:$rs1, GPR:$rs2)>; def : Pat<(int_riscv_pulp_macu GPR:$rs1, GPR:$rs2, GPR:$rd), (P_MACU GPR:$rd, GPR:$rs1, GPR:$rs2)>; def : Pat<(int_riscv_pulp_machhs GPR:$rs1, GPR:$rs2, GPR:$rd), (P_MACHHS GPR:$rd, GPR:$rs1, GPR:$rs2)>; def : Pat<(int_riscv_pulp_machhu GPR:$rs1, GPR:$rs2, GPR:$rd), (P_MACHHU GPR:$rd, GPR:$rs1, GPR:$rs2)>; +} // Predicates = [IsRV32, HasPULPExtPartmac] -def : PatGprGpr; - +let Predicates = [IsRV32, HasPULPExtMinmax] in { def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; +} // Predicates = [IsRV32, HasPULPExtMinmax] +let Predicates = [IsRV32, HasPULPExtVect] in { multiclass BinaryVectorBuiltin { def : PatV2V2("int_riscv_pulp_" # intrin # "2"), !cast("PV_" # instr # "_H")>; @@ -1772,17 +1885,16 @@ multiclass DotproductBuiltin { defm : DotproductBuiltin<"s", "S">; defm : DotproductBuiltin<"u", "U">; defm : DotproductBuiltin<"us", "US">; +} // Predicates = [IsRV32, HasPULPExtVect] +let Predicates = [IsRV32, HasPULPExtMulrnhi] in { def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; def : PatGprGpr; +} // Predicates = [IsRV32, HasPULPExtMulrnhi] -defm : int_mul_mac_N_RN<"s", "S">; -defm : int_mul_mac_N_RN<"u", "U">; -defm : int_mul_mac_N_RN<"hhs", "HHS">; -defm : int_mul_mac_N_RN<"hhu", "HHU">; - +let Predicates = [IsRV32, HasPULPExtAddsubrn] in { multiclass int_N_RN_r { // N: op with normalization factor as immediate def : Pat<(!cast("int_riscv_pulp_" # intrin # "N") @@ -1810,7 +1922,9 @@ defm : int_N_RN_r<"add", "ADD">; defm : int_N_RN_r<"addu", "ADDU">; defm : int_N_RN_r<"sub", "SUB">; defm : int_N_RN_r<"subu", "SUBU">; +} // Predicates = [IsRV32, HasPULPExtAddsubrn] +let Predicates = [IsRV32, HasPULPExtVectshufflepack] in { def : Pat<(int_riscv_pulp_pack2 GPR:$rs1, GPR:$rs2), (PV_PACK_H GPR:$rs2, GPR:$rs1)>; def : Pat<(int_riscv_pulp_pack4 GPR:$rs1, GPR:$rs2, GPR:$rs3, GPR:$rs4), @@ -1825,29 +1939,22 @@ def : Pat<(int_riscv_pulp_shuffle2h PulpV2:$rd, PulpV2:$rs1, PulpV2:$rs2), (PV_SHUFFLE2_H PulpV2:$rd, PulpV2:$rs1, PulpV2:$rs2)>; def : Pat<(int_riscv_pulp_shuffle4b PulpV4:$rd, PulpV4:$rs1, PulpV4:$rs2), (PV_SHUFFLE2_B PulpV4:$rd, PulpV4:$rs1, PulpV4:$rs2)>; +} // Predicates = [IsRV32, HasPULPExtVectshufflepack] -def : Pat<(int_riscv_pulp_bclr GPR:$rs1, shiftedFlippedMask:$mask), - (P_BCLR GPR:$rs1, (flippedMaskWidthMinus1 imm:$mask), (trailing1s imm:$mask))>; -def : PatGprGpr; - -def : Pat<(int_riscv_pulp_bset GPR:$rs1, shiftedMask:$mask), - (P_BSET GPR:$rs1, (maskWidthMinus1 imm:$mask), (trailing0s imm:$mask))>; -def : PatGprGpr; - -def : Pat<(int_riscv_pulp_bextract GPR:$rs1, tuimm5:$size, tuimm5:$shift), - (P_EXTRACT GPR:$rs1, tuimm5:$size, tuimm5:$shift)>; -def : PatGprGpr; +let Predicates = [IsRV32, HasPULPExtPostmod] in { +def : Pat<(int_riscv_pulp_OffsetedRead GPR:$rs1, GPR:$rs2), (P_LW_rr GPR:$rs1, GPR:$rs2)>; +def : Pat<(int_riscv_pulp_OffsetedReadHalf GPR:$rs1, GPR:$rs2), (P_LH_rr GPR:$rs1, GPR:$rs2)>; +def : Pat<(int_riscv_pulp_OffsetedReadByte GPR:$rs1, GPR:$rs2), (P_LB_rr GPR:$rs1, GPR:$rs2)>; -def : Pat<(int_riscv_pulp_bextractu GPR:$rs1, tuimm5:$size, tuimm5:$shift), - (P_EXTRACTU GPR:$rs1, tuimm5:$size, tuimm5:$shift)>; -def : PatGprGpr; +def : Pat<(int_riscv_pulp_OffsetedWrite GPR:$rs2, GPR:$rs1, GPR:$rs3), (P_SW_rr GPR:$rs2, GPR:$rs1, GPR:$rs3)>; +def : Pat<(int_riscv_pulp_OffsetedWriteHalf GPR:$rs2, GPR:$rs1, GPR:$rs3), (P_SH_rr GPR:$rs2, GPR:$rs1, GPR:$rs3)>; +def : Pat<(int_riscv_pulp_OffsetedWriteByte GPR:$rs2, GPR:$rs1, GPR:$rs3), (P_SB_rr GPR:$rs2, GPR:$rs1, GPR:$rs3)>; -def : Pat<(int_riscv_pulp_binsert GPR:$rd, shiftedFlippedMask, - GPR:$rs1, shiftedMask:$srcMask, tuimm5:$shift), - (P_INSERT GPR:$rd, GPR:$rs1, (maskWidthMinus1 imm:$srcMask), tuimm5:$shift)>; -def : Pat<(int_riscv_pulp_binsert_r GPR:$rd, GPR:$rs1, GPR:$rs2), - (P_INSERTR GPR:$rd, GPR:$rs1, GPR:$rs2)>; +def : Pat<(int_riscv_pulp_read_base_off GPR:$rs1, GPR:$rs2), (P_LW_rr GPR:$rs1, GPR:$rs2)>; +def : Pat<(int_riscv_pulp_write_base_off GPR:$rs2, GPR:$rs1, GPR:$rs3), (P_SW_rr GPR:$rs2, GPR:$rs1, GPR:$rs3)>; +} // Predicates = [IsRV32, HasPULPExtPostmod] +let Predicates = [IsRV32, HasPULPExtClip] in { def : Pat<(int_riscv_pulp_clip GPR:$rs1, negativePowerOf2:$lowerBound, powerOf2Minus1), (P_CLIP GPR:$rs1, (trailing0s imm:$lowerBound))>; @@ -1856,18 +1963,9 @@ def : PatGprGpr; def : Pat<(int_riscv_pulp_clipu GPR:$rs1, 0, powerOf2Minus1:$upperBound), (P_CLIPU GPR:$rs1, (trailing1sPlus1 imm:$upperBound))>; def : PatGprGpr; +} // Predicates = [IsRV32, HasPULPExtClip] -def : Pat<(int_riscv_pulp_OffsetedRead GPR:$rs1, GPR:$rs2), (P_LW_rr GPR:$rs1, GPR:$rs2)>; -def : Pat<(int_riscv_pulp_OffsetedReadHalf GPR:$rs1, GPR:$rs2), (P_LH_rr GPR:$rs1, GPR:$rs2)>; -def : Pat<(int_riscv_pulp_OffsetedReadByte GPR:$rs1, GPR:$rs2), (P_LB_rr GPR:$rs1, GPR:$rs2)>; - -def : Pat<(int_riscv_pulp_OffsetedWrite GPR:$rs2, GPR:$rs1, GPR:$rs3), (P_SW_rr GPR:$rs2, GPR:$rs1, GPR:$rs3)>; -def : Pat<(int_riscv_pulp_OffsetedWriteHalf GPR:$rs2, GPR:$rs1, GPR:$rs3), (P_SH_rr GPR:$rs2, GPR:$rs1, GPR:$rs3)>; -def : Pat<(int_riscv_pulp_OffsetedWriteByte GPR:$rs2, GPR:$rs1, GPR:$rs3), (P_SB_rr GPR:$rs2, GPR:$rs1, GPR:$rs3)>; - -def : Pat<(int_riscv_pulp_read_base_off GPR:$rs1, GPR:$rs2), (P_LW_rr GPR:$rs1, GPR:$rs2)>; -def : Pat<(int_riscv_pulp_write_base_off GPR:$rs2, GPR:$rs1, GPR:$rs3), (P_SW_rr GPR:$rs2, GPR:$rs1, GPR:$rs3)>; - +let Predicates = [IsRV32, HasPULPExtV2] in { def : Pat<(int_riscv_pulp_spr_read tuimm12:$csr), (CSRRS csr_sysreg:$csr, X0)>; def : Pat<(int_riscv_pulp_spr_read_vol tuimm12:$csr), @@ -1896,5 +1994,4 @@ def : Pat<(int_riscv_pulp_IsFc), (SRLI (ANDI (CSRRS MHARTID.Encoding, X0), 0b100 // Symbols below must be provided by the platform, no CSR involved // Note: GCC lowers HasFc to zero immediate def : Pat<(int_riscv_pulp_HasFc), (ANDI X0, 0)>; - } // Predicates = [IsRV32, HasPULPExtV2] diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td index 5a3c8deb7943b..2a078401cb246 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td +++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td @@ -20,7 +20,14 @@ def RocketModel : SchedMachineModel { let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, - HasVInstructions, HasVInstructionsI64]; + HasVInstructions, HasVInstructionsI64, HasPULPExtV2, + HasPULPExtHwloop, HasPULPExtPostmod, HasPULPExtIndregreg, + HasPULPExtElw, HasPULPExtAbs, HasPULPExtSlet, + HasPULPExtMacsi, HasPULPExtMulrnhi, HasPULPExtMacrnhi, + HasPULPExtPartmac, HasPULPExtMinmax, HasPULPExtBitop, + HasPULPExtVect, HasPULPExtVectshufflepack, HasPULPExtVectcomplex, + HasPULPExtClip, HasPULPExtAddsubrn, HasPULPExtBr, + HasPULPExtBitrev, HasPULPExtVectgap8, HasPULPExtVectgap9]; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index cfbd9722d7bc6..95d56b018afc6 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -18,7 +18,14 @@ def SiFive7Model : SchedMachineModel { let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, - HasVInstructions]; + HasVInstructions, HasPULPExtV2, + HasPULPExtHwloop, HasPULPExtPostmod, HasPULPExtIndregreg, + HasPULPExtElw, HasPULPExtAbs, HasPULPExtSlet, + HasPULPExtMacsi, HasPULPExtMulrnhi, HasPULPExtMacrnhi, + HasPULPExtPartmac, HasPULPExtMinmax, HasPULPExtBitop, + HasPULPExtVect, HasPULPExtVectshufflepack, HasPULPExtVectcomplex, + HasPULPExtClip, HasPULPExtAddsubrn, HasPULPExtBr, + HasPULPExtBitrev, HasPULPExtVectgap8, HasPULPExtVectgap9]; } // The SiFive7 microarchitecture has two pipelines: A and B. diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index cefdeb2a73806..0600586c1a321 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -61,6 +61,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { RISCVProcFamilyEnum RISCVProcFamily = Others; bool HasPULPExtV2 = false; + bool HasPULPExtHwloop = false; + bool HasPULPExtPostmod = false; + bool HasPULPExtIndregreg = false; + bool HasPULPExtElw = false; + bool HasPULPExtAbs = false; + bool HasPULPExtSlet = false; + bool HasPULPExtMacsi = false; + bool HasPULPExtMulrnhi = false; + bool HasPULPExtMacrnhi = false; + bool HasPULPExtPartmac = false; + bool HasPULPExtMinmax = false; + bool HasPULPExtBitop = false; + bool HasPULPExtVect = false; + bool HasPULPExtVectshufflepack = false; + bool HasPULPExtVectcomplex = false; + bool HasPULPExtClip = false; + bool HasPULPExtAddsubrn = false; + bool HasPULPExtBr = false; + bool HasPULPExtBitrev = false; + bool HasPULPExtVectgap8 = false; + bool HasPULPExtVectgap9 = false; bool HasStdExtM = false; bool HasStdExtA = false; bool HasStdExtF = false; @@ -227,6 +248,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool hasExtXcopift() const { return HasExtXcopift; } bool hasExtXmempool() const { return HasExtXmempool; } bool hasPULPExtV2() const { return HasPULPExtV2; } + bool hasPULPExtHwloop() const { return HasPULPExtHwloop; } + bool hasPULPExtPostmod() const { return HasPULPExtPostmod; } + bool hasPULPExtIndregreg() const { return HasPULPExtIndregreg; } + bool hasPULPExtElw() const { return HasPULPExtElw; } + bool hasPULPExtAbs() const { return HasPULPExtAbs; } + bool hasPULPExtSlet() const { return HasPULPExtSlet; } + bool hasPULPExtMacsi() const { return HasPULPExtMacsi; } + bool hasPULPExtMulrnhi() const { return HasPULPExtMulrnhi; } + bool hasPULPExtMacrnhi() const { return HasPULPExtMacrnhi; } + bool hasPULPExtPartmac() const { return HasPULPExtPartmac; } + bool hasPULPExtMinmax() const { return HasPULPExtMinmax; } + bool hasPULPExtBitop() const { return HasPULPExtBitop; } + bool hasPULPExtVect() const { return HasPULPExtVect; } + bool hasPULPExtVectshufflepack() const { return HasPULPExtVectshufflepack; } + bool hasPULPExtVectcomplex() const { return HasPULPExtVectcomplex; } + bool hasPULPExtClip() const { return HasPULPExtClip; } + bool hasPULPExtAddsubrn() const { return HasPULPExtAddsubrn; } + bool hasPULPExtBr() const { return HasPULPExtBr; } + bool hasPULPExtBitrev() const { return HasPULPExtBitrev; } + bool hasPULPExtVectgap8() const { return HasPULPExtVectgap8; } + bool hasPULPExtVectgap9() const { return HasPULPExtVectgap9; } bool hasExtXsmallfloat() const { return HasExtXfalthalf || HasExtXfquarter || HasExtXfaltquarter || HasExtXfvecsingle || HasExtXfvechalf || HasExtXfvecalthalf || diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 53871493c5e51..e69cead585ca7 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -433,5 +433,5 @@ bool RISCVTTIImpl::isLoweredToCall(const Function *F) { } bool RISCVTTIImpl::shouldFavorPostInc() const { - return ST->hasPULPExtV2(); + return ST->hasPULPExtPostmod(); } diff --git a/llvm/test/CodeGen/RISCV/intrinsics/xpulpmacsi.ll b/llvm/test/CodeGen/RISCV/intrinsics/xpulpmacsi.ll new file mode 100644 index 0000000000000..8c3672593545c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/intrinsics/xpulpmacsi.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=riscv32 -mattr=+xpulpv -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=riscv32 -mattr=+xpulpmacsi -verify-machineinstrs < %s | FileCheck %s + +declare i32 @llvm.riscv.pulp.mac(i32, i32, i32) +define i32 @test_llvm_riscv_pulp_mac() { +; CHECK-LABEL: test_llvm_riscv_pulp_mac: +; CHECK: # %bb.0: +; CHECK-DAG: li [[REG0:a[0-9]+]], 1 +; CHECK-DAG: li [[REG1:a[0-9]+]], 2 +; CHECK-DAG: li [[REG2:a[0-9]+]], 3 +; CHECK-NEXT: p.mac [[REG2]], [[REG0]], [[REG1]] +; + %1 = tail call i32 @llvm.riscv.pulp.mac(i32 1, i32 2, i32 3) + ret i32 %1 +} + +declare i32 @llvm.riscv.pulp.msu(i32, i32, i32) +define i32 @test_llvm_riscv_pulp_msu() { +; CHECK-LABEL: @test_llvm_riscv_pulp_msu +; CHECK: # %bb.0: +; CHECK-DAG: li [[REG0:a[0-9]+]], 1 +; CHECK-DAG: li [[REG1:a[0-9]+]], 2 +; CHECK-DAG: li [[REG2:a[0-9]+]], 10 +; CHECK-NEXT: p.msu [[REG2]], [[REG0]], [[REG1]] +; + %1 = call i32 @llvm.riscv.pulp.msu(i32 1, i32 2, i32 10) + ret i32 %1 +} diff --git a/llvm/test/CodeGen/RISCV/intrinsics/xpulppostmod.ll b/llvm/test/CodeGen/RISCV/intrinsics/xpulppostmod.ll new file mode 100644 index 0000000000000..60135776fc4f2 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/intrinsics/xpulppostmod.ll @@ -0,0 +1,94 @@ +; RUN: llc -march=riscv32 -mattr=+xpulpv -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=riscv32 -mattr=+xpulppostmod -verify-machineinstrs < %s | FileCheck %s + +declare i32 @llvm.riscv.pulp.OffsetedRead(i32*, i32) +define i32 @test_llvm_riscv_pulp_OffsetedRead(i32* %data) { +; CHECK-LABEL: @test_llvm_riscv_pulp_OffsetedRead +; CHECK: # %bb.0: +; CHECK: li [[OFFSET:a[0-9]+]], 4 +; CHECK: p.lw [[PTR:a[0-9]+]], [[OFFSET]]([[PTR]]) +; + %1 = call i32 @llvm.riscv.pulp.OffsetedRead(i32* %data, i32 4) + ret i32 %1 +} + +declare void @llvm.riscv.pulp.OffsetedWrite(i32, i32*, i32) +define void @test_llvm_riscv_pulp_OffsetedWrite(i32* %data) { +; CHECK-LABEL: @test_llvm_riscv_pulp_OffsetedWrite +; CHECK: # %bb.0: +; CHECK-DAG: li [[OFFSET:a[0-9]+]], 4 +; CHECK-DAG: li [[VALUE:a[0-9]+]], 1 +; CHECK: p.sw [[VALUE]], [[OFFSET]]({{a[0-9]+}}) +; + call void @llvm.riscv.pulp.OffsetedWrite(i32 1, i32* %data, i32 4) + ret void +} + +declare i32 @llvm.riscv.pulp.OffsetedReadHalf(i16*, i32) +define i32 @test_llvm_riscv_pulp_OffsetedReadHalf(i16* %data) { +; CHECK-LABEL: @test_llvm_riscv_pulp_OffsetedReadHalf +; CHECK: # %bb.0: +; CHECK: li [[OFFSET:a[0-9]+]], 4 +; CHECK: p.lh [[PTR:a[0-9]+]], [[OFFSET]]([[PTR]]) +; + %1 = call i32 @llvm.riscv.pulp.OffsetedReadHalf(i16* %data, i32 4) + ret i32 %1 +} + +declare void @llvm.riscv.pulp.OffsetedWriteHalf(i32, i16*, i32) +define void @test_llvm_riscv_pulp_OffsetedWriteHalf(i16* %data) { +; CHECK-LABEL: @test_llvm_riscv_pulp_OffsetedWriteHalf +; CHECK: # %bb.0: +; CHECK-DAG: li [[OFFSET:a[0-9]+]], 4 +; CHECK-DAG: li [[VALUE:a[0-9]+]], 1 +; CHECK: p.sh [[VALUE]], [[OFFSET]]({{a[0-9]+}}) +; + call void @llvm.riscv.pulp.OffsetedWriteHalf(i32 1, i16* %data, i32 4) + ret void +} + +declare i32 @llvm.riscv.pulp.OffsetedReadByte(i8*, i32) +define i32 @test_llvm_riscv_pulp_OffsetedReadByte(i8* %data) { +; CHECK-LABEL: @test_llvm_riscv_pulp_OffsetedReadByte +; CHECK: # %bb.0: +; CHECK: li [[OFFSET:a[0-9]+]], 4 +; CHECK: p.lb [[PTR:a[0-9]+]], [[OFFSET]]([[PTR]]) +; + %1 = call i32 @llvm.riscv.pulp.OffsetedReadByte(i8* %data, i32 4) + ret i32 %1 +} + +declare void @llvm.riscv.pulp.OffsetedWriteByte(i32, i8*, i32) +define void @test_llvm_riscv_pulp_OffsetedWriteByte(i8* %data) { +; CHECK-LABEL: @test_llvm_riscv_pulp_OffsetedWriteByte +; CHECK: # %bb.0: +; CHECK-DAG: li [[OFFSET:a[0-9]+]], 4 +; CHECK-DAG: li [[VALUE:a[0-9]+]], 1 +; CHECK: p.sb [[VALUE]], [[OFFSET]]({{a[0-9]+}}) +; + call void @llvm.riscv.pulp.OffsetedWriteByte(i32 1, i8* %data, i32 4) + ret void +} + +declare i32 @llvm.riscv.pulp.read.base.off(i32* %data, i32) +define i32 @test_llvm_riscv_pulp_read_base_off(i32* %data) { +; CHECK-LABEL: @test_llvm_riscv_pulp_read_base_off +; CHECK: # %bb.0: +; CHECK: li [[OFFSET:a[0-9]+]], 15 +; CHECK: p.lw [[PTR:a[0-9]+]], [[OFFSET]]([[PTR]]) +; + %1 = call i32 @llvm.riscv.pulp.read.base.off(i32* %data, i32 15) + ret i32 %1 +} + +declare void @llvm.riscv.pulp.write.base.off(i32, i32*, i32) +define void @test_llvm_riscv_pulp_write_base_off(i32* %data) { +; CHECK-LABEL: @test_llvm_riscv_pulp_write_base_off +; CHECK: # %bb.0: +; CHECK-DAG: li [[OFFSET:a[0-9]+]], 15 +; CHECK-DAG: li [[VALUE:a[0-9]+]], 1 +; CHECK: p.sw [[VALUE]], [[OFFSET]]({{a[0-9]+}}) +; + call void @llvm.riscv.pulp.write.base.off(i32 1, i32* %data, i32 15) + ret void +}