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Bootloader using S25FL128S #16

erikyujui opened this issue Jul 4, 2016 · 2 comments


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commented Jul 4, 2016

Hi guys,
I want to simulate the bootloader with S25FL128S Verilog model.
S25FL128S has port CS, SCK, SI, SO, WP, HOLD.
But S25FL128S is in QSPI mode, some of the port will configure as inout port.
The PULPino SPI sperate the input and output port as SDI and SDO.
How do you connect the S25FL128S to PULPino SPI Master ?

Thank you!!!


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commented Jul 4, 2016


what you need are pad instances, the following should do the job:

module generic_pad
    input  logic in_i,
    output logic out_o,
    inout  logic pad,
    input  logic en_i

  assign out_o = pad;
  assign pad = en_i ? in_i : 1'bZ;


Instantiate the generic pad for each signal coming from your SPI model. Then depending on the SPI mode (single, quad receiving or quad transmitting) you need to enable the output. Use the spi_master_mode_o to decide in which state PULPino's SPI master currently is.

Just for your information: We tested the boot process with Spansion's S25fs256s flash. Depending on how your model may deviate from ours, you may need to adapt the boot code. The readme should clarify the process on how to regenerate the boot code.

Hope this helps.




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commented Jul 4, 2016

Thank you !!!
I will try it.

Best regards

@erikyujui erikyujui closed this Jul 4, 2016

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