{"payload":{"header_redesign_enabled":false,"results":[{"id":"99689233","archived":false,"color":"#DAE1C2","followers":1257,"has_funding_file":false,"hl_name":"lowRISC/ibex","hl_trunc_description":"Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.","language":"SystemVerilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":99689233,"name":"ibex","owner_id":7814611,"owner_login":"lowRISC","updated_at":"2024-05-02T19:53:57.827Z","has_issues":true}},"sponsorable":false,"topics":["hardware","risc-v","rv32","cpucore"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":5,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":58,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AlowRISC%252Fibex%2B%2Blanguage%253ASystemVerilog","metadata":null,"csrf_tokens":{"/lowRISC/ibex/star":{"post":"twPnVPDdPMOBovHljphBKfJKtNyNlbiYAKULZuMTqcosDGYJ-yKQbaFdh2YuB__u39Ng_HlsnpRtOEbUNrb-rw"},"/lowRISC/ibex/unstar":{"post":"Nk9eObBXWLbAlg9ik_7DoMrYS3I6Y0dvtGGzRsdiXDf43_wzpQQInsuH7gZelmLT4sfZw_9x2MO4pxZyi24_Tw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"mus3FVJZAJkayXKUNTGIR9BViZL_s4PvnvyCy5C34LqdfyUFuDPosoKFRIdQ8jZRIVQbVqvxfQALh_9noLQlBQ"}}},"title":"Repository search results"}