diff --git a/CHANGELOG.md b/CHANGELOG.md index 68c868e..284632b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,24 @@ All notable changes to this project will be documented in this file. -## v0.2.0 +## v0.2.1 2025-01-28 + +### Added + + - Added array access to timer CCR registers + - Added py32f040 device + - `scripts/README.md` to show usage of scripts + - modified scripts to handle `bitRange` vs `bitOffset` and `bitWidth` usage in svd files + +### Changed + + - Renamed field `DBG_TIM14_STOP` to `DBG_TIMER14_STOP` in `DBG` peripheral for py32f002b to make it consistent with other devices + +### Removed + + - Removed renaming of timer CCR registers + +## v0.2.0 2024-12-28 ### Added @@ -17,11 +34,11 @@ All notable changes to this project will be documented in this file. - Updated form version from 0.10.0 to 0.12.1 - Updated svdtools version from 0.3.0 to 0.3.14 -## v0.1.1 +## v0.1.1 2024-10-10 -## V0.1.0 +## V0.1.0 2024-09-27 -## v0.0.1 +## v0.0.1 2023-06-10 - Original Release diff --git a/README.md b/README.md index c21115a..ab9032c 100644 --- a/README.md +++ b/README.md @@ -26,7 +26,7 @@ make any guarantee of correctness. Please report any bugs you find! In your own project's `Cargo.toml`: ```toml [dependencies.py32f0] -version = "0.1.1" +version = "0.2.1" features = ["py32f030"] ``` diff --git a/devices/common_patches/adc_rw.yaml b/devices/common_patches/adc_rw.yaml new file mode 100644 index 0000000..b453554 --- /dev/null +++ b/devices/common_patches/adc_rw.yaml @@ -0,0 +1,4 @@ +SR: + _modify: + OVER: + access: read-write diff --git a/devices/common_patches/f002b_dbg.yaml b/devices/common_patches/f002b_dbg.yaml new file mode 100644 index 0000000..fca12ce --- /dev/null +++ b/devices/common_patches/f002b_dbg.yaml @@ -0,0 +1,4 @@ +APB_FZ2: + _modify: + DBG_TIM14_STOP: + name: DBG_TIMER14_STOP diff --git a/devices/common_patches/flash_f040_rename.yaml b/devices/common_patches/flash_f040_rename.yaml new file mode 100644 index 0000000..fdd2ebc --- /dev/null +++ b/devices/common_patches/flash_f040_rename.yaml @@ -0,0 +1,4 @@ +OPTR: + _modify: + NBOOT1: + name: nBOOT1 diff --git a/devices/common_patches/rtc_040_renames.yaml b/devices/common_patches/rtc_040_renames.yaml new file mode 100644 index 0000000..4c91762 --- /dev/null +++ b/devices/common_patches/rtc_040_renames.yaml @@ -0,0 +1,35 @@ +PRLH: + _modify: + PRL: + name: PRLH +PRLL: + _modify: + PRL: + name: PRLL +DIVH: + _modify: + DIV: + name: DIVH +DIVL: + _modify: + DIV: + name: DIVL +CNTH: + _modify: + RTC_CNT: + name: CNTH +CNTL: + _modify: + RTC_CNT: + name: CNTL +ALRH: + _modify: + RTC_ALR: + name: ALRH +ALRL: + _modify: + RTC_ALR: + name: ALRL +_modify: + BKP_RTCCR: + name: RTCCR diff --git a/devices/common_patches/timer_ccr_reg_array.yaml b/devices/common_patches/timer_ccr_reg_array.yaml new file mode 100644 index 0000000..b08a927 --- /dev/null +++ b/devices/common_patches/timer_ccr_reg_array.yaml @@ -0,0 +1,2 @@ +_array: + CCR*: {} diff --git a/devices/common_patches/usart_f040_rename.yaml b/devices/common_patches/usart_f040_rename.yaml new file mode 100644 index 0000000..968997e --- /dev/null +++ b/devices/common_patches/usart_f040_rename.yaml @@ -0,0 +1,10 @@ +BRR: + _modify: + DIV_FRACTION: + name: DIV_Fraction + DIV_MANTISSA: + name: DIV_Mantissa +CR3: + _modify: + ABRMODE: + name: ABRMOD diff --git a/devices/py32f002a.yaml b/devices/py32f002a.yaml index b74f975..9ff2108 100644 --- a/devices/py32f002a.yaml +++ b/devices/py32f002a.yaml @@ -8,6 +8,10 @@ _svd: ../svd/py32f002a.svd _include: - common_patches/usart_dr8.yaml +TIM1: + _include: + - common_patches/timer_ccr_reg_array.yaml + _include: - ./common_patches/pwr_f002a.yaml - ./common_patches/syscfg_f002a.yaml diff --git a/devices/py32f002b.yaml b/devices/py32f002b.yaml index 542f877..5b6778c 100644 --- a/devices/py32f002b.yaml +++ b/devices/py32f002b.yaml @@ -9,6 +9,14 @@ _svd: ../svd/py32f002b.svd _include: - common_patches/usart_dr8.yaml +"DBG": + _include: + - common_patches/f002b_dbg.yaml + +"TIM*": + _include: + - common_patches/timer_ccr_reg_array.yaml + _include: - ./common_patches/syscfg_f002b.yaml - ../peripherals/flash/flash_f002b.yaml diff --git a/devices/py32f003.yaml b/devices/py32f003.yaml index ccf9765..5c4060c 100644 --- a/devices/py32f003.yaml +++ b/devices/py32f003.yaml @@ -12,6 +12,10 @@ _svd: ../svd/py32f003.svd _include: - common_patches/dma_cluster.yaml +"TIM*": + _include: + - common_patches/timer_ccr_reg_array.yaml + _include: - ../peripherals/flash/flash_f0.yaml - ../peripherals/pwr/pwr_f0.yaml diff --git a/devices/py32f030.yaml b/devices/py32f030.yaml index 01a34b1..344fdcf 100644 --- a/devices/py32f030.yaml +++ b/devices/py32f030.yaml @@ -12,6 +12,10 @@ _svd: ../svd/py32f030.svd _include: - common_patches/dma_cluster.yaml +"TIM*": + _include: + - common_patches/timer_ccr_reg_array.yaml + _include: - ../peripherals/flash/flash_f0.yaml - ../peripherals/pwr/pwr_f0.yaml diff --git a/devices/py32f040.yaml b/devices/py32f040.yaml new file mode 100644 index 0000000..cbff295 --- /dev/null +++ b/devices/py32f040.yaml @@ -0,0 +1,48 @@ +_svd: ../svd/py32f040.svd + +"SPI*": + _include: + - common_patches/spi_dr8.yaml + +"USART*": + _include: + - common_patches/usart_dr8.yaml + - common_patches/usart_f040_rename.yaml + +"DMA, DMA[12]": + _include: + - common_patches/dma_cluster.yaml + +"FLASH": + _include: + - common_patches/flash_f040_rename.yaml + +"ADC": + _include: + - common_patches/adc_rw.yaml + +"RTC": + _include: + - common_patches/rtc_040_renames.yaml + +_include: + - ../peripherals/flash/flash_f040.yaml + - ../peripherals/pwr/pwr_f040.yaml + - ../peripherals/rcc/rcc_f040.yaml + - ../peripherals/gpio/gpio_f0.yaml + - ../peripherals/syscfg/syscfg_f040.yaml + - ../peripherals/dma/dma_f0.yaml + - ../peripherals/exti/exti_f0.yaml + - ../peripherals/crc/crc_f0.yaml + - ../peripherals/adc/adc_f040.yaml + - ../peripherals/comp/comp_f040.yaml + - ../peripherals/lcd/lcd_f0.yaml + - ../peripherals/tim/tim_f040.yaml + - ../peripherals/lptim/lptim_f0.yaml + - ../peripherals/iwdg/iwdg_f0.yaml + - ../peripherals/wwdg/wwdg_f0.yaml + - ../peripherals/rtc/rtc_f0.yaml + - ../peripherals/i2c/i2c_f040.yaml + - ../peripherals/usart/usart_f0.yaml + - ../peripherals/spi/spi_f040.yaml + - ../peripherals/dbg/dbg_f0.yaml diff --git a/peripherals/adc/adc_f040.yaml b/peripherals/adc/adc_f040.yaml new file mode 100644 index 0000000..42aaf4e --- /dev/null +++ b/peripherals/adc/adc_f040.yaml @@ -0,0 +1,259 @@ +ADC: + SR: + OVER: + _read: + NoOverload: [0, "No overload occurred"] + Overload: [1, "Overload occurred"] + _write: + Clear: [0, "Clear the overload flag"] + STRT: + _read: + NotStarted: [0, "Rule channel conversion has not started"] + Started: [1, "Rule channel conversion started"] + _W0C: + Clear: [0, "Clear the Rule channel conversion start flag"] + JSTRT: + _read: + NotStarted: [0, "Injection channel conversion has not started"] + Started: [1, "Injection channel conversion started"] + _W0C: + Clear: [0, "Clear the Injection channel conversion start flag"] + JEOC: + _read: + NotComplete: [0, "Injection channel conversion is not complete"] + Complete: [1, "Injection channel conversion complete"] + _W0C: + Clear: [0, "Clear the Injection channel conversion flag"] + EOC: + _read: + NotComplete: [0, "Channel conversion is not complete"] + Complete: [1, "Channel conversion complete"] + _W0C: + Clear: [0, "Clear the channel conversion flag"] + AWD: + _read: + NoEvent: [0, "No analog watchdog event occurred"] + Event: [1, "Analog watchdog event occurred"] + _W0C: + Clear: [0, "Clear the analog watchdog event flag"] + CR1: + _modify: + OVETIE: + name: OVRIE + OVRIE: + Disabled: [0, "Overload interrupt disabled"] + Enabled: [1, "Overload interrupt enabled"] + ADSTP: + _read: + NotStopping: [0, "No stop command active"] + Stopping: [1, "ADC stopping conversion"] + _write: + StopConversion: [1, "Stop the active conversion"] + RESSEL: + TwelveBit: [0, "12 bits"] + TenBit: [1, "10 bits"] + EightBit: [2, "8 bits"] + SixBit: [3, "6 bits"] + AWDEN: + Disabled: [0, "Analog rule channel watchdog disabled"] + Enabled: [1, "Analog rule channel watchdog enabled"] + JAWDEN: + Disabled: [0, "Analog inject channel watchdog disabled"] + Enabled: [1, "Analog inject channel watchdog enabled"] + DISCNUM: [0, 7] + JDISCEN: + Disabled: [0, "Analog inject channel intermittent mode disabled"] + Enabled: [1, "Analog inject channel intermittent mode enabled"] + DISCEN: + Disabled: [0, "Analog rule channel intermittent mode disabled"] + Enabled: [1, "Analog rule channel intermittent mode enabled"] + JAUTO: + Disabled: [0, "Analog auto inject disabled"] + Enabled: [1, "Analog auto inject enabled"] + AWDSGL: + Disabled: [0, "Analog watchdog on single channel disabled"] + Enabled: [1, "Analog watchdog on single channel enabled"] + SCAN: + Off: [0, "Scan mode off"] + On: [1, "Scan mode on"] + JEOCIE: + Disabled: [0, "Injection channel conversion end interrupt disabled"] + Enabled: [1, "Injection channel conversion end interrupt enabled"] + AWDIE: + Disabled: [0, "Analog watchdog interrupt disabled"] + Enabled: [1, "Analog watchdog interrupt enabled"] + EOCIE: + Disabled: [0, "Rule channel conversion end interrupt disabled"] + Enabled: [1, "Rule channel conversion end interrupt enabled"] + AWDCH: [0, 15] + CR2: + _modify: + VERFBUFFERSEL: + name: VREFBUFFSEL + VERFBUFFERE: + name: VREFBUF + VREFBUFFSEL: + OV1_5: [0, "1.5V VREFBUF output voltage"] + OV2_048: [1, "2.048V VREFBUF output voltage"] + OV2_5: [2, "2.5V VREFBUF output voltage"] + Reserved: [3, "Reserved"] + VREFBUF: + Disabled: [0, "Disable VREFBUF"] + Enabled: [1, "Enable VREFBUF"] + TSVREFE: + Disabled: [0, "Temperature sensor and VREFINT disabled"] + Enabled: [1, "Temperature sensor and VREFINT enabled"] + SWSTART: + _read: + Reset: [0, "Rule channel conversion reset"] + Start: [1, "Rule channel conversion started"] + _write: + StartConversion: [1, "Start rule channel conversion"] + JSWSTART: + _read: + Reset: [0, "Injection channel conversion reset"] + Start: [1, "Injection channel conversion started"] + _write: + StartConversion: [1, "Start injection channel conversion"] + EXTTRIG: + Disabled: [0, "External triggering of rule channel disabled"] + Enabled: [1, "External triggering of rule channel enabled"] + EXTSEL: + Timer1Ch1: [0, "Timer1 Channel 1 event"] + Timer1Ch2: [1, "Timer1 Channel 2 event"] + Timer1Ch3: [2, "Timer1 Channel 3 event"] + Timer2Ch2: [3, "Timer2 Channel 2 event"] + Timer3Trgo: [4, "Timer3 TRGO event"] + Timer15Trgo: [5, "Timer15 TRGO event"] + Exti11: [6, "EXTI11 event"] + Swstart: [7, "SWSTART event"] + JEXTTRIG: + Disabled: [0, "Temperature sensor and VREFINT disabled"] + Enabled: [1, "Temperature sensor and VREFINT enabled"] + JEXTSEL: + Timer1Trgo: [0, "Timer1 TRGO event"] + Timer1Ch4: [1, "Timer1 Channel 4 event"] + Timer2Trgo: [2, "Timer2 TRGO event"] + Timer2Ch1: [3, "Timer2 Channel 1 event"] + Timer3Trgo: [4, "Timer3 TRGO event"] + Timer15Trgo: [5, "Timer15 TRGO event"] + Exti15: [6, "EXTI15 event"] + Jswstart: [7, "JSWSTART event"] + ALIGN: + Right: [0, "Right-aligned"] + Left: [1, "Left-aligned"] + DMA: + Disabled: [0, "Temperature sensor and VREFINT disabled"] + Enabled: [1, "Temperature sensor and VREFINT enabled"] + RSTCAL: + _read: + IsInitialized: [0, "Calibration register is initialized"] + Initialized: [1, "Calibration register initialized"] + _write: + Reset: [1, "Calibration reset enable"] + CAL: + _read: + Complete: [0, "Calibration complete"] + Enabled: [1, "Enabled calibration"] + _write: + StartCalibration: [1, "Start calibration"] + CONT: + Single: [0, "Single conversion mode"] + Continuous: [1, "Continuous conversion mode"] + ADON: + Disabled: [0, "Temperature sensor and VREFINT disabled"] + Enabled: [1, "Temperature sensor and VREFINT enabled"] + + SMPR1: + "SMP2?": + Cycles3_5: [0, "3.5 cycles"] + Cycles5_5: [1, "5.5 cycles"] + Cycles7_5: [2, "7.5 cycles"] + Cycles13_5: [3, "13.5 cycles"] + + SMPR2: + "SMP1?": + Cycles3_5: [0, "3.5 cycles"] + Cycles5_5: [1, "5.5 cycles"] + Cycles7_5: [2, "7.5 cycles"] + Cycles13_5: [3, "13.5 cycles"] + + SMPR3: + "SMP?": + Cycles3_5: [0, "3.5 cycles"] + Cycles5_5: [1, "5.5 cycles"] + Cycles7_5: [2, "7.5 cycles"] + Cycles13_5: [3, "13.5 cycles"] + + "JOFR?": + "JOFFSET?": [0, 0xFFF] + + HTR: + HT: [0, 0xFFF] + + LTR: + LT: [0, 0xFFF] + + SQR1: + L: [0, 0xf] + "SQ1?": [0, 0x1f] + + SQR2: + "SQ*": [0, 0x1f] + + SQR3: + "SQ?": [0, 0x1f] + + JSQR: + JL: + Conversion1: [0, "1 Conversion"] + Transition2: [1, "2 Transitions"] + Conversion3: [2, "3 Conversions"] + Transition4: [3, "4 Transitions"] + "JSQ?": [0, 0x1f] + + "JDR?": + "JDR?": [0, 0xffff] + + DR: + DATA: [0, 0xffff] + + CCSR: + _modify: + CALFAIL: + name: CAPSUC + CALON: + InProgress: [0, "ADC calibration in progress"] + Completed: [1, "ADC calibration completed or has not been initiated"] + CAPSUC: + _read: + NotSuccessful: [0, "Capacitance calibration not successful"] + Successful: [1, "Capacitance calibration successful"] + _write: + Clear: [1, "Set to zero"] + OFFSUC: + _read: + NotSuccessful: [0, "Offset calibration not successful"] + Successful: [1, "Offset calibration successful"] + _write: + Clear: [1, "Set to zero"] + CALSET: + _read: + Valid: [0, "Capacitance factor selection valid"] + NotValid: [1, "Capacitance factor not valid"] + _write: + Clear: [1, "Clear"] + CALBYP: + _read: + Valid: [0, "Calibration factor bypass not successful"] + NotValid: [1, "Calibration factor bypass successful"] + _write: + Clear: [1, "Clear"] + CALSMP: + Clock1: [0, "1 ADC clock period"] + Clock2: [1, "2 ADC clock periods"] + Clock4: [2, "4 ADC clock periods"] + Clock8: [3, "8 ADC clock periods"] + CALSEL: + OffsetLinearity: [0, "Calibration of OFFSET and linearity"] + Offset: [1, "Calibration of OFFSET only"] diff --git a/peripherals/comp/comp_f040.yaml b/peripherals/comp/comp_f040.yaml new file mode 100644 index 0000000..4a9a40b --- /dev/null +++ b/peripherals/comp/comp_f040.yaml @@ -0,0 +1,72 @@ +"COMP?": + CSR: + _modify: + COMP_OUT: + name: VALUE + VALUE: + _read: + Low: [0, "Comparator output is low"] + High: [1, "Comparator output is high"] + PWRMODE: + HighSpeed: [0, "High speed 250 ua"] + MediumSpeed: [1, "Medium speed 5 ua"] + HYST: + No: [0, "no Comp1 hysteresis"] + Yes: [1, "Comp1 hysteresis voltage approx 20mV"] + POLARITY: + NotInverted: [0, "Output is not inverted"] + Inverted: [1, "Output is inverted"] + WINMODE: + Disabled: [0, ""] + Enabled: [1, ""] + INPSEL: + Inp0: [0, "COMP1_INP0 from PC0"] + Inp1: [1, "COMP1_INP1 from PC1"] + Inp2: [2, "COMP1_INP2 from PC2"] + Inp3: [3, "COMP1_INP3 from PC3"] + Inp4: [4, "COMP1_INP4 from PA0"] + Inp5: [5, "COMP1_INP5 from PA1"] + Inp6: [6, "COMP1_INP6 from PA2"] + Inp7: [7, "COMP1_INP7 from PA3"] + Inp8: [8, "COMP1_INP8 from PA4"] + Inp9: [9, "COMP1_INP9 from PA5"] + Inp10: [10, "COMP1_INP10 from PA6"] + Inp11: [11, "COMP1_INP11 from PA7"] + Inp12: [12, "COMP1_INP12 from PB4"] + Inp13: [13, "COMP1_INP13 from PB5"] + Inp14: [14, "COMP1_INP14 from PB6"] + INMSEL: + Inm0: [0, "COMP1_INM0 from PA0"] + Inm1: [1, "COMP1_INM1 from PA1"] + Inm2: [2, "COMP1_INM2 from PA2"] + Inm3: [3, "COMP1_INM3 from PA3"] + Inm4: [4, "COMP1_INM4 from PA4"] + Inm5: [5, "COMP1_INM5 from PA5"] + Inm6: [6, "COMP1_INM6 from PA6"] + Inm7: [7, "COMP1_INM7 from PA7"] + Inm8: [8, "COMP1_INM8 from PC4"] + Inm9: [9, "COMP1_INM9 from PC5"] + Inm11: [10, "COMP1_INM11 from resistor voltage divider"] + Inm12: [11, "COMP1_INM12 from TS_VIN"] + Inm13: [12, "COMP1_INM13 from VREF1P2"] + Inm14: [13, "COMP1_INM14 from VREFBUF"] + Inm15: [14, "COMP1_INM15 from OPA1_VIN"] + EN: + Disabled: [0, "Comparator 1 disabled"] + Enabled: [1, "Comparator 1 enabled"] + + FR: + "FLTCNT?": [0, 0xffff] + "FLTEN?": + Disabled: [0, "Comparator digital filter disabled"] + Enabled: [1, "Comparator digital filter enabled"] + +COMP1: + CSR: + VCSEL: + Vcc: [0, "VCC"] + AdcRef: [1, "ADC reference voltage"] + VCDIV_EN: + Disabled: [0, "Voltage division not enabled"] + Enabled: [1, "Voltage division enabled"] + VCDIV: [0, 0x3f] diff --git a/peripherals/flash/flash_f040.yaml b/peripherals/flash/flash_f040.yaml new file mode 100644 index 0000000..e30a323 --- /dev/null +++ b/peripherals/flash/flash_f040.yaml @@ -0,0 +1,81 @@ +FLASH: + ACR: + LATENCY: + WS0: [0, "0 wait states"] + WS1: [1, "1 wait state"] + + KEYR: + KEY: [0, 0xFFFFFFFF] + + OPTKEYR: + OPTKEY: [0, 0xFFFFFFFF] + + SR: + EOP: + NoEvent: [0, "No EOP operation occurred"] + Event: [1, "An EOP event occurred"] + WRPERR: + NoError: [0, "No write protection error occurred"] + Error: [1, "A write protection error occurred"] + OPTVERR: + NoError: [0, "No option and Engineering bits loading validity error occurred"] + Error: [1, " An option and Engineering bits loading validity error occurred"] + BSY: + _read: + Inactive: [0, "No write/erase operation is in progress"] + Active: [1, "A write/erase operation is in progress"] + + CR: + OBL_LAUNCH: + Inactive: [0, "Force option byte loading inactive"] + Active: [1, "Force option byte loading active"] + EOPIE: + Disabled: [0, "End of operation interrupt disabled"] + Enabled: [1, "End of operation interrupt enabled"] + ERRIE: + Disabled: [0, "Error interrupt generation disabled"] + Enabled: [1, "Error interrupt generation enabled"] + OPTLOCK: + Unlocked: [0, "Options is unlocked"] + Locked: [1, "Options is locked"] + LOCK: + Unlocked: [0, "FLASH_CR register is unlocked"] + Locked: [1, "FLASH_CR register is locked"] + _modify: + PGTSTRT: + name: PGSTRT + Start: [1, "Flash main memory program start"] + OPTSTRT: + OptionByteProgram: [1, "Option byte program start"] + SER: + SectorErase: [1, "Erase activated for user sectors"] + MER: + MassErase: [1, "Erase activated for all user sectors"] + PER: + PageErase: [1, "Erase activated for selected page"] + PG: + Program: [1, "Flash programming activated"] + OPTR: + nBOOT1: + Clear: [0, "Select boot mode together with BOOT Pin"] + Set: [1, "Select boot mode together with BOOT Pin"] + NRST_MODE: + NRST: [0, "Configure as NRST pin"] + GPIO: [1, "Configure as GPIO pin"] + WWDG_SW: + Hardware: [0, "Hardware window watchdog"] + Software: [1, "Software window watchdog"] + _modify: + IDWG_SW: + name: IWDG_SW + Hardware: [0, "Hardware independent watchdog"] + Software: [1, "Software independent watchdog"] + RDP: + Level0: [0xAA, "Level 0, readout protection not active"] + Level2: [0xCC, "Level 2, chip readout protection active"] + # The manual specifies "Others" for Level 1, 0x88 is arbitrary + # Since the reset value is AA, the value for Level 1 needs to be written + # so there is no conflict reading other values (unless unsafe is used) + Level1: [0x88, "Level 1, memories readout protection active (writes 0x88)"] + WRPR: + WRP: [0, 0xFFFF] diff --git a/peripherals/i2c/i2c_f040.yaml b/peripherals/i2c/i2c_f040.yaml new file mode 100644 index 0000000..7ebdb0b --- /dev/null +++ b/peripherals/i2c/i2c_f040.yaml @@ -0,0 +1,189 @@ +"I2C*": + CR1: + SWRST: + NotReset: [0, "I2C peripheral not under reset"] + Reset: [1, "I2C peripheral under reset"] + ALERT: + Release: [0, "Release the SMBAlert pin to make it high"] + Drive: [1, "Drive the SMBAlert pin to make it low"] + PEC: + NoErrorCheck: [0, "no Packet error correction transmission"] + ErrorCheckOn: [1, "Packet error correction transmission"] + POS: + Current: [0, "ACK bit controls the (N)ACK of the current byte being received"] + Next: [1, "ACK bit controls the (N)ACK of the next byte to be received"] + ACK: + NAK: [0, "No acknowledge returned"] + ACK: [1, "Acknowledge returned after a byte is received"] + STOP: + NoStop: [0, "No Stop generation"] + Stop: [1, "In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte"] + START: + NoStart: [0, "No Start generation"] + Start: [1, "In master mode: repeated start generation, in slave mode: start generation when bus is free"] + NOSTRETCH: + Enabled: [0, "Clock stretching enabled"] + Disabled: [1, "Clock stretching disabled"] + ENGC: + Disabled: [0, "General call disabled"] + Enabled: [1, "General call enabled"] + ENPEC: + Disabled: [0, "PEC calculation disabled"] + Enabled: [1, "PEC calculation enabled"] + ENARP: + Disabled: [0, "ARP disabled"] + Enabled: [1, "ARP enabled"] + SMBTYPE: + Device: [0, "SMB device"] + Host: [1, "SMB host"] + SMBUS: + I2c: [0, "I2c mode"] + SMBus: [1, "SMBus mode"] + PE: + Disabled: [0, "Peripheral disabled"] + Enabled: [1, "Peripheral enabled"] + + CR2: + LAST: + NotLast: [0, "Next DMA EOT is not the last transfer"] + Last: [1, "Next DMA EOT is the last transfer"] + DMAEN: + Disabled: [0, "DMA requests disabled"] + Enabled: [1, "DMA request enabled when TxE=1 or RxNE=1"] + ITBUFEN: + Disabled: [0, "TxE=1 or RxNE=1 does not generate any interrupt"] + Enabled: [1, "TxE=1 or RxNE=1 generates Event interrupt"] + ITEVTEN: + Disabled: [0, "Event interrupt disabled"] + Enabled: [1, "Event interrupt enabled"] + ITERREN: + Disabled: [0, "Error interrupt disabled"] + Enabled: [1, "Error interrupt enabled"] + FREQ: [4, 50] + + OAR1: + ADDMODE: + SevenBit: [0, "7-bit slave address (does not respond to a 10-bit address)"] + TenBit: [1, "10-bit slave address (does not respond to a 7-bit address)"] + ADD8_9: [0, 3] + ADD1_7: [0, 0x7f] + ADD0: [0, 1] + + OAR2: + ADD2: [0, 127] + ENDUAL: + Disabled: [0, "in 7-bit adddress mode, only OAR1 is recognized"] + Enabled: [1, "in 7-bit adddress mode, both OAR1 and OAR2 are recognized"] + + DR: + DR: [0, 0xFF] + + SR1: + SMBALERT: + _read: + NoAlert: [0, "No SMBAlert"] + Alert: [1, "SMBAlert Event"] + _W0C: + Clear: [0, "Clear flag"] + TIMEOUT: + _read: + NoTimeout: [0, "No timeout error"] + Timeout: [1, "Timeout"] + _W0C: + Clear: [0, "Clear flag"] + PECERR: + _read: + NoError: [0, "no PEC error: receiver returns ACK after PEC reception (if ACK=1)"] + Error: [1, "PEC error: receiver returns NACK after PEC reception (whatever ACK)"] + _W0C: + Clear: [0, "Clear flag"] + OVR: + _read: + NoOverrun: [0, "No overrun/underrun occured"] + Overrun: [1, "Overrun/underrun occured"] + _W0C: + Clear: [0, "Clear flag"] + AF: + _read: + NoFailure: [0, "No acknowledge failure"] + Failure: [1, "Acknowledge failure"] + _W0C: + Clear: [0, "Clear flag"] + ARLO: + _read: + NoLost: [0, "No Arbitration Lost detected"] + Lost: [1, "Arbitration Lost detected"] + _W0C: + Clear: [0, "Clear flag"] + BERR: + _read: + NoError: [0, "No misplaced Start or Stop condition"] + Error: [1, "Misplaced Start or Stop condition"] + _W0C: + Clear: [0, "Clear flag"] + _modify: + TxE: + name: TXE + RxNE: + name: RXNE + TXE: + NotEmpty: [0, "Data register not empty"] + Empty: [1, "Data register empty"] + RXNE: + Empty: [0, "Data register empty"] + NotEmpty: [1, "Data register not empty"] + STOPF: + NoStop: [0, "No Stop condition detected"] + Stop: [1, "Stop condition detected"] + ADD10: + NoEvent: [0, "No ADD10 event occurred"] + Sent: [1, "Master device has sent the first address out"] + BTF: + NotFinished: [0, "Data byte transfer not done"] + Finished: [1, "Data byte transfer successful"] + ADDR: + NoMatch: [0, "Address does not match"] + Match: [1, "Address matched"] + SB: + NoStart: [0, "No Start condition"] + Start: [1, "Start condition generated"] + + SR2: + PEC: [0, 1] + DUALF: + Oar1: [0, "Received address matches OAR1"] + Oar2: [1, "Received address matches OAR2"] + SMBHOST: + NotRecv: [0, "SMBus host address not received"] + Recv: [1, "SMBus host address received"] + SMBDEFAULT: + NoDefault: [0, "Default address of SMBus device not received"] + Default: [1, "Default address of SMBus device received"] + GENCALL: + _read: + NoGeneralCallRecv: [0, "Not receive general call address"] + GeneralCallRecv: [1, "When ENGC=1, received a general call address"] + TRA: + _read: + Received: [0, "Data received flag"] + Transferred: [1, "Data transferred flag"] + BUSY: + _read: + NotBusy: [0, "No communication on bus"] + Busy: [1, "Bus busy"] + MSL: + _read: + Slave: [0, "Slave mode"] + Master: [1, "Master mode"] + + CCR: + FS: + Standard: [0, "Standard mode I2C"] + Fast: [1, "Fast mode I2C"] + DUTY: + Duty2_1: [0, "Duty cycle t_low/t_high = 2/1"] + Duty16_9: [1, "Duty cycle t_low/t_high = 16/9"] + CCR: [1, 0xFFF] + + TRISE: + TRISE: [0, 0x3F] diff --git a/peripherals/iwdg/iwdg_f0.yaml b/peripherals/iwdg/iwdg_f0.yaml index c9af236..8d35998 100644 --- a/peripherals/iwdg/iwdg_f0.yaml +++ b/peripherals/iwdg/iwdg_f0.yaml @@ -17,7 +17,7 @@ RLR: RL: [0, 4095] SR: - WVU: + ?~WVU: Idle: [0, "No update on-going"] Busy: [1, "Update on-going"] RVU: @@ -26,5 +26,5 @@ PVU: Idle: [0, "No update on-going"] Busy: [1, "Update on-going"] - WINR: + ?~WINR: WIN: [0, 4095] diff --git a/peripherals/lcd/lcd_f0.yaml b/peripherals/lcd/lcd_f0.yaml new file mode 100644 index 0000000..7003fa0 --- /dev/null +++ b/peripherals/lcd/lcd_f0.yaml @@ -0,0 +1,146 @@ +LCD: + CR0: + CONTRAST: [0, 0xf] + BSEL: + Ext: [0, "External resistor mode, external circuitry required"] + IntMed: [2, " Internal resistive divider, medium power consumption mode"] + IntSm: [4, "Internal resistive voltage divider, small power consumption mode"] + IntHi: [6, "Internal resistive voltage divider, high power mode"] + DUTY: + Static: [0, "Static"] + Duty2: [1, "1/2 duty"] + Duty3: [2, "1/3 duty"] + Duty4: [3, "1/4 duty"] + Duty6: [5, "1/6 duty"] + Duty8: [7, "1/8 duty"] + BIAS: + Bias3: [0, "1/3 bias"] + Bias2: [1, "1/2 bias"] + LCDCLK: + Hz64: [0, "64 Hz"] + Hz128: [1, "128 Hz"] + Hz256: [2, "256 Hz"] + Hz512: [3, "512 Hz"] + EN: + Disabled: [0, "LCD disabled"] + Enabled: [1, "LCD enabled"] + + CR1: + INTF: + NoInterrupt: [0, "No Interrupt"] + Interrupt: [1, "Interrupt"] + DMAEN: + Disabled: [0, "Disable LCD interrupt triggered DMA"] + Enabled: [1, "Enables LCD interrupt triggering DMA"] + IE: + Disabled: [0, "Interrupt disabled"] + Enabled: [1, "Interrupt enabled"] + MODE: + Mode0: [0, "Mode 0"] + Mode1: [1, "Mode 1"] + BLINKEN: + Disabled: [0, "LCD splash screen disabled"] + Enabled: [1, "LCD splash screen enabled"] + BLINKCNT: [0, 0x3f] + + INTCLR: + INTF_CLR: + _W0C: + Clear: [0, "Clear flag"] + + POEN0: + S31: + S30: + S29: + S28: + S27: + S26: + S25: + S24: + S23: + S22: + S21: + S20: + S19: + S18: + S17: + S16: + S15: + S14: + S13: + S12: + S11: + S10: + S9: + S8: + S7: + S6: + S5: + S4: + S3: + S2: + S1: + S0: + + POEN1: + MUX: + C3: + C2: + C1: + C0: + S36C7: + S37C6: + S38C5: + S39C4: + S35: + S34: + S33: + S32: + + RAM0: + D: + + RAM1: + D: + + RAM2: + D: + + RAM3: + D: + + RAM4: + D: + + RAM5: + D: + + RAM6: + D: + + RAM7: + D: + + RAM8: + D: + + RAM9: + D: + + RAM10: + D: + + RAM11: + D: + + RAM12: + D: + + RAM13: + D: + + RAM14: + D: + + RAM15: + D: diff --git a/peripherals/pwr/pwr_f040.yaml b/peripherals/pwr/pwr_f040.yaml new file mode 100644 index 0000000..d45fb17 --- /dev/null +++ b/peripherals/pwr/pwr_f040.yaml @@ -0,0 +1,57 @@ +PWR: + CR1: + _modify: + LPR: + name: LPRUN + LPRUN: + MainMode: [0, "Voltage regulator in Main mode in Low-power run mode"] + LowPowerMode: [1, "Voltage regulator in low-power mode in Low-power run mode"] + HSION_CTRL: + WaiteMR: [0, "Enable HSI after MR is stable"] + WakeOnVR: [1, "Enable HSI when VR is on (enable HSI immediately when wakeup)"] + VOS: + V1_2: [0, "1.2 V (range 1)"] + V1_0: [1, "1.0 V (range 2)"] + DBP: + Disabled: [0, "Access to RTC, RTC Backup and RCC CSR registers disabled"] + Enabled: [1, "Access to RTC, RTC Backup and RCC CSR registers enabled"] + BIAS_CR_SEL: + FactoryConfig: [0, "Bias config from factory config bytes"] + BiasCR: [1, "Bias config from BIAS_CR register"] + BIAS_CR: + [0, 15] + CR2: + FLT_TIME: + T30us: [0, "Filter time is about 30 us"] + T60us: [1, "Filter time is about 60 us"] + T120us: [2, "Filter time is about 120 us"] + T480us: [3, "Filter time is about 480 us"] + T1_92ms: [4, "Filter time is about 1.92 ms"] + T3_8ms: [5, "Filter time is about 3.8 ms"] + T30_7ms: [6, "Filter time is about 30.7 ms"] + FLTEN: + Disabled: [0, "Digital filter disabled"] + Enabled: [1, "Digital filter enabled"] + PVDT: + V1_8: [0, "1.8 V"] + V2_0: [1, "2.0 V"] + V2_2: [2, "2.2 V"] + V2_4: [3, "2.4 V"] + V2_6: [4, "2.6 V"] + V2_8: [5, "2.8 V"] + V3_0: [6, "3.0 V"] + V3_2: [7, "3.2 V"] + _modify: + SRCSEL: + name: PVD_SRCSEL + PVD_SRCSEL: + Vcc: [0, "VCC as detector source"] + PB7: [1, "PB7 pin as detector source"] + PVDE: + Disabled: [0, "PVD Disabled"] + Enabled: [1, "PVD Enabled"] + SR: + PVDO: + _read: + AboveThreshold: [0, "VDD is higher than the PVD threshold selected with the PLS[2:0] bits"] + BelowThreshold: [1, "VDD is lower than the PVD threshold selected with the PLS[2:0] bits"] diff --git a/peripherals/rcc/rcc_f040.yaml b/peripherals/rcc/rcc_f040.yaml new file mode 100644 index 0000000..45d42f0 --- /dev/null +++ b/peripherals/rcc/rcc_f040.yaml @@ -0,0 +1,209 @@ +RCC: + CR: + "*ON": + Off: [0, "Clock disabled"] + On: [1, "Clock enabled"] + PLLRDY: + _read: + Unlocked: [0, "PLL unlocked"] + Locked: [1, "PLL locked"] + HSEBYP: + NotBypassed: [0, "HSE oscillator not bypassed"] + Bypassed: [1, "HSE oscillator bypassed"] + "HSERDY,HSIRDY": + _read: + NotReady: [0, "Oscillator is not stable"] + Ready: [1, "Oscillator is stable"] + HSIDIV: + NotDivided: [0, "no HSI division requested"] + Div2: [1, "HSI division by 2 requested"] + Div4: [2, "HSI division by 4 requested"] + Div8: [3, "HSI division by 8 requested"] + Div16: [4, "HSI division by 16 requested"] + Div32: [5, "HSI division by 32 requested"] + Div64: [6, "HSI division by 64 requested"] + Div128: [7, "HSI division by 128 requested"] + ICSCR: + LSI_TRIM: [0, 255] + HSI_FS: + Freq4MHz: [0, "Select internal 4 MHz oscilator"] + Freq8MHz: [1, "Select internal 8 MHz oscilator"] + Freq16MHz: [2, "Select internal 16 MHz oscilator"] + Freq22_12MHz: [3, "Select internal 22.12 MHz oscilator"] + Freq24MHz: [4, "Select internal 24 MHz oscilator"] + HSI_TRIM: [0, 31] + CFGR: + MCOPRE: + NotDivided: [0, "No division"] + Div2: [1, "Division by 2"] + Div4: [2, "Division by 4"] + Div8: [3, "Division by 8"] + Div16: [4, "Division by 16"] + Div32: [5, "Division by 32"] + Div64: [6, "Division by 64"] + Div128: [7, "Division by 128"] + MCOSEL: + NoClock: [0, "No clock"] + SYSCLK: [1, "SYSCLK clock selected"] + Reserved: [2, "Reserved"] + HSI: [3, "MSI oscillator clock selected"] + HSE: [4, "HSE oscillator clock selected"] + PLL: [5, "PLL clock selected"] + LSI: [6, "LSI oscillator clock selected"] + LSE: [7, "LSE oscillator clock selected"] + PPRE: + NotDivided: [3, "HCLK not divided"] + Div2: [4, "HCLK divided by 2"] + Div4: [5, "HCLK divided by 4"] + Div8: [6, "HCLK divided by 8"] + Div16: [7, "HCLK divided by 16"] + HPRE: + NotDivided: [7, "system clock not divided"] + Div2: [8, "system clock divided by 2"] + Div4: [9, "system clock divided by 4"] + Div8: [10, "system clock divided by 8"] + Div16: [11, "system clock divided by 16"] + Div64: [12, "system clock divided by 64"] + Div128: [13, "system clock divided by 128"] + Div256: [14, "system clock divided by 256"] + Div512: [15, "system clock divided by 512"] + SWS: + HSISYS: [0, "HSI oscillator used as system clock"] + HSE: [1, "HSE oscillator used as system clock"] + PLL: [2, "PLL used as system clock"] + LSI: [3, "LSI oscillator used as system clock"] + LSE: [4, "LSE oscillator used as system clock"] + SW: + HSISYS: [0, "HSI oscillator used as system clock"] + HSE: [1, "HSE oscillator used as system clock"] + PLL: [2, "PLL used as system clock"] + LSI: [3, "LSI oscillator used as system clock"] + LSE: [4, "LSE oscillator used as system clock"] + PLLCFGR: + PLLSRC: + HSI: [0, "HSI selected as PLL input clock"] + HSE: [1, "HSE selected as PLL input clock"] + ECSCR: + LSE_STARTUP: + ClockCycles1: [0, "LSEBYP=0 4096 LSE clock cycles, LSEBYP=1 2048 LSE clock cycles"] + ClockCycles2: [1, "LSEBYP=0 2048 LSE clock cycles, LSEBYP=1 1024 LSE clock cycles"] + ClockCycles3: [2, "LSEBYP=0 8192 LSE clock cycles, LSEBYP=1 4096 LSE clock cycles"] + DirectOutput: [3, "Direct Output, regardless of stabilization time"] + LSE_DRIVER: + Disabled: [0, "Disable LSE drive"] + Low: [1, "Lowest drive"] + Medium: [2, "Medium drive"] + High: [3, "Highest drive"] + HSE_STARTUP: + ClockCycles1: [0, "HSEBYP=0 4096 LSE clock cycles, HSEBYP=1 2048 LSE clock cycles"] + ClockCycles2: [1, "HSEBYP=0 2048 LSE clock cycles, HSEBYP=1 1024 LSE clock cycles"] + ClockCycles3: [2, "HSEBYP=0 8192 LSE clock cycles, HSEBYP=1 4096 LSE clock cycles"] + DirectOutput: [3, "Direct Output, regardless of stabilization time"] + HSE_DRV: + Disabled: [0, "Disable HSE drive"] + Low: [1, "Lowest drive"] + Medium: [2, "Medium drive"] + High: [3, "Highest drive"] + CIER: + "*RDYIE": + Disabled: [0, "Ready interrupt disabled"] + Enabled: [1, "Ready interrupt enabled"] + CIFR: + CSSF: + NoClock: [0, "No clock security interrupt caused by HSE clock failure"] + Clock: [1, "Clock security interrupt caused by HSE clock failure"] + LSECSSF: + NoFailure: [0, "No failure detected on LSE clock failure"] + Failure: [1, "Failure detected on LSE clock failure"] + "*RDYF": + _read: + NotInterrupted: [0, "No clock ready interrupt"] + Interrupted: [1, "Clock ready interrupt"] + CICR: + LSECSSC: + _write: + Clear: [1, "Clear LSE clock secure system interrupt flag"] + "*SEC,*RDYC": + _write: + Clear: [1, "Clear interrupt flag"] + IOPRSTR: + "*RST": + Reset: [1, "Reset I/O port"] + IOPENR: + "*EN": + Disabled: [0, "Port clock disabled"] + Enabled: [1, "Port clock enabled"] + AHBRSTR: + "*RST": + _write: + Reset: [1, "Reset the module"] + "APBRSTR?": + "*RST": + _write: + Reset: [1, "Reset the module"] + AHBENR: + "*EN": + Disabled: [0, "Clock disabled"] + Enabled: [1, "Clock enabled"] + "APBENR?": + "*EN": + Disabled: [0, "Clock disabled"] + Enabled: [1, "Clock enabled"] + CCIPR: + LPTIM1SEL: + PCLK: [0, "APB clock selected as Timer clock"] + LSI: [1, "LSI clock selected as Timer clock"] + Reserved: [2, "No clock selected (Reserved)"] + LSE: [3, "LSE clock selected as Timer clock"] + "COMP?SEL, PVDSEL": + PCLK: [0, "APB clock selected as Timer clock"] + LSC: [1, "LSC clock (LSI or LSE selected by LSCOSEL) selected as Timer clock"] + BDCR: + LSCOSEL: + LSI: [0, "LSI clock selected"] + LSE: [1, "LSE clock selected"] + LSCOEN: + Disabled: [0, "LSCO disabled"] + Enabled: [1, "LSCO enabled"] + BDRST: + Disabled: [0, "Reset not activated"] + Enabled: [1, "Reset the entire RTC domain"] + RTCEN: + Disabled: [0, "RTC clock disabled"] + Enabled: [1, "RTC clock enabled"] + RTCSEL: + NoClock: [0, "No clock"] + LSE: [1, "LSE oscillator clock used as RTC clock"] + LSI: [2, "LSI oscillator clock used as RTC clock"] + HSE: [3, "HSE oscillator clock divided by a prescaler used as RTC clock"] + LSECSSD: + _read: + NoFailure: [0, "No failure detected on LSE (32 kHz oscillator)"] + Failure: [1, "Failure detected on LSE (32 kHz oscillator)"] + LSECSSON: + "Off": [0, "CSS on LSE (32 kHz external oscillator) OFF"] + "On": [1, "CSS on LSE (32 kHz external oscillator) ON"] + LSEBYP: + NotBypassed: [0, "LSE crystal oscillator not bypassed"] + Bypassed: [1, "LSE crystal oscillator bypassed with external clock"] + LSERDY: + _read: + NotReady: [0, "LSE oscillator not ready"] + Ready: [1, "LSE oscillator ready"] + LSEON: + "Off": [0, "LSE oscillator Off"] + "On": [1, "LSE oscillator On"] + CSR: + "*ON": + "Off": [0, "Oscillator OFF"] + "On": [1, "Oscillator ON"] + "*RDY": + NotReady: [0, "Oscillator not ready"] + Ready: [1, "Oscillator ready"] + "*RSTF": + _read: + NoReset: [0, "No reset has occured"] + Reset: [1, "A reset has occured"] + RMVF: + _write: + Clear: [1, "Clears the reset flag"] diff --git a/peripherals/spi/spi_f040.yaml b/peripherals/spi/spi_f040.yaml new file mode 100644 index 0000000..856ca3e --- /dev/null +++ b/peripherals/spi/spi_f040.yaml @@ -0,0 +1,105 @@ +"SPI*": + CR1: + BIDIMODE: + Unidirectional: [0, "2-line unidirectional data mode selected"] + Bidirectional: [1, "1-line bidirectional data mode selected"] + BIDIOE: + OutputDisabled: [0, "Output disabled (receive-only mode)"] + OutputEnabled: [1, "Output enabled (transmit-only mode)"] + RXONLY: + FullDuplex: [0, "Full duplex (Transmit and receive)"] + OutputDisabled: [1, "Output disabled (Receive-only mode)"] + SSM: + Disabled: [0, "Software slave management disabled"] + Enabled: [1, "Software slave management enabled"] + SSI: + SlaveSelected: [0, "0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] + SlaveNotSelected: [1, "1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] + LSBFIRST: + MSBFirst: [0, "Data is transmitted/received with the MSB first"] + LSBFirst: [1, "Data is transmitted/received with the LSB first"] + SPE: + Disabled: [0, "Peripheral disabled"] + Enabled: [1, "Peripheral enabled"] + BR: + Div2: [0, "f_PCLK / 2"] + Div4: [1, "f_PCLK / 4"] + Div8: [2, "f_PCLK / 8"] + Div16: [3, "f_PCLK / 16"] + Div32: [4, "f_PCLK / 32"] + Div64: [5, "f_PCLK / 64"] + Div128: [6, "f_PCLK / 128"] + Div256: [7, "f_PCLK / 256"] + MSTR: + Slave: [0, "Slave configuration"] + Master: [1, "Master configuration"] + CPOL: + IdleLow: [0, "CK to 0 when idle"] + IdleHigh: [1, "CK to 1 when idle"] + CPHA: + FirstEdge: [0, "The first clock transition is the first data capture edge"] + SecondEdge: [1, "The second clock transition is the first data capture edge"] + CR2: + LDMA_TX: + Even: [0, "Number of data to transfer for transmit is even"] + Odd: [1, "Number of data to transfer for transmit is odd"] + LDMA_RX: + Even: [0, "Number of data to transfer for receive is even"] + Odd: [1, "Number of data to transfer for receive is odd"] + FRXTH: + Half: [0, "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] + Quarter: [1, "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] + TXEIE: + Masked: [0, "TXE interrupt masked"] + NotMasked: [1, "TXE interrupt not masked"] + RXNEIE: + Masked: [0, "RXE interrupt masked"] + NotMasked: [1, "RXE interrupt not masked"] + ERRIE: + Masked: [0, "Error interrupt masked"] + NotMasked: [1, "Error interrupt not masked"] + CLRTXFIFO: + NoEffect: [0, "No Effect"] + ClearTxFifo: [1, "Clear Tx Fifo"] + SSOE: + Disabled: [0, "SS output is disabled in master mode"] + Enabled: [1, "SS output is enabled in master mode"] + TXDMAEN: + Disabled: [0, "Tx buffer DMA disabled"] + Enabled: [1, "Tx buffer DMA enabled"] + RXDMAEN: + Disabled: [0, "Rx buffer DMA disabled"] + Enabled: [1, "Rx buffer DMA enabled"] + SR: + FTLVL: + _read: + Empty: [0, "Tx FIFO Empty"] + Quarter: [1, "Tx 1/4 FIFO"] + Half: [2, "Tx 1/2 FIFO"] + Full: [3, "Tx FIFO full"] + FRLVL: + _read: + Empty: [0, "Rx FIFO Empty"] + Quarter: [1, "Rx 1/4 FIFO"] + Half: [2, "Rx 1/2 FIFO"] + Full: [3, "Rx FIFO full"] + BSY: + _read: + NotBusy: [0, "SPI not busy"] + Busy: [1, "SPI busy"] + OVR: + _read: + NoOverrun: [0, "No overrun occurred"] + Overrun: [1, "Overrun occurred"] + MODF: + _read: + NoFault: [0, "No mode fault occurred"] + Fault: [1, "Mode fault occurred"] + TXE: + NotEmpty: [0, "Tx buffer not empty"] + Empty: [1, "Tx buffer empty"] + RXNE: + Empty: [0, "Rx buffer empty"] + NotEmpty: [1, "Rx buffer not empty"] + DR: + DR: [0, 0xFFFF] diff --git a/peripherals/syscfg/syscfg_f040.yaml b/peripherals/syscfg/syscfg_f040.yaml new file mode 100644 index 0000000..ad7f21e --- /dev/null +++ b/peripherals/syscfg/syscfg_f040.yaml @@ -0,0 +1,83 @@ +SYSCFG: + CFGR1: + MEM_MODE: + MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] + SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] + MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] + SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] + "TIM?_IC*": + Standard: [0, "From TIM?_CH* IO"] + Comp1: [1, "From Comp 1"] + Comp2: [2, "From Comp 2"] + Comp3: [3, "From Comp 3"] + "ETR_SRC_TIM?": + GPIO: [0, "TIM*_ETR is connected to GPIO"] + COMP1: [1, "TIM*_ETR is connected to COMP1"] + COMP2: [2, "TIM*_ETR is connected to COMP2"] + ADC: [3, "TIM*_ETR is connected to ADC"] + GPIO_AHB_SEL: + FastIO: [0, "Fast IO bus access to GPIO register control"] + AHB: [1, "AHB bus access to GPIO register control"] + CFGR2: + "COMP?_OCREF_CLR_TIM*": + NotUsed: [0, "COMP? output not used as TIM? ocref_clr input"] + Used: [1, "COMP? output used as TIM? ocref_clr input"] + "COMP?_BRK_TIM*": + Disconnected: [0, "COMP? output not connect to TIM? Break input"] + Connected: [1, "COMP? output connected to TIM? Break input"] + PVD_LOCK: + Disconnected: [0, "PVD LOCKUP output disconnected from TIM1/16/17 Break input"] + Connected: [1, "PVD LOCKUP output connected to TIM1/16/17 Break input"] + LOCKUP_LOCK: + Disconnected: [0, "Cortex-M0+ LOCKUP output disconnected from TIM1/16/17 Break input"] + Connected: [1, "Cortex-M0+ LOCKUP output connected to TIM1/16/17 Break input"] + "CFGR[34]": + "DMA?_MAP": + ADC: [0, "ADC DMA requests mapped on DMA?"] + SPI1_TX: [3, "SPI1_TX DMA requests mapped on DMA?"] + SPI1_RX: [4, "SPI1_RX DMA requests mapped on DMA?"] + SPI2_TX: [5, "SPI2_TX DMA requests mapped on DMA?"] + SPI2_RX: [6, "SPI2_RX DMA requests mapped on DMA?"] + USART1_TX: [7, "USART1_TX DMA requests mapped on DMA?"] + USART1_RX: [8, "USART1_RX DMA requests mapped on DMA?"] + USART2_TX: [9, "USART2_TX DMA requests mapped on DMA?"] + USART2_RX: [10, "USART2_RX DMA requests mapped on DMA?"] + USART3_TX: [11, "USART3_TX DMA requests mapped on DMA?"] + USART3_RX: [12, "USART3_RX DMA requests mapped on DMA?"] + USART4_TX: [13, "USART4_TX DMA requests mapped on DMA?"] + USART4_RX: [14, "USART4_RX DMA requests mapped on DMA?"] + I2C1_TX: [15, "I2C1_TX DMA requests mapped on DMA?"] + I2C1_RX: [16, "I2C1_RX DMA requests mapped on DMA?"] + I2C2_TX: [17, "I2C2_TX DMA requests mapped on DMA?"] + I2C2_RX: [18, "I2C2_RX DMA requests mapped on DMA?"] + TIM1_CH1: [19, "TIM1_CH1 DMA requests mapped on DMA?"] + TIM1_CH2: [20, "TIM1_CH2 DMA requests mapped on DMA?"] + TIM1_CH3: [21, "TIM1_CH3 DMA requests mapped on DMA?"] + TIM1_CH4: [22, "TIM1_CH4 DMA requests mapped on DMA?"] + TIM1_COM: [23, "TIM1_COM DMA requests mapped on DMA?"] + TIM1_TRIG: [24, "TIM1_TRIG DMA requests mapped on DMA?"] + TIM1_UP: [25, "TIM1_UP DMA requests mapped on DMA?"] + TIM2_CH1: [26, "TIM2_CH1 DMA requests mapped on DMA?"] + TIM2_CH2: [27, "TIM2_CH2 DMA requests mapped on DMA?"] + TIM2_CH3: [28, "TIM2_CH3 DMA requests mapped on DMA?"] + TIM2_CH4: [29, "TIM2_CH4 DMA requests mapped on DMA?"] + TIM2_UP: [30, "TIM2_UP DMA requests mapped on DMA?"] + TIM2_TRIG: [31, "TIM2_TRIG DMA requests mapped on DMA?"] + TIM3_CH1: [32, "TIM3_CH1 DMA requests mapped on DMA?"] + TIM3_CH2: [33, "TIM3_CH2 DMA requests mapped on DMA?"] + TIM3_CH3: [34, "TIM3_CH3 DMA requests mapped on DMA?"] + TIM3_CH4: [35, "TIM3_CH4 DMA requests mapped on DMA?"] + TIM3_UP: [36, "TIM3_UP DMA requests mapped on DMA?"] + TIM3_TRIG: [37, "TIM3_TRIG DMA requests mapped on DMA?"] + TIM6_UP: [38, "TIM6_UP DMA requests mapped on DMA?"] + TIM7_UP: [39, "TIM7_UP DMA requests mapped on DMA?"] + TIM15_CH1: [40, "TIM15_CH1 DMA requests mapped on DMA?"] + TIM15_CH2: [41, "TIM15_CH2 DMA requests mapped on DMA?"] + TIM15_UP: [42, "TIM15_UP DMA requests mapped on DMA?"] + TIM15_TRIG: [43, "TIM15_TRIG DMA requests mapped on DMA?"] + TIM15_COM: [44, "TIM15_COM DMA requests mapped on DMA?"] + TIM16_CH1: [45, "TIM16_CH1 DMA requests mapped on DMA?"] + TIM16_UP: [46, "TIM16_UP DMA requests mapped on DMA?"] + TIM17_CH1: [47, "TIM17_CH1 DMA requests mapped on DMA?"] + TIM17_UP: [48, "TIM17_UP DMA requests mapped on DMA?"] + LCD: [49, "LCD DMA requests mapped on DMA?"] diff --git a/peripherals/tim/tim_f0.yaml b/peripherals/tim/tim_f0.yaml index 0a76923..3c7fc7c 100644 --- a/peripherals/tim/tim_f0.yaml +++ b/peripherals/tim/tim_f0.yaml @@ -1,8 +1,4 @@ "TIM*": - "CCR?": - _modify: - "CCR?": - name: CCR CR1: ARPE: Disabled: [0, "TIMx_APRR register is not buffered"] diff --git a/peripherals/tim/tim_f040.yaml b/peripherals/tim/tim_f040.yaml new file mode 100644 index 0000000..be3e82a --- /dev/null +++ b/peripherals/tim/tim_f040.yaml @@ -0,0 +1,306 @@ +"TIM*": + ARR: + ARR: [0, 0xffff] + CNT: + CNT: [0, 0xffff] + CR1: + CKD: + NoMult: [0, "tDTS = tCK_INT"] + X2: [1, "tDTS = 2 x tCK_INT"] + X4: [2, "tDTS = 4 x tCK_INT"] + ARPE: + Disabled: [0, "TIMx_ARR register is not buffered"] + Enabled: [1, "TIMx_ARR register is buffered"] + CMS: + EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] + CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down"] + CenterAligned2: [2, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up"] + CenterAligned3: [3, "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down"] + OPM: + NotStopped: [0, "Counter not stopped at update event"] + Stopped: [1, "Counter stopped at update event"] + URS: + AnyEvent: [0, "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] + CounterOnly: [1, "Only counter overflow/underflow generates an update interrupt or DMA request"] + UDIS: + Enabled: [0, "Update event enabled"] + Disabled: [1, "Update event disabled"] + CEN: + Disabled: [0, "Counter disabled"] + Enabled: [1, "Counter enabled"] + DIER: + TDE: + Disabled: [0, "Trigger DMA request disabled"] + Enabled: [1, "Trigger DMA request enabled"] + "CC?DE": + Disabled: [0, "CCx DMA request disabled"] + Enabled: [1, "CCx DMA request enabled"] + UDE: + Disabled: [0, "Update DMA request disabled"] + Enabled: [1, "Update DMA request enabled"] + TIE: + Disabled: [0, "Trigger interrupt disabled"] + Enabled: [1, "Trigger interrupt enabled"] + "CC?IE": + Disabled: [0, "CCx interrupt disabled"] + Enabled: [1, "CCx interrupt enabled"] + UIE: + Disabled: [0, "Update interrupt disabled"] + Enabled: [1, "Update interrupt enabled"] + EGR: + "CC?G": + _write: + Trigger: [1, "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register"] + UG: + _write: + Trigger: [1, "Re-initializes the timer counter and generates an update of the registers"] + TG: + _write: + Trigger: [1, "Trigger interrupt generated"] + PSC: + PSC: [0, 0xffff] + SR: + "CC?OF": + _read: + Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxOF flag was already set"] + _W0C: + Clear: [0, "Clear flag"] + TIF: + _read: + Triggered: [1, "Valid edge detected at the TRGI input"] + _W0C: + Clear: [0, "Clear flag"] + "CC?IF": + _read: + Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set"] + _W0C: + Clear: [0, "Clear flag"] + UIF: + _read: + Update: [1, "Update event waiting for response"] + _W0C: + Clear: [0, "Clear flag"] + +TIM1: + CR2: + "OIS?": + Off: [0, ""] + On: [1, "Output Idle state ? (OC? output)"] + "OIS?N": + Off: [0, ""] + On: [1, "Output Idle state ? (OC?N output)"] + CCUS: + Bit: [0, "When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only"] + BitOrEdge: [1, "When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI"] + CCPC: + NoPreload: [0, "CCxE, CCxNE, OCxM are not updated with event"] + Preload: [1, "CCxE, CCxNE, OCxM are updated with event"] + SMCR: + OCCS: + Ocref_Clr: [0, "OCREF_CLR_INT connected to the OCREF_CLR input"] + Etrf: [1, "OCREF_CLR_INT connected to ETRF"] + +"TIM[123]": + CR1: + DIR: + Up: [0, "Counter used as upcounter"] + Down: [1, "Counter used as downcounter"] + CCMR2_OUTPUT: + OC?CE: + Disabled: [0, "Output compare ? clear disabled"] + Enabled: [1, "Output compare ? clear enabled"] + OC?M: [0, 6] + OC?PE: + Disabled: [0, "Preload register on CCRx disabled. New values written to CCRx are taken into account immediately"] + Enabled: [1, "Preload register on CCRx enabled. Preload value is loaded into active register on each update event"] + CC?S: + Output: [0, "CCx channel is configured as output"] + OC3FE: + Disabled: [0, "Output compare 3 fast disabled"] + Enabled: [1, "Output compare 3 fast enabled"] + CCMR2_INPUT: + IC?F: [0, 15] + IC?PSC: [0, 3] + CC4S: + Output: [0, "CC4 channel is configured as output"] + TI4: [1, "CC4 channel is configured as input, IC4 is mapped on TI4"] + TI3: [2, "CC4 channel is configured as input, IC4 is mapped on TI3"] + TRC: [3, "CC4 channel is configured as input, IC4 is mapped on TRC"] + CC3S: + Output: [0, "CC3 channel is configured as output"] + TI3: [1, "CC3 channel is configured as input, IC3 is mapped on TI3"] + TI4: [2, "CC3 channel is configured as input, IC3 is mapped on TI4"] + TRC: [3, "CC3 channel is configured as input, IC3 is mapped on TRC"] + CCR3: + CCR3: [0, 0xffff] + CCR4: + CCR4: [0, 0xffff] + +"TIM[123], TIM15": + CCR2: + CCR2: [0, 0xffff] + SMCR: + ETP: + NotInverted: [0, "ETR is noninverted, active at high level or rising edge"] + Inverted: [1, "ETR is inverted, active at low level or falling edge"] + ECE: + Disabled: [0, "External clock mode 2 disabled"] + Enabled: [1, "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] + ETPS: + Div1: [0, "Prescaler OFF"] + Div2: [1, "ETRP frequency divided by 2"] + Div4: [2, "ETRP frequency divided by 4"] + Div8: [3, "ETRP frequency divided by 8"] + ETF: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + MSM: + NoSync: [0, "No action"] + Sync: [1, "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO)"] + TS: + ITR0: [0, "Internal Trigger 0 (ITR0)"] + ITR2: [2, "Internal Trigger 2 (ITR2)"] + TI1F_ED: [4, "TI1 Edge Detector (TI1F_ED)"] + TI1FP1: [5, "Filtered Timer Input 1 (TI1FP1)"] + TI2FP2: [6, "Filtered Timer Input 2 (TI2FP2)"] + ETRF: [7, "External Trigger input (ETRF)"] + SMS: + Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + Encoder_Mode_1: [1, "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + Encoder_Mode_2: [2, "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + Encoder_Mode_3: [3, "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + Reset_Mode: [4, "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + Gated_Mode: [5, "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + Trigger_Mode: [6, "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + Ext_Clock_Mode: [7, "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + +"TIM1, TIM1[567]": + BDTR: + MOE: + Disabled: [0, "OC and OCN outputs are disabled or forced to idle state"] + Enabled: [1, "OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)"] + AOE: + Disabled: [0, "MOE can be set only by software"] + Enabled: [1, "MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)"] + BKP: + Low: [0, "Brake input active low"] + High: [1, "Brake intput active high"] + BKE: + Disabled: [0, "brake input (BRK and BRK_ACTH) is disabled"] + Enabled: [1, "Brake input (BRK and BRK_ACTH) is enabled"] + OSSR: + Disabled: [0, "When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal = 0)"] + Enabled: [1, "When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE = 1 or CCxNE = 1. Then, OC/OCN enable output signal = 1"] + OSSI: + Disabled: [0, "When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal = 0)"] + Enabled: [1, "When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE = 1 or CCxNE = 1. OC/OCN enable output signal = 1)"] + LOCK: + Off: [0, "LOCK OFF - No bit is write protected"] + Lvl1: [1, " LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written"] + Lvl2: [2, "LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written"] + Lvl3: [3, "LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written"] + DTG: [0, 0xff] + RCR: + REP: [0, 0xff] + +"TIM[123], TIM1[567]": + DCR: + DBL: [0, 18] + DBA: [0, 31] + DMAR: + DMAB: [0, 0xffff] + +"TIM[123], TIM1[4567]": + CCER: + CC?P: + Disabled: [0, "OC? active high"] + Enabled: [1, "OC? active low"] + CC?E: + Disabled: [0, "Capture Disable"] + Enabled: [1, "Capture Enable"] + CCMR1_INPUT: + IC?F: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + IC?PSC: + NoDiv: [0, "no prescaler, capture is done each time an edge is detected on the capture input"] + Div2: [1, "capture is done once every 2 events"] + Div4: [2, "capture is done once every 4 events"] + Div8: [3, "capture is done once every 8 events"] + CC?S: + TI1: [1, "CC? channel is configured as input, IC1 is mapped on TI1"] + TI2: [2, "CC? channel is configured as input, IC1 is mapped on TI2"] + TRC: [3, "CC? channel is configured as input, IC1 is mapped on TRC"] + CCMR1_OUTPUT: + OC1PE: + Disabled: [0, "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] + Enabled: [1, "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] + CC1S: + Output: [0, "CC1 channel is configured as output"] + CCR1: + CCR1: [0, 0xffff] + +"TIM[12367], TIM1[567]": + CR2: + TI1S: + Single: [0, "TIMx_CH1 pin is connected to TI1 input"] + Xor: [1, "TIMx_CH1, CH2, CH3 pins are connected to TI1 input (XOR combination)"] + MMS: + Reset: [0, "The UG bit from the TIMx_EGR register is used as trigger output"] + Enable: [1, "The counter enable signal, CNT_EN, is used as trigger output"] + Update: [2, "The update event is selected as trigger output"] + ComparePulse: [3, "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + CompareOC1: [4, "OC1REF signal is used as trigger output"] + CompareOC2: [5, "OC2REF signal is used as trigger output"] + CompareOC3: [6, "OC3REF signal is used as trigger output"] + CompareOC4: [7, "OC4REF signal is used as trigger output"] + CCDS: + OnCompare: [0, "CCx DMA request sent when CCx event occurs"] + OnUpdate: [1, "CCx DMA request sent when update event occurs"] + SR: + IC?IF: + NoCapture: [0, "no repeat captures are generated"] + Capture: [1, "falling edge capture event occurs"] + IC?IR: + NoCapture: [0, "no repeat captures are generated"] + Capture: [1, "Rising edge capture event occurs"] + BIF: + _read: + NoBrake: [0, "no brake event is generated"] + Brake: [1, "Valid level detected on the brake input"] + _W0C: + Clear: [0, "Clear flag"] + COMIF: + _read: + NoEvt: [0, "no COM event is generated"] + Event: [1, "COM interrupt waiting for response"] + _W0C: + Clear: [0, "Clear flag"] diff --git a/py32_part_table.yaml b/py32_part_table.yaml index 775e5fb..ed44632 100644 --- a/py32_part_table.yaml +++ b/py32_part_table.yaml @@ -39,3 +39,10 @@ py32f0: rm_url: https://www.puyasemi.com/download_path/%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C/MCU%20%E5%BE%AE%E5%A4%84%E7%90%86%E5%99%A8/PY32F030%20Reference%20manual%20v1.3_EN.pdf members: - PY32F030 + py32f040: + url: https://www.puyasemi.com/en/py32f040.html?tag=48#common + rm: PY32F040 Reference manual + rm_title: PY32F040 Reference manual + rm_url: https://www.puyasemi.com/download_path/%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C/MCU/PY32F040_Reference_Manual_V0.2.pdf + members: + - PY32F040 diff --git a/scripts/README.md b/scripts/README.md new file mode 100644 index 0000000..5cc6708 --- /dev/null +++ b/scripts/README.md @@ -0,0 +1,102 @@ +# Scripts for py32-rs +These scripts are used during development of the py32f0 crates + +## comparesvd.py +Compares 2 svd's by peripheral memory address. +``` +usage: comparesvd.py svdfile1 svdfile2 +``` + +## group.py [NOT WORKING] +Generate sets of devices with peripherals in common +``` +usage: group.py [-h] devices output +``` + +## htmlcomparesvdall.sh +Runs `htmlcomparesvd.py` on all patched svd files in svd directory. Generates a `html/comparisons.html` file. +``` +usage: htmlcomparesvdall.sh +``` + +## htmlcomparesvd.py +Creates html pages that compare peripherals, registers, and fields given a set of svd's. +``` +usage: htmlcomparesvd.py [-h] htmldir [svdfiles ...] +``` + +## interrupts.py +Outputs peripheral vector number, interrupt name, and description from a svd +``` +usage: interrupts.py [-h] outdir [svdfiles ...] +``` + +## makecrates.py +Script that builds the rust crates. +``` +usage: makecrates.py [-h] [-y] [--families FAMILY [FAMILY ...]] devices +``` + +## makehtml.py +Generates a webpage for a given SVD file containing details on every +peripheral and register and their level of coverage. +``` +usage: makehtml.py [-h] htmldir [svdfiles ...] +``` + +## makejson.py [NOT WORKING] +Transforms the given SVD files into a JSON format more suited for +web pages. +``` +usage: makejson.py [-h] htmldir [svdfiles ...] +``` + +## matchperipherals.py [NOT WORKING] + +## periphtemplate.py +Prints out a basic yaml template of a peripheral in svdfile. +``` +usage: periphtemplate.py [-h] svdfile peripheral yamlfile +``` + +## svdmmap.py +Outputs a peripheral memory map of the device in a svd file +usage: +``` +python3 svdmmap.py +``` +Example output (partial) +``` +0x40000000 A PERIPHERAL TIM2 +0x40000000 B REGISTER CR1: desc CR1 +0x40000000 C FIELD 00w01 CEN: desc CEN +0x40000000 C FIELD 01w01 UDIS: desc UDIS +0x40000000 C FIELD 02w01 URS: desc URS +0x40000000 C FIELD 03w01 OPM: desc OPM +0x40000000 C FIELD 04w01 DIR: desc DIR +0x40000000 C FIELD 05w02 CMS: desc CMS +0x40000000 C FIELD 07w01 ARPE: desc ARPE +0x40000000 C FIELD 08w02 CKD: desc CKD +0x40000004 B REGISTER CR2: desc CR2 +0x40000004 C FIELD 03w01 CCDS: desc CCDS +0x40000004 C FIELD 04w03 MMS: desc MMS +0x40000004 C FIELD 07w01 TI1S: desc TI1S +... +``` + +## timer_hierarchy.py +Prints the timer peripherals common registers and fields for the device in a svd file +``` +usage: timer_hierarchy.py [-h] svdfile +``` + +## tool_install.sh +Installs the tools required to generate the rust crates for this device family. The script will download and install +the specific version of the tools needed. + +## HTML Templates +Used in `makehtml.py` and `makejson.py` + + - makehtml.index.template.html + - makehtml.template.html + - viewgroups.html diff --git a/scripts/htmlcomparesvd.py b/scripts/htmlcomparesvd.py index 2a2d858..36fd82f 100644 --- a/scripts/htmlcomparesvd.py +++ b/scripts/htmlcomparesvd.py @@ -1,7 +1,7 @@ import argparse import os.path import xml.etree.ElementTree as ET - +import re def iter_peripherals(tree): for ptag in tree.iter('peripheral'): @@ -18,7 +18,29 @@ def iter_fields(rtag): yield ftag +def get_field_offset_width(ftag): + # Some svd files will specify a bitRange rather than + # bitOffset and bitWidth + if ftag.find('bitRange') != None: + frange = ftag.find('bitRange').text + parts = frange[1:-1].split(':') + end = int(parts[0], 0) + start = int(parts[1], 0) + foffset = start + fwidth = end - start + 1 + else: + # some svd files will specify msb,lsb rather + # then bitOffset and bitWidth + if ftag.find('msb') != None: + foffset = int(ftag.find('lsb').text, 0) + fwidth = int(ftag.find('msb').text, 0) - foffset + 1 + else: + foffset = int(ftag.find('bitOffset').text, 0) + fwidth = int(ftag.find('bitWidth').text, 0) + return (foffset, fwidth) + def parse(svdfile): + print('svdfile:',svdfile) tree = ET.parse(svdfile) peripherals = {} for ptag in iter_peripherals(tree): @@ -34,10 +56,10 @@ def parse(svdfile): for ftag in iter_fields(rtag): fname = ftag.find('name').text print("\t\tfield: %s" % fname) - foffset = int(ftag.find('bitOffset').text, 0) - fwidth = int(ftag.find('bitWidth').text, 0) - fields[fname] = {"name": fname, "offset": foffset, - "width": fwidth} + foffset, fwidth = get_field_offset_width(ftag) + + fields[fname] = {"name": fname, "offset": foffset, "width": fwidth} + registers[rname] = {"name": rname, "offset": roffset, "fields": fields} peripherals[pname] = {"name": pname, "base": pbase, diff --git a/scripts/htmlcomparesvdall.sh b/scripts/htmlcomparesvdall.sh index 95ee472..ad03c83 100755 --- a/scripts/htmlcomparesvdall.sh +++ b/scripts/htmlcomparesvdall.sh @@ -31,7 +31,7 @@ cat > html/comparisons.html <Device families diff --git a/scripts/makecrates.py b/scripts/makecrates.py index 4bc5785..ee2ef94 100644 --- a/scripts/makecrates.py +++ b/scripts/makecrates.py @@ -16,11 +16,11 @@ import re import yaml -VERSION = "0.2.0" +VERSION = "0.2.1" SVD2RUST_VERSION = "0.28.0" CRATE_DOC_FEATURES = { - "py32f0": ["critical-section", "rt", "py32f002a", "py32f002b", "py32f003", "py32f030"] + "py32f0": ["critical-section", "rt", "py32f002a", "py32f002b", "py32f003", "py32f030", "py32f040"] } CRATE_DOC_TARGETS = { @@ -32,7 +32,7 @@ edition = "2021" name = "{crate}" version = "{version}" -authors = ["creatoy ", "py32-rs Contributors"] +authors = ["creatoy ", "Greg Green ", "py32-rs Contributors"] description = "Device support crates for {family} devices" repository = "https://github.com/py32-rust/py32-rs" readme = "README.md" diff --git a/scripts/makehtml.py b/scripts/makehtml.py index 4cc5d71..e582b7b 100644 --- a/scripts/makehtml.py +++ b/scripts/makehtml.py @@ -21,6 +21,27 @@ env = Environment(loader=PackageLoader('makehtml', '')) +def get_field_offset_width(ftag): + # Some svd files will specify a bitRange rather than + # bitOffset and bitWidth + frange = get_string(ftag, 'bitRange') + if frange: + parts = frange[1:-1].split(':') + end = int(parts[0], 0) + start = int(parts[1], 0) + foffset = start + fwidth = end - start + 1 + else: + # some svd files will specify msb,lsb rather + # then bitOffset and bitWidth + msb = get_string(ftag, 'msb') + if msb: + foffset = get_int(ftag, 'lsb') + fwidth = get_int(ftag, 'msb') - foffset + 1 + else: + foffset = get_int(ftag, 'bitOffset') + fwidth = get_int(ftag, 'bitWidth') + return (foffset, fwidth) def generate_index_page(devices): print("Generating Index") @@ -166,18 +187,7 @@ def parse_register(rtag): register_fields_total += 1 fname = get_string(ftag, 'name') fdesc = get_string(ftag, 'description') - # Some svd files will specify a bitRange rather than - # bitOffset and bitWidth - frange = get_string(ftag, 'bitRange') - if frange: - parts = frange[1:-1].split(':') - end = int(parts[0], 0) - start = int(parts[1], 0) - foffset = start - fwidth = end - start + 1 - else: - foffset = get_int(ftag, 'bitOffset') - fwidth = get_int(ftag, 'bitWidth') + foffset, fwidth = get_field_offset_width(ftag) faccs = get_string(ftag, 'access') or raccs enum = ftag.find('enumeratedValues') wc = ftag.find('writeConstraint') diff --git a/scripts/makejson.py b/scripts/makejson.py index 477fb7f..585599b 100644 --- a/scripts/makejson.py +++ b/scripts/makejson.py @@ -20,6 +20,26 @@ def generate_device_page(device): template = env.get_template('makehtml.template.html') return template.render(device=device) +def get_field_offset_width(ftag): + # Some svd files will specify a bitRange rather than + # bitOffset and bitWidth + if ftag.find('bitRange') != None: + frange = ftag.find('bitRange').text + parts = frange[1:-1].split(':') + end = int(parts[0], 0) + start = int(parts[1], 0) + foffset = start + fwidth = end - start + 1 + else: + # some svd files will specify msb,lsb rather + # then bitOffset and bitWidth + if ftag.find('msb') != None: + foffset = int(ftag.find('lsb').text, 0) + fwidth = int(ftag.find('msb').text, 0) - foffset + 1 + else: + foffset = int(ftag.find('bitOffset').text, 0) + fwidth = int(ftag.find('bitWidth').text, 0) + return (foffset, fwidth) def parse_device(svdfile): tree = ET.parse(svdfile) @@ -55,8 +75,7 @@ def parse_device(svdfile): register_fields_total += 1 fname = ftag.find('name').text fdesc = ftag.find('description').text - foffset = int(ftag.find('bitOffset').text, 0) - fwidth = int(ftag.find('bitWidth').text, 0) + foffset, fwidth = get_field_offset_width(ftag) enum = ftag.find('enumeratedValues') if enum is not None: register_fields_documented += 1 diff --git a/scripts/periphtemplate.py b/scripts/periphtemplate.py index debea42..a9a397a 100644 --- a/scripts/periphtemplate.py +++ b/scripts/periphtemplate.py @@ -9,7 +9,28 @@ import argparse import xml.etree.ElementTree as ET +import re +def get_field_offset_width(ftag): + # Some svd files will specify a bitRange rather than + # bitOffset and bitWidth + if ftag.find('bitRange') != None: + frange = ftag.find('bitRange').text + parts = frange[1:-1].split(':') + end = int(parts[0], 0) + start = int(parts[1], 0) + foffset = start + fwidth = end - start + 1 + else: + # some svd files will specify msb,lsb rather + # then bitOffset and bitWidth + if ftag.find('msb') != None: + foffset = int(ftag.find('lsb').text, 0) + fwidth = int(ftag.find('msb').text, 0) - foffset + 1 + else: + foffset = int(ftag.find('bitOffset').text, 0) + fwidth = int(ftag.find('bitWidth').text, 0) + return (foffset, fwidth) def parse_periph(svdfile, pname): tree = ET.parse(svdfile) @@ -32,9 +53,8 @@ def parse_periph(svdfile, pname): roffset = int(rtag.find('addressOffset').text, 0) for ftag in rtag.iter('field'): fname = ftag.find('name').text - foffset = int(ftag.find('bitOffset').text, 0) - fwidth = int(ftag.find('bitWidth').text, 0) - fields[foffset] = {"name": fname, "width": fwidth} + foffset, fwidth = get_field_offset_width(ftag) + fields[foffset] = {"name": fname, "offset": foffset, "width": fwidth} registers[roffset] = {"name": rname, "fields": fields} return registers diff --git a/scripts/svdmmap.py b/scripts/svdmmap.py index e273d0a..76c18cc 100644 --- a/scripts/svdmmap.py +++ b/scripts/svdmmap.py @@ -8,7 +8,7 @@ import sys import copy import xml.etree.ElementTree as ET - +import re def iter_clusters(ptag): registers = ptag.find('registers') @@ -134,6 +134,28 @@ def expand_cluster(node): return nodes +def get_field_offset_width(ftag): + # Some svd files will specify a bitRange rather than + # bitOffset and bitWidth + frange = get_string(ftag, 'bitRange') + if frange: + parts = frange[1:-1].split(':') + end = int(parts[0], 0) + start = int(parts[1], 0) + foffset = start + fwidth = end - start + 1 + else: + # some svd files will specify msb,lsb rather + # then bitOffset and bitWidth + msb = get_string(ftag, 'msb') + if msb: + foffset = get_int(ftag, 'lsb') + fwidth = get_int(ftag, 'msb') - foffset + 1 + else: + foffset = get_int(ftag, 'bitOffset') + fwidth = get_int(ftag, 'bitWidth') + return (foffset, fwidth) + def parse_register(rtag): """ Extract register and field information from a register node into a dict. @@ -145,8 +167,7 @@ def parse_register(rtag): roffset = get_int(rtag, 'addressOffset') for ftag in iter_fields(rtag): fname = get_string(ftag, 'name') - foffset = get_int(ftag, 'bitOffset') - fwidth = get_int(ftag, 'bitWidth') + foffset, fwidth = get_field_offset_width(ftag) fdesc = get_string(ftag, 'description') faccess = get_access(ftag) fields[fname] = {"name": fname, "offset": foffset, diff --git a/scripts/timer_hierarchy.py b/scripts/timer_hierarchy.py index f179c91..cb7448f 100644 --- a/scripts/timer_hierarchy.py +++ b/scripts/timer_hierarchy.py @@ -1,20 +1,37 @@ import argparse import xml.etree.ElementTree as ET import pprint +import re from collections import defaultdict from svdtools import patch +def iter_peripherals(tree, pspec): + for ptag in tree.iter('peripheral'): + if re.match(pspec, ptag.find('name').text): + yield ptag + + +def iter_registers(ptag): + for rtag in ptag.iter('register'): + yield rtag + + +def iter_fields(rtag): + for ftag in rtag.iter('field'): + yield ftag + + def main(svdfile): tree = ET.parse(svdfile) field_tims = defaultdict(set) - for ptag in patch.iter_peripherals(tree, "TIM*"): + for ptag in iter_peripherals(tree, "TIM*"): pname = ptag.find('name').text - for rtag in patch.iter_registers(ptag, "*"): + for rtag in iter_registers(ptag): rname = rtag.find('name').text - for ftag in patch.iter_fields(rtag, "*"): + for ftag in iter_fields(rtag): fname = ftag.find('name').text rfname = "{}.{}".format(rname, fname) field_tims[rfname].add(pname) diff --git a/svd/extract.sh b/svd/extract.sh index ff37e82..a3755e2 100755 --- a/svd/extract.sh +++ b/svd/extract.sh @@ -5,3 +5,4 @@ cp vendor/PY32F002Axx.svd py32f002a.svd cp vendor/PY32F002Bxx.svd py32f002b.svd cp vendor/PY32F003xx.svd py32f003.svd cp vendor/PY32F030xx.svd py32f030.svd +cp vendor/py32f040xx.svd py32f040.svd diff --git a/svd/vendor/py32f040xx.svd b/svd/vendor/py32f040xx.svd new file mode 100644 index 0000000..b0eb462 --- /dev/null +++ b/svd/vendor/py32f040xx.svd @@ -0,0 +1,12539 @@ + + + Puya + Puya + PY32F040xx + PY32F0 + 1.0.0 + Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. + + CM0+ + r0p1 + little + false + false + 4 + false + + 8 + 32 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + ADC + Analog to Digital Converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + SR + desc SR + 0x0 + + + AWD + desc AWD + [0:0] + + + EOC + desc EOC + [1:1] + + + JEOC + desc JEOC + [2:2] + + + JSTRT + desc JSTRT + [3:3] + + + STRT + desc STRT + [4:4] + + + OVER + desc OVER + [5:5] + read-only + + + + + CR1 + desc CR1 + 0x4 + + + AWDCH + desc AWDCH + [4:0] + + + EOCIE + desc EOCIE + [5:5] + + + AWDIE + desc AWDIE + [6:6] + + + JEOCIE + desc JEOCIE + [7:7] + + + SCAN + desc SCAN + [8:8] + + + AWDSGL + desc AWDSGL + [9:9] + + + JAUTO + desc JAUTO + [10:10] + + + DISCEN + desc DISCEN + [11:11] + + + JDISCEN + desc JDISCEN + [12:12] + + + DISCNUM + desc DISCNUM + [15:13] + + + JAWDEN + desc JAWDEN + [22:22] + + + AWDEN + desc AWDEN + [23:23] + + + RESSEL + desc RESSEL + [25:24] + + + ADSTP + desc ADSTP + [27:27] + + + OVETIE + desc OVETIE + [29:29] + + + + + CR2 + desc CR2 + 0x8 + + + ADON + desc ADON + [0:0] + + + CONT + desc CONT + [1:1] + + + CAL + desc CAL + [2:2] + + + RSTCAL + desc RSTCAL + [3:3] + + + DMA + desc DMA + [8:8] + + + ALIGN + desc ALIGN + [11:11] + + + JEXTSEL + desc JEXTSEL + [14:12] + + + JEXTTRIG + desc JEXTTRIG + [15:15] + + + EXTSEL + desc EXTSEL + [19:17] + + + EXTTRIG + desc EXTTRIG + [20:20] + + + JSWSTART + desc JSWSTART + [21:21] + + + SWSTART + desc SWSTART + [22:22] + + + TSVREFE + desc TSVREFE + [23:23] + + + VERFBUFFERE + desc VERFBUFFERE + [25:25] + + + VERFBUFFERSEL + desc VERFBUFFERSEL + [27:26] + + + + + SMPR1 + desc SMPR1 + 0xC + + + SMP20 + desc SMP20 + [2:0] + + + SMP21 + desc SMP21 + [5:3] + + + SMP22 + desc SMP22 + [8:6] + + + SMP23 + desc SMP23 + [11:9] + + + + + SMPR2 + desc SMPR2 + 0x10 + + + SMP10 + desc SMP10 + [2:0] + + + SMP11 + desc SMP11 + [5:3] + + + SMP12 + desc SMP12 + [8:6] + + + SMP13 + desc SMP13 + [11:9] + + + SMP14 + desc SMP14 + [14:12] + + + SMP15 + desc SMP15 + [17:15] + + + SMP16 + desc SMP16 + [20:18] + + + SMP17 + desc SMP17 + [23:21] + + + SMP18 + desc SMP18 + [26:24] + + + SMP19 + desc SMP19 + [29:27] + + + + + SMPR3 + desc SMPR2 + 0x14 + + + SMP0 + desc SMP0 + [2:0] + + + SMP1 + desc SMP1 + [5:3] + + + SMP2 + desc SMP2 + [8:6] + + + SMP3 + desc SMP3 + [11:9] + + + SMP4 + desc SMP4 + [14:12] + + + SMP5 + desc SMP5 + [17:15] + + + SMP6 + desc SMP6 + [20:18] + + + SMP7 + desc SMP7 + [23:21] + + + SMP8 + desc SMP8 + [26:24] + + + SMP9 + desc SMP9 + [29:27] + + + + + JOFR1 + desc JOFR1 + 0x18 + + + JOFFSET1 + desc JOFFSET1 + [11:0] + + + + + JOFR2 + desc JOFR2 + 0x1C + + + JOFFSET2 + desc JOFFSET2 + [11:0] + + + + + JOFR3 + desc JOFR3 + 0x20 + + + JOFFSET3 + desc JOFFSET3 + [11:0] + + + + + JOFR4 + desc JOFR4 + 0x24 + + + JOFFSET4 + desc JOFFSET4 + [11:0] + + + + + HTR + desc HTR + 0x28 + + + HT + desc HT + [11:0] + + + + + LTR + desc LTR + 0x2C + + + LT + desc LT + [11:0] + + + + + SQR1 + desc SQR1 + 0x30 + + + SQ13 + desc SQ13 + [4:0] + + + SQ14 + desc SQ14 + [9:5] + + + SQ15 + desc SQ15 + [14:10] + + + SQ16 + desc SQ16 + [19:15] + + + L + desc L + [23:20] + + + + + SQR2 + desc SQR2 + 0x34 + + + SQ7 + desc SQ7 + [4:0] + + + SQ8 + desc SQ8 + [9:5] + + + SQ9 + desc SQ9 + [14:10] + + + SQ10 + desc SQ10 + [19:15] + + + SQ11 + desc SQ11 + [24:20] + + + SQ12 + desc SQ12 + [29:25] + + + + + SQR3 + desc SQR3 + 0x38 + + + SQ1 + desc SQ1 + [4:0] + + + SQ2 + desc SQ2 + [9:5] + + + SQ3 + desc SQ3 + [14:10] + + + SQ4 + desc SQ4 + [19:15] + + + SQ5 + desc SQ5 + [24:20] + + + SQ6 + desc SQ6 + [29:25] + + + + + JSQR + desc JSQR + 0x3C + + + JSQ1 + desc JSQ1 + [4:0] + + + JSQ2 + desc JSQ2 + [9:5] + + + JSQ3 + desc JSQ3 + [14:10] + + + JSQ4 + desc JSQ4 + [19:15] + + + JL + desc JL + [23:20] + + + + + JDR1 + desc JDR1 + 0x40 + read-only + + + JDR1 + desc JDR1 + [15:0] + read-only + + + + + JDR2 + desc JDR2 + 0x44 + read-only + + + JDR2 + desc JDR2 + [15:0] + read-only + + + + + JDR3 + desc JDR3 + 0x48 + read-only + + + JDR3 + desc JDR3 + [15:0] + read-only + + + + + JDR4 + desc JDR4 + 0x4C + read-only + + + JDR4 + desc JDR4 + [15:0] + read-only + + + + + DR + desc DR + 0x50 + read-only + + + DATA + desc DATA + [15:0] + read-only + + + + + CCSR + desc CCSR + 0x54 + + + CALSEL + desc CALSEL + [11:11] + + + CALSMP + desc CALSMP + [13:12] + + + CALBYP + desc CALBYP + [14:14] + + + CALSET + desc CALSET + [15:15] + + + OFFSUC + desc OFFSUC + [29:29] + + + CALFAIL + desc CALFAIL + [30:30] + + + CALON + desc CALON + [31:31] + read-only + + + + + + + COMP1 + Comparator 1 + COMP + 0x40010200 + + 0x0 + 0x10 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + CSR + CSR + COMP control and status register + 0x0 + + + EN + COMP enable bit + [0:0] + + + INMSEL + Comparator signal selector for inverting input INM + [5:2] + + + INPSEL + Comparator signal selector for non-inverting input + [9:6] + + + WINMODE + Comparator non-inverting input selector for window mode + [11:11] + + + POLARITY + Comparator polarity selector + [15:15] + + + HYST + Comparator hysteresis enable selector + [16:16] + + + PWRMODE + Comparator power mode selector + [19:18] + + + VCDIV + VCDIV + [25:20] + + + VCDIV_EN + VCDIV_EN + [26:26] + + + VCSEL + VCSEL + [27:27] + + + COMP_OUT + Comparator output status + [30:30] + + + + + FR + FR + Comparator Filter register + 0x4 + + + FLTEN1 + Filter enable bit + [0:0] + + + FLTCNT1 + Comparator filter and counter + [31:16] + + + + + + + COMP2 + Comparator2 + COMP + 0x40010210 + + 0x0 + 0x10 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + CSR + CSR + COMP control and status register + 0x0 + + + EN + COMP enable bit + [0:0] + + + HYST + Comparator hysteresis enable selector + [1:1] + + + INMSEL + Comparator signal selector for inverting input INM + [5:2] + + + INPSEL + Comparator signal selector for non-inverting input + [9:6] + + + WINMODE + Comparator non-inverting input selector for window mode + [11:11] + + + POLARITY + Comparator polarity selector + [15:15] + + + PWRMODE + Comparator power mode selector + [19:18] + + + COMP_OUT + Comparator output status + [30:30] + + + + + FR + FR + Comparator Filter register + 0x4 + + + FLTEN2 + Filter enable bit + [0:0] + + + FLTCNT2 + Comparator filter and counter + [31:16] + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0xFFFFFFFF + + + DR + Data Register + [31:0] + + + + + IDR + IDR + Independent Data register + 0x4 + + + IDR + Independent Data register + [7:0] + + + + + CR + CR + Control register + 0x8 + write-only + + + RESET + Reset bit + [0:0] + + + + + + + CTC + desc CTC + CTC + 0x40006C00 + + 0x0 + 0x400 + registers + + + RCC_CTC + RCC and CTC global Interrupts + 4 + + + + CTL0 + desc CTL0 + 0x0 + 0x4000 + + + CKOKIE + desc CKOKIE + [0:0] + + + CKWARNIE + desc CKWARNIE + [1:1] + + + ERRIE + desc ERRIE + [2:2] + + + EREFIE + desc EREFIE + [3:3] + + + CNTEN + desc CNTEN + [5:5] + + + AUTOTRIM + desc AUTOTRIM + [6:6] + + + SWREFPUL + desc SWREFPUL + [7:7] + write-only + + + TRIMVALUE + desc TRIMVALUE + [14:8] + + + + + CTL1 + desc CTL1 + 0x4 + 0x2022BB7F + + + RLVALUE + desc RLVALUE + [15:0] + + + CKLIM + desc CKLIM + [23:16] + + + REFPSC + desc REFPSC + [26:24] + + + REFSEL + desc REFSEL + [29:28] + + + REFPOL + desc REFPOL + [31:31] + + + + + SR + desc SR + 0x8 + read-only + + + CKOKIF + desc CKOKIF + [0:0] + read-only + + + CKWARNIF + desc CKWARNIF + [1:1] + read-only + + + ERRIF + desc ERRIF + [2:2] + read-only + + + EREFIF + desc EREFIF + [3:3] + read-only + + + CKERR + desc CKERR + [8:8] + read-only + + + REFMISS + desc REFMISS + [9:9] + read-only + + + TRIMERR + desc TRIMERR + [10:10] + read-only + + + REFDIR + desc REFDIR + [15:15] + read-only + + + REFCAP + desc REFCAP + [31:16] + read-only + + + + + INTC + desc INTC + 0xC + write-only + + + CKOKIC + desc CKOKIC + [0:0] + write-only + + + CKWARNIC + desc CKWARNIC + [1:1] + write-only + + + ERRIC + desc ERRIC + [2:2] + write-only + + + EREFIC + desc EREFIC + [3:3] + write-only + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + read-only + + + REV_ID + REV_ID + [30:0] + + + + + CR + CR + Debug MCU Configuration Register + 0x4 + + + DBG_SLEEP + Debug Sleep Mode + [0:0] + + + DBG_STOP + Debug Stop Mode + [1:1] + + + + + APB_FZ1 + APB_FZ1 + APB Freeze Register1 + 0x8 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is halted + [0:0] + + + DBG_TIMER3_STOP + Debug Timer 3 stopped when Core is halted + [1:1] + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is halted + [4:4] + + + DBG_TIMER7_STOP + Debug Timer 7 stopped when Core is halted + [5:5] + + + DBG_RTC_STOP + Debug RTC stopped when Core is halted + [10:10] + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core is halted + [11:11] + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when Core is halted + [12:12] + + + DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT + [21:21] + + + DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT + [22:22] + read-only + + + DBG_LPTIM_STOP + Debug LPTIM stopped when Core is halted + [31:31] + + + + + APB_FZ2 + APB_FZ2 + APB Freeze Register2 + 0xC + + + DBG_TIMER1_STOP + Debug Timer 1 stopped when Core is halted + [11:11] + + + DBG_TIMER14_STOP + Debug Timer 14 stopped when Core is halted + [15:15] + + + DBG_TIMER15_STOP + Debug Timer 15 stopped when Core is halted + [16:16] + + + DBG_TIMER16_STOP + Debug Timer 16 stopped when Core is halted + [17:17] + + + DBG_TIMER17_STOP + Debug Timer 17 stopped when Core is halted + [18:18] + + + + + + + DIV + Hardware Divider + DIV + 0x40023800 + + 0x0 + 0x400 + registers + + + + DEND + DEND + Dividend + 0x0 + + + DEND + Dividend + [31:0] + + + + + SOR + SOR + Divisor + 0x4 + + + SOR + Divisor + [31:0] + + + + + QUOT + QUOT + Quotient + 0x8 + read-only + + + QUOT + Quotient + [31:0] + + + + + REMA + REMA + Remainder + 0xC + read-only + + + REMA + Remainder + [31:0] + read-only + + + + + SIGN + SIGN + des SIGN + 0x10 + + + DIV_SIGN + des DIV_SIGN + [0:0] + + + + + STAT + STAT + des SIGN + 0x14 + + + DIV_END + des DIV_END + [0:0] + + + DIV_ZERO + des DIV_ZERO + [1:1] + + + + + + + DMA + Direct memory access + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel 1 Interrupt + 9 + + + DMA1_Channel2_3 + DMA1 Channel 2 and Channel 3 Interrupt + 10 + + + DMA1_Channel4_5_6_7 + DMA1 Channel 4, 5, 6, 7 Interrupts + 11 + + + + ISR + desc ISR + 0x0 + read-only + + + GIF1 + desc GIF1 + [0:0] + read-only + + + TCIF1 + desc TCIF1 + [1:1] + read-only + + + HTIF1 + desc HTIF1 + [2:2] + read-only + + + TEIF1 + desc TEIF1 + [3:3] + read-only + + + GIF2 + desc GIF2 + [4:4] + read-only + + + TCIF2 + desc TCIF2 + [5:5] + read-only + + + HTIF2 + desc HTIF2 + [6:6] + read-only + + + TEIF2 + desc TEIF2 + [7:7] + read-only + + + GIF3 + desc GIF3 + [8:8] + read-only + + + TCIF3 + desc TCIF3 + [9:9] + read-only + + + HTIF3 + desc HTIF3 + [10:10] + read-only + + + TEIF3 + desc TEIF3 + [11:11] + read-only + + + GIF4 + desc GIF4 + [12:12] + read-only + + + TCIF4 + desc TCIF4 + [13:13] + read-only + + + HTIF4 + desc HTIF4 + [14:14] + read-only + + + TEIF4 + desc TEIF4 + [15:15] + read-only + + + GIF5 + desc GIF5 + [16:16] + read-only + + + TCIF5 + desc TCIF5 + [17:17] + read-only + + + HTIF5 + desc HTIF5 + [18:18] + read-only + + + TEIF5 + desc TEIF5 + [19:19] + read-only + + + GIF6 + desc GIF6 + [20:20] + read-only + + + TCIF6 + desc TCIF6 + [21:21] + read-only + + + HTIF6 + desc HTIF6 + [22:22] + read-only + + + TEIF6 + desc TEIF6 + [23:23] + read-only + + + GIF7 + desc GIF7 + [24:24] + read-only + + + TCIF7 + desc TCIF7 + [25:25] + read-only + + + HTIF7 + desc HTIF7 + [26:26] + read-only + + + TEIF7 + desc TEIF7 + [27:27] + read-only + + + + + IFCR + desc IFCR + 0x4 + write-only + + + CGIF1 + desc CGIF1 + [0:0] + write-only + + + CTCIF1 + desc CTCIF1 + [1:1] + write-only + + + CHTIF1 + desc CHTIF1 + [2:2] + write-only + + + CTEIF1 + desc CTEIF1 + [3:3] + write-only + + + CGIF2 + desc CGIF2 + [4:4] + write-only + + + CTCIF2 + desc CTCIF2 + [5:5] + write-only + + + CHTIF2 + desc CHTIF2 + [6:6] + write-only + + + CTEIF2 + desc CTEIF2 + [7:7] + write-only + + + CGIF3 + desc CGIF3 + [8:8] + write-only + + + CTCIF3 + desc CTCIF3 + [9:9] + write-only + + + CHTIF3 + desc CHTIF3 + [10:10] + write-only + + + CTEIF3 + desc CTEIF3 + [11:11] + write-only + + + CGIF4 + desc CGIF4 + [12:12] + write-only + + + CTCIF4 + desc CTCIF4 + [13:13] + write-only + + + CHTIF4 + desc CHTIF4 + [14:14] + write-only + + + CTEIF4 + desc CTEIF4 + [15:15] + write-only + + + CGIF5 + desc CGIF5 + [16:16] + write-only + + + CTCIF5 + desc CTCIF5 + [17:17] + write-only + + + CHTIF5 + desc CHTIF5 + [18:18] + write-only + + + CTEIF5 + desc CTEIF5 + [19:19] + write-only + + + CGIF6 + desc CGIF6 + [20:20] + write-only + + + CTCIF6 + desc CTCIF6 + [21:21] + write-only + + + CHTIF6 + desc CHTIF6 + [22:22] + write-only + + + CTEIF6 + desc CTEIF6 + [23:23] + write-only + + + CGIF7 + desc CGIF7 + [24:24] + write-only + + + CTCIF7 + desc CTCIF7 + [25:25] + write-only + + + CHTIF7 + desc CHTIF7 + [26:26] + write-only + + + CTEIF7 + desc CTEIF7 + [27:27] + write-only + + + + + CCR1 + desc CCR1 + 0x8 + + + EN + desc EN + [0:0] + + + TCIE + desc TCIE + [1:1] + + + HTIE + desc HTIE + [2:2] + + + TEIE + desc TEIE + [3:3] + + + DIR + desc DIR + [4:4] + + + CIRC + desc CIRC + [5:5] + + + PINC + desc PINC + [6:6] + + + MINC + desc MINC + [7:7] + + + PSIZE + desc PSIZE + [9:8] + + + MSIZE + desc MSIZE + [11:10] + + + PL + desc PL + [13:12] + + + MEM2MEM + desc MEM2MEM + [14:14] + + + + + CNDTR1 + desc CNDTR1 + 0xC + + + NDT + desc NDT + [15:0] + + + + + CPAR1 + desc CPAR1 + 0x10 + + + PA + desc PA + [31:0] + + + + + CMAR1 + desc CMAR1 + 0x14 + + + MA + desc MA + [31:0] + + + + + CCR2 + desc CCR2 + 0x1C + + + EN + desc EN + [0:0] + + + TCIE + desc TCIE + [1:1] + + + HTIE + desc HTIE + [2:2] + + + TEIE + desc TEIE + [3:3] + + + DIR + desc DIR + [4:4] + + + CIRC + desc CIRC + [5:5] + + + PINC + desc PINC + [6:6] + + + MINC + desc MINC + [7:7] + + + PSIZE + desc PSIZE + [9:8] + + + MSIZE + desc MSIZE + [11:10] + + + PL + desc PL + [13:12] + + + MEM2MEM + desc MEM2MEM + [14:14] + + + + + CNDTR2 + desc CNDTR2 + 0x20 + + + NDT + desc NDT + [15:0] + + + + + CPAR2 + desc CPAR2 + 0x24 + + + PA + desc PA + [31:0] + + + + + CMAR2 + desc CMAR2 + 0x28 + + + MA + desc MA + [31:0] + + + + + CCR3 + desc CCR3 + 0x30 + + + EN + desc EN + [0:0] + + + TCIE + desc TCIE + [1:1] + + + HTIE + desc HTIE + [2:2] + + + TEIE + desc TEIE + [3:3] + + + DIR + desc DIR + [4:4] + + + CIRC + desc CIRC + [5:5] + + + PINC + desc PINC + [6:6] + + + MINC + desc MINC + [7:7] + + + PSIZE + desc PSIZE + [9:8] + + + MSIZE + desc MSIZE + [11:10] + + + PL + desc PL + [13:12] + + + MEM2MEM + desc MEM2MEM + [14:14] + + + + + CNDTR3 + desc CNDTR3 + 0x34 + + + NDT + desc NDT + [15:0] + + + + + CPAR3 + desc CPAR3 + 0x38 + + + PA + desc PA + [31:0] + + + + + CMAR3 + desc CMAR3 + 0x3C + + + MA + desc MA + [31:0] + + + + + CCR4 + desc CCR4 + 0x44 + + + EN + desc EN + [0:0] + + + TCIE + desc TCIE + [1:1] + + + HTIE + desc HTIE + [2:2] + + + TEIE + desc TEIE + [3:3] + + + DIR + desc DIR + [4:4] + + + CIRC + desc CIRC + [5:5] + + + PINC + desc PINC + [6:6] + + + MINC + desc MINC + [7:7] + + + PSIZE + desc PSIZE + [9:8] + + + MSIZE + desc MSIZE + [11:10] + + + PL + desc PL + [13:12] + + + MEM2MEM + desc MEM2MEM + [14:14] + + + + + CNDTR4 + desc CNDTR4 + 0x48 + + + NDT + desc NDT + [15:0] + + + + + CPAR4 + desc CPAR4 + 0x4C + + + PA + desc PA + [31:0] + + + + + CMAR4 + desc CMAR4 + 0x50 + + + MA + desc MA + [31:0] + + + + + CCR5 + desc CCR5 + 0x58 + + + EN + desc EN + [0:0] + + + TCIE + desc TCIE + [1:1] + + + HTIE + desc HTIE + [2:2] + + + TEIE + desc TEIE + [3:3] + + + DIR + desc DIR + [4:4] + + + CIRC + desc CIRC + [5:5] + + + PINC + desc PINC + [6:6] + + + MINC + desc MINC + [7:7] + + + PSIZE + desc PSIZE + [9:8] + + + MSIZE + desc MSIZE + [11:10] + + + PL + desc PL + [13:12] + + + MEM2MEM + desc MEM2MEM + [14:14] + + + + + CNDTR5 + desc CNDTR5 + 0x5C + + + NDT + desc NDT + [15:0] + + + + + CPAR5 + desc CPAR5 + 0x60 + + + PA + desc PA + [31:0] + + + + + CMAR5 + desc CMAR5 + 0x64 + + + MA + desc MA + [31:0] + + + + + CCR6 + desc CCR6 + 0x6C + + + EN + desc EN + [0:0] + + + TCIE + desc TCIE + [1:1] + + + HTIE + desc HTIE + [2:2] + + + TEIE + desc TEIE + [3:3] + + + DIR + desc DIR + [4:4] + + + CIRC + desc CIRC + [5:5] + + + PINC + desc PINC + [6:6] + + + MINC + desc MINC + [7:7] + + + PSIZE + desc PSIZE + [9:8] + + + MSIZE + desc MSIZE + [11:10] + + + PL + desc PL + [13:12] + + + MEM2MEM + desc MEM2MEM + [14:14] + + + + + CNDTR6 + desc CNDTR6 + 0x70 + + + NDT + desc NDT + [15:0] + + + + + CPAR6 + desc CPAR6 + 0x74 + + + PA + desc PA + [31:0] + + + + + CMAR6 + desc CMAR6 + 0x78 + + + MA + desc MA + [31:0] + + + + + CCR7 + desc CCR7 + 0x80 + + + EN + desc EN + [0:0] + + + TCIE + desc TCIE + [1:1] + + + HTIE + desc HTIE + [2:2] + + + TEIE + desc TEIE + [3:3] + + + DIR + desc DIR + [4:4] + + + CIRC + desc CIRC + [5:5] + + + PINC + desc PINC + [6:6] + + + MINC + desc MINC + [7:7] + + + PSIZE + desc PSIZE + [9:8] + + + MSIZE + desc MSIZE + [11:10] + + + PL + desc PL + [13:12] + + + MEM2MEM + desc MEM2MEM + [14:14] + + + + + CNDTR7 + desc CNDTR7 + 0x84 + + + NDT + desc NDT + [15:0] + + + + + CPAR7 + desc CPAR7 + 0x88 + + + PA + desc PA + [31:0] + + + + + CMAR7 + desc CMAR7 + 0x8C + + + MA + desc MA + [31:0] + + + + + + + EXTI + External interrupt/event controller + EXTI + 0x40021800 + + 0x0 + 0x400 + registers + + + PVD + PVD Interrupt through EXTI Lines 16 + 1 + + + EXTI0_1 + EXTI Line 0 and 1 Interrupt + 5 + + + EXTI2_3 + EXTI Line 2 and 3 Interrupt + 6 + + + EXTI4_15 + EXTI Line 4 to 15 Interrupt + 7 + + + + RTSR + RTSR + EXTI rising trigger selection register + 0x0 + + + RT0 + Rising trigger event configuration bit of Configurable Event input + [0:0] + + + RT1 + Rising trigger event configuration bit of Configurable Event input + [1:1] + + + RT2 + Rising trigger event configuration bit of Configurable Event input + [2:2] + + + RT3 + Rising trigger event configuration bit of Configurable Event input + [3:3] + + + RT4 + Rising trigger event configuration bit of Configurable Event input + [4:4] + + + RT5 + Rising trigger event configuration bit of Configurable Event input + [5:5] + + + RT6 + Rising trigger event configuration bit of Configurable Event input + [6:6] + + + RT7 + Rising trigger event configuration bit of Configurable Event input + [7:7] + + + RT8 + Rising trigger event configuration bit of Configurable Event input + [8:8] + + + RT9 + Rising trigger event configuration bit of Configurable Event input + [9:9] + + + RT10 + Rising trigger event configuration bit of Configurable Event input + [10:10] + + + RT11 + Rising trigger event configuration bit of Configurable Event input + [11:11] + + + RT12 + Rising trigger event configuration bit of Configurable Event input + [12:12] + + + RT13 + Rising trigger event configuration bit of Configurable Event input + [13:13] + + + RT14 + Rising trigger event configuration bit of Configurable Event input + [14:14] + + + RT15 + Rising trigger event configuration bit of Configurable Event input + [15:15] + + + RT16 + Rising trigger event configuration bit of Configurable Event input + [16:16] + + + RT17 + Rising trigger event configuration bit of Configurable Event input + [17:17] + + + RT18 + Rising trigger event configuration bit of Configurable Event input + [18:18] + + + RT20 + Rising trigger event configuration bit of Configurable Event input + [20:20] + + + + + FTSR + FTSR + EXTI falling trigger selection register + 0x4 + + + FT0 + Falling trigger event configuration bit of Configurable Event input + [0:0] + + + FT1 + Falling trigger event configuration bit of Configurable Event input + [1:1] + + + FT2 + Falling trigger event configuration bit of Configurable Event input + [2:2] + + + FT3 + Falling trigger event configuration bit of Configurable Event input + [3:3] + + + FT4 + Falling trigger event configuration bit of Configurable Event input + [4:4] + + + FT5 + Falling trigger event configuration bit of Configurable Event input + [5:5] + + + FT6 + Falling trigger event configuration bit of Configurable Event input + [6:6] + + + FT7 + Falling trigger event configuration bit of Configurable Event input + [7:7] + + + FT8 + Falling trigger event configuration bit of Configurable Event input + [8:8] + + + FT9 + Falling trigger event configuration bit of Configurable Event input + [9:9] + + + FT10 + Falling trigger event configuration bit of Configurable Event input + [10:10] + + + FT11 + Falling trigger event configuration bit of Configurable Event input + [11:11] + + + FT12 + Falling trigger event configuration bit of Configurable Event input + [12:12] + + + FT13 + Falling trigger event configuration bit of Configurable Event input + [13:13] + + + FT14 + Falling trigger event configuration bit of Configurable Event input + [14:14] + + + FT15 + Falling trigger event configuration bit of Configurable Event input + [15:15] + + + FT16 + Falling trigger event configuration bit of Configurable Event input + [16:16] + + + FT17 + Falling trigger event configuration bit of Configurable Event input + [17:17] + + + FT18 + Falling trigger event configuration bit of Configurable Event input + [18:18] + + + FT20 + Falling trigger event configuration bit of Configurable Event input + [20:20] + + + + + SWIER + SWIER + EXTI software interrupt event register + 0x8 + + + SWI0 + Rising trigger event configuration bit of Configurable Event input + [0:0] + + + SWI1 + Rising trigger event configuration bit of Configurable Event input + [1:1] + + + SWI2 + Rising trigger event configuration bit of Configurable Event input + [2:2] + + + SWI3 + Rising trigger event configuration bit of Configurable Event input + [3:3] + + + SWI4 + Rising trigger event configuration bit of Configurable Event input + [4:4] + + + SWI5 + Rising trigger event configuration bit of Configurable Event input + [5:5] + + + SWI6 + Rising trigger event configuration bit of Configurable Event input + [6:6] + + + SWI7 + Rising trigger event configuration bit of Configurable Event input + [7:7] + + + SWI8 + Rising trigger event configuration bit of Configurable Event input + [8:8] + + + SWI9 + Rising trigger event configuration bit of Configurable Event input + [9:9] + + + SWI10 + Rising trigger event configuration bit of Configurable Event input + [10:10] + + + SWI11 + Rising trigger event configuration bit of Configurable Event input + [11:11] + + + SWI12 + Rising trigger event configuration bit of Configurable Event input + [12:12] + + + SWI13 + Rising trigger event configuration bit of Configurable Event input + [13:13] + + + SWI14 + Rising trigger event configuration bit of Configurable Event input + [14:14] + + + SWI15 + Rising trigger event configuration bit of Configurable Event input + [15:15] + + + SWI16 + Rising trigger event configuration bit of Configurable Event input + [16:16] + + + SWI17 + Rising trigger event configuration bit of Configurable Event input + [17:17] + + + SWI18 + Rising trigger event configuration bit of Configurable Event input + [18:18] + + + SWI20 + Rising trigger event configuration bit of Configurable Event input + [20:20] + + + + + PR + PR + EXTI pending register + 0xC + + + PR0 + configurable event inputs x rising edge Pending bit. + [0:0] + + + PR1 + configurable event inputs x rising edge Pending bit. + [1:1] + + + PR2 + configurable event inputs x rising edge Pending bit. + [2:2] + + + PR3 + configurable event inputs x rising edge Pending bit. + [3:3] + + + PR4 + configurable event inputs x rising edge Pending bit. + [4:4] + + + PR5 + configurable event inputs x rising edge Pending bit. + [5:5] + + + PR6 + configurable event inputs x rising edge Pending bit. + [6:6] + + + PR7 + configurable event inputs x rising edge Pending bit. + [7:7] + + + PR8 + configurable event inputs x rising edge Pending bit. + [8:8] + + + PR9 + configurable event inputs x rising edge Pending bit. + [9:9] + + + PR10 + configurable event inputs x rising edge Pending bit. + [10:10] + + + PR11 + configurable event inputs x rising edge Pending bit. + [11:11] + + + PR12 + configurable event inputs x rising edge Pending bit. + [12:12] + + + PR13 + configurable event inputs x rising edge Pending bit + [13:13] + + + PR14 + configurable event inputs x rising edge Pending bit. + [14:14] + + + PR15 + configurable event inputs x rising edge Pending bit. + [15:15] + + + PR16 + configurable event inputs x rising edge Pending bit. + [16:16] + + + PR17 + configurable event inputs x rising edge Pending bit. + [17:17] + + + PR18 + configurable event inputs x rising edge Pending bit. + [18:18] + + + PR20 + configurable event inputs x rising edge Pending bit. + [20:20] + + + + + EXTICR1 + EXTICR1 + EXTI external interrupt selection register + 0x60 + + + EXTI0 + GPIO port selection + [1:0] + + + EXTI1 + GPIO port selection + [9:8] + + + EXTI2 + GPIO port selection + [17:16] + + + EXTI3 + GPIO port selection + [25:24] + + + + + EXTICR2 + EXTICR2 + EXTI external interrupt selection register + 0x64 + + + EXTI4 + GPIO port selection + [1:0] + + + EXTI5 + GPIO port selection + [9:8] + + + EXTI6 + GPIO port selection + [17:16] + + + EXTI7 + GPIO port selection + [25:24] + + + + + EXTICR3 + EXTICR3 + EXTI external interrupt selection register + 0x68 + + + EXTI8 + GPIO port selection + [1:0] + + + EXTI9 + GPIO port selection + [9:8] + + + EXTI10 + GPIO port selection + [17:16] + + + EXTI11 + GPIO port selection + [25:24] + + + + + EXTICR4 + EXTICR4 + EXTI external interrupt selection register + 0x6C + + + EXTI12 + GPIO port selection + [1:0] + + + EXTI13 + GPIO port selection + [9:8] + + + EXTI14 + GPIO port selection + [17:16] + + + EXTI15 + GPIO port selection + [25:24] + + + + + IMR + IMR + EXTI CPU wakeup with interrupt mask register + 0x80 + 0xFFF80000 + + + IM0 + CPU wakeup with interrupt mask on event input + [0:0] + + + IM1 + CPU wakeup with interrupt mask on event input + [1:1] + + + IM2 + CPU wakeup with interrupt mask on event input + [2:2] + + + IM3 + CPU wakeup with interrupt mask on event input + [3:3] + + + IM4 + CPU wakeup with interrupt mask on event input + [4:4] + + + IM5 + CPU wakeup with interrupt mask on event input + [5:5] + + + IM6 + CPU wakeup with interrupt mask on event input + [6:6] + + + IM7 + CPU wakeup with interrupt mask on event input + [7:7] + + + IM8 + CPU wakeup with interrupt mask on event input + [8:8] + + + IM9 + CPU wakeup with interrupt mask on event input + [9:9] + + + IM10 + CPU wakeup with interrupt mask on event input + [10:10] + + + IM11 + CPU wakeup with interrupt mask on event input + [11:11] + + + IM12 + CPU wakeup with interrupt mask on event input + [12:12] + + + IM13 + CPU wakeup with interrupt mask on event input + [13:13] + + + IM14 + CPU wakeup with interrupt mask on event input + [14:14] + + + IM15 + CPU wakeup with interrupt mask on event input + [15:15] + + + IM16 + CPU wakeup with interrupt mask on event input + [16:16] + + + IM17 + CPU wakeup with interrupt mask on event input + [17:17] + + + IM18 + CPU wakeup with interrupt mask on event input + [18:18] + + + IM19 + CPU wakeup with interrupt mask on event input + [19:19] + + + IM20 + CPU wakeup with interrupt mask on event input + [20:20] + + + IM29 + CPU wakeup with interrupt mask on event input + [29:29] + + + + + EMR + EMR + EXTI CPU wakeup with event mask register + 0x84 + + + EM0 + CPU wakeup with event mask on event input + [0:0] + + + EM1 + CPU wakeup with event mask on event input + [1:1] + + + EM2 + CPU wakeup with event mask on event input + [2:2] + + + EM3 + CPU wakeup with event mask on event input + [3:3] + + + EM4 + CPU wakeup with event mask on event input + [4:4] + + + EM5 + CPU wakeup with event mask on event input + [5:5] + + + EM6 + CPU wakeup with event mask on event input + [6:6] + + + EM7 + CPU wakeup with event mask on event input + [7:7] + + + EM8 + CPU wakeup with event mask on event input + [8:8] + + + EM9 + CPU wakeup with event mask on event input + [9:9] + + + EM10 + CPU wakeup with event mask on event input + [10:10] + + + EM11 + CPU wakeup with event mask on event input + [11:11] + + + EM12 + CPU wakeup with event mask on event input + [12:12] + + + EM13 + CPU wakeup with event mask on event input + [13:13] + + + EM14 + CPU wakeup with event mask on event input + [14:14] + + + EM15 + CPU wakeup with event mask on event input + [15:15] + + + EM16 + CPU wakeup with event mask on event input + [16:16] + + + EM17 + CPU wakeup with event mask on event input + [17:17] + + + EM18 + CPU wakeup with event mask on event input + [18:18] + + + EM19 + CPU wakeup with event mask on event input + [19:19] + + + EM20 + CPU wakeup with event mask on event input + [20:20] + + + EM29 + CPU wakeup with event mask on event input + [29:29] + + + + + + + FLASH + desc FLASH + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global Interrupt + 3 + + + + ACR + desc ACR + 0x0 + 0x500 + + + LATENCY + desc LATENCY + [1:0] + + + + + KEYR + desc KEYR + 0x8 + write-only + + + KEY + desc KEY + [31:0] + write-only + + + + + OPTKEYR + desc OPTKEYR + 0xC + write-only + + + OPTKEY + desc OPTKEY + [31:0] + write-only + + + + + SR + desc SR + 0x10 + + + EOP + desc EOP + [0:0] + + + WRPERR + desc WRPERR + [4:4] + + + OPTVERR + desc OPTVERR + [15:15] + + + BSY + desc BSY + [16:16] + read-only + + + + + CR + desc CR + 0x14 + + + PG + desc PG + [0:0] + + + PER + desc PER + [1:1] + + + MER + desc MER + [2:2] + + + SER + desc SER + [11:11] + + + OPTSTRT + desc OPTSTRT + [17:17] + + + PGSTRT + desc PGSTRT + [19:19] + + + EOPIE + desc EOPIE + [24:24] + + + ERRIE + desc ERRIE + [25:25] + + + OBL_LAUNCH + desc OBL_LAUNCH + [27:27] + + + OPTLOCK + desc OPTLOCK + [30:30] + + + LOCK + desc LOCK + [31:31] + + + + + OPTR + desc OPTR + 0x20 + read-only + + + RDP + desc RDP + [7:0] + read-only + + + IWDG_SW + desc IWDG_SW + [11:11] + read-only + + + WWDG_SW + desc WWDG_SW + [12:12] + read-only + + + NRST_MODE + desc NRST_MODE + [13:13] + read-only + + + NBOOT1 + desc nBOOT1 + [14:14] + read-only + + + IWDG_STOP + desc IWDG_STOP + [15:15] + read-only + + + + + SDKR + desc SDKR + 0x24 + read-only + + + SDK_STRT + desc SDK_STRT + [4:0] + read-only + + + BOR_EN + desc BOR_EN + [5:5] + read-only + + + SDK_END + desc SDK_END + [12:8] + read-only + + + BOR_LEV + desc BOR_LEV + [15:13] + read-only + + + + + WRPR + desc WRPR + 0x2C + + + WRP + desc WRP + [15:0] + + + + + STCR + desc STCR + 0x90 + 0x6400 + + + SLEEP_EN + desc SLEEP_EN + [0:0] + + + SLEEP_TIME + desc SLEEP_TIME + [15:8] + + + + + TS0 + desc TS0 + 0x100 + 0xB4 + + + TS0 + desc TS0 + [7:0] + + + + + TS1 + desc TS1 + 0x104 + 0x1B0 + + + TS1 + desc TS1 + [8:0] + + + + + TS2P + desc TS2P + 0x108 + 0xB4 + + + TS2P + desc TS2P + [7:0] + + + + + TPS3 + desc TPS3 + 0x10C + 0x6C0 + + + TPS3 + desc TPS3 + [10:0] + + + + + TS3 + desc TS3 + 0x110 + 0xB4 + + + TS3 + desc TS3 + [7:0] + + + + + PERTPE + desc PERTPE + 0x114 + 0xEA60 + + + PERTPE + desc PERTPE + [16:0] + + + + + SMERTPE + desc SMERTPE + 0x118 + 0xFD20 + + + SMERTPE + desc SMERTPE + [16:0] + + + + + PRGTPE + desc PRGTPE + 0x11C + 0x8CA0 + + + PRGTPE + desc PRGTPE + [15:0] + + + + + PRETPE + desc PRETPE + 0x120 + 0x12C0 + + + PRETPE + desc PRETPE + [13:0] + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x50000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0xEBFFFFFF + + + MODE0 + Port x configuration bits (y=0-15) + [1:0] + + + MODE1 + Port x configuration bits (y=0-15) + [3:2] + + + MODE2 + Port x configuration bits (y=0-15) + [5:4] + + + MODE3 + Port x configuration bits (y=0-15) + [7:6] + + + MODE4 + Port x configuration bits (y=0-15) + [9:8] + + + MODE5 + Port x configuration bits (y=0-15) + [11:10] + + + MODE6 + Port x configuration bits (y=0-15) + [13:12] + + + MODE7 + Port x configuration bits (y=0-15) + [15:14] + + + MODE8 + Port x configuration bits (y=0-15) + [17:16] + + + MODE9 + Port x configuration bits (y=0-15) + [19:18] + + + MODE10 + Port x configuration bits (y=0-15) + [21:20] + + + MODE11 + Port x configuration bits (y=0-15) + [23:22] + + + MODE12 + Port x configuration bits (y=0-15) + [25:24] + + + MODE13 + Port x configuration bits (y=0-15) + [27:26] + + + MODE14 + Port x configuration bits (y=0-15) + [29:28] + + + MODE15 + Port x configuration bits (y=0-15) + [31:30] + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + + + OT0 + Port x configuration bits (y=0-15) + [0:0] + + + OT1 + Port x configuration bits (y=0-15) + [1:1] + + + OT2 + Port x configuration bits (y=0-15) + [2:2] + + + OT3 + Port x configuration bits (y=0-15) + [3:3] + + + OT4 + Port x configuration bits (y=0-15) + [4:4] + + + OT5 + Port x configuration bits (y=0-15) + [5:5] + + + OT6 + Port x configuration bits (y=0-15) + [6:6] + + + OT7 + Port x configuration bits (y=0-15) + [7:7] + + + OT8 + Port x configuration bits (y=0-15) + [8:8] + + + OT9 + Port x configuration bits (y=0-15) + [9:9] + + + OT10 + Port x configuration bits (y=0-15) + [10:10] + + + OT11 + Port x configuration bits (y=0-15) + [11:11] + + + OT12 + Port x configuration bits (y=0-15) + [12:12] + + + OT13 + Port x configuration bits (y=0-15) + [13:13] + + + OT14 + Port x configuration bits (y=0-15) + [14:14] + + + OT15 + Port x configuration bits (y=0-15) + [15:15] + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0xC000000 + + + OSPEED0 + Port x configuration bits (y=0-15) + [1:0] + + + OSPEED1 + Port x configuration bits (y=0-15) + [3:2] + + + OSPEED2 + Port x configuration bits (y=0-15) + [5:4] + + + OSPEED3 + Port x configuration bits (y=0-15) + [7:6] + + + OSPEED4 + Port x configuration bits (y=0-15) + [9:8] + + + OSPEED5 + Port x configuration bits (y=0-15) + [11:10] + + + OSPEED6 + Port x configuration bits (y=0-15) + [13:12] + + + OSPEED7 + Port x configuration bits (y=0-15) + [15:14] + + + OSPEED8 + Port x configuration bits (y=0-15) + [17:16] + + + OSPEED9 + Port x configuration bits (y=0-15) + [19:18] + + + OSPEED10 + Port x configuration bits (y=0-15) + [21:20] + + + OSPEED11 + Port x configuration bits (y=0-15) + [23:22] + + + OSPEED12 + Port x configuration bits (y=0-15) + [25:24] + + + OSPEED13 + Port x configuration bits (y=0-15) + [27:26] + + + OSPEED14 + Port x configuration bits (y=0-15) + [29:28] + + + OSPEED15 + Port x configuration bits (y=0-15) + [31:30] + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x24000000 + + + PUPD0 + Port x configuration bits (y=0-15) + [1:0] + + + PUPD1 + Port x configuration bits (y=0-15) + [3:2] + + + PUPD2 + Port x configuration bits (y=0-15) + [5:4] + + + PUPD3 + Port x configuration bits (y=0-15) + [7:6] + + + PUPD4 + Port x configuration bits (y=0-15) + [9:8] + + + PUPD5 + Port x configuration bits (y=0-15) + [11:10] + + + PUPD6 + Port x configuration bits (y=0-15) + [13:12] + + + PUPD7 + Port x configuration bits (y=0-15) + [15:14] + + + PUPD8 + Port x configuration bits (y=0-15) + [17:16] + + + PUPD9 + Port x configuration bits (y=0-15) + [19:18] + + + PUPD10 + Port x configuration bits (y=0-15) + [21:20] + + + PUPD11 + Port x configuration bits (y=0-15) + [23:22] + + + PUPD12 + Port x configuration bits (y=0-15) + [25:24] + + + PUPD13 + Port x configuration bits (y=0-15) + [27:26] + + + PUPD14 + Port x configuration bits (y=0-15) + [29:28] + + + PUPD15 + Port x configuration bits (y=0-15) + [31:30] + + + + + IDR + IDR + GPIO port input data register + 0x10 + read-only + + + ID0 + Port input data (y=0-15) + [0:0] + + + ID1 + Port input data (y=0-15) + [1:1] + + + ID2 + Port input data (y=0-15) + [2:2] + + + ID3 + Port input data (y=0-15) + [3:3] + + + ID4 + Port input data (y=0-15) + [4:4] + + + ID5 + Port input data (y=0-15) + [5:5] + + + ID6 + Port input data (y=0-15) + [6:6] + + + ID7 + Port input data (y=0-15) + [7:7] + + + ID8 + Port input data (y=0-15) + [8:8] + + + ID9 + Port input data (y=0-15) + [9:9] + + + ID10 + Port input data (y=0-15) + [10:10] + + + ID11 + Port input data (y=0-15) + [11:11] + + + ID12 + Port input data (y=0-15) + [12:12] + + + ID13 + Port input data (y=0-15) + [13:13] + + + ID14 + Port input data (y=0-15) + [14:14] + + + ID15 + Port input data (y=0-15) + [15:15] + + + + + ODR + ODR + GPIO port output data register + 0x14 + + + OD0 + Port output data (y=0-15) + [0:0] + + + OD1 + Port output data (y=0-15) + [1:1] + + + OD2 + Port output data (y=0-15) + [2:2] + + + OD3 + Port output data (y=0-15) + [3:3] + + + OD4 + Port output data (y=0-15) + [4:4] + + + OD5 + Port output data (y=0-15) + [5:5] + + + OD6 + Port output data (y=0-15) + [6:6] + + + OD7 + Port output data (y=0-15) + [7:7] + + + OD8 + Port output data (y=0-15) + [8:8] + + + OD9 + Port output data (y=0-15) + [9:9] + + + OD10 + Port output data (y=0-15) + [10:10] + + + OD11 + Port output data (y=0-15) + [11:11] + + + OD12 + Port output data (y=0-15) + [12:12] + + + OD13 + Port output data (y=0-15) + [13:13] + + + OD14 + Port output data (y=0-15) + [14:14] + + + OD15 + Port output data (y=0-15) + [15:15] + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + write-only + + + BS0 + Port x set bit y (y=0-15) + [0:0] + + + BS1 + Port x set bit y (y=0-15) + [1:1] + + + BS2 + Port x set bit y (y=0-15) + [2:2] + + + BS3 + Port x set bit y (y=0-15) + [3:3] + + + BS4 + Port x set bit y (y=0-15) + [4:4] + + + BS5 + Port x set bit y (y=0-15) + [5:5] + + + BS6 + Port x set bit y (y=0-15) + [6:6] + + + BS7 + Port x set bit y (y=0-15) + [7:7] + + + BS8 + Port x set bit y (y=0-15) + [8:8] + + + BS9 + Port x set bit y (y=0-15) + [9:9] + + + BS10 + Port x set bit y (y=0-15) + [10:10] + + + BS11 + Port x set bit y (y=0-15) + [11:11] + + + BS12 + Port x set bit y (y=0-15) + [12:12] + + + BS13 + Port x set bit y (y=0-15) + [13:13] + + + BS14 + Port x set bit y (y=0-15) + [14:14] + + + BS15 + Port x set bit y (y=0-15) + [15:15] + + + BR0 + Port x set bit y (y=0-15) + [16:16] + + + BR1 + Port x reset bit y (y=0-15) + [17:17] + + + BR2 + Port x reset bit y (y=0-15) + [18:18] + + + BR3 + Port x reset bit y (y=0-15) + [19:19] + + + BR4 + Port x reset bit y (y=0-15) + [20:20] + + + BR5 + Port x reset bit y (y=0-15) + [21:21] + + + BR6 + Port x reset bit y (y=0-15) + [22:22] + + + BR7 + Port x reset bit y (y=0-15) + [23:23] + + + BR8 + Port x reset bit y (y=0-15) + [24:24] + + + BR9 + Port x reset bit y (y=0-15) + [25:25] + + + BR10 + Port x reset bit y (y=0-15) + [26:26] + + + BR11 + Port x reset bit y (y=0-15) + [27:27] + + + BR12 + Port x reset bit y (y=0-15) + [28:28] + + + BR13 + Port x reset bit y (y=0-15) + [29:29] + + + BR14 + Port x reset bit y (y=0-15) + [30:30] + + + BR15 + Port x reset bit y (y=0-15) + [31:31] + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + + + LCK0 + Port x lock bit y (y=0-15) + [0:0] + + + LCK1 + Port x lock bit y (y=0-15) + [1:1] + + + LCK2 + Port x lock bit y (y=0-15) + [2:2] + + + LCK3 + Port x lock bit y (y=0-15) + [3:3] + + + LCK4 + Port x lock bit y (y=0-15) + [4:4] + + + LCK5 + Port x lock bit y (y=0-15) + [5:5] + + + LCK6 + Port x lock bit y (y=0-15) + [6:6] + + + LCK7 + Port x lock bit y (y=0-15) + [7:7] + + + LCK8 + Port x lock bit y (y=0-15) + [8:8] + + + LCK9 + Port x lock bit y (y=0-15) + [9:9] + + + LCK10 + Port x lock bit y (y=0-15) + [10:10] + + + LCK11 + Port x lock bit y (y=0-15) + [11:11] + + + LCK12 + Port x lock bit y (y=0-15) + [12:12] + + + LCK13 + Port x lock bit y (y=0-15) + [13:13] + + + LCK14 + Port x lock bit y (y=0-15) + [14:14] + + + LCK15 + Port x lock bit y (y=0-15) + [15:15] + + + LCKK + Port x lock (LCKK) + [16:16] + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + + + AFSEL0 + Alternate function selection for port x bit y (y=0-7) + [3:0] + + + AFSEL1 + Alternate function selection for port x bit y (y=0-7) + [7:4] + + + AFSEL2 + Alternate function selection for port x bit y (y=0-7) + [11:8] + + + AFSEL3 + Alternate function selection for port x bit y (y=0-7) + [15:12] + + + AFSEL4 + Alternate function selection for port x bit y (y=0-7) + [19:16] + + + AFSEL5 + Alternate function selection for port x bit y (y=0-7) + [23:20] + + + AFSEL6 + Alternate function selection for port x bit y (y=0-7) + [27:24] + + + AFSEL7 + Alternate function selection for port x bit y (y=0-7) + [31:28] + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + + + AFSEL8 + Alternate function selection for port x bit y (y=8-15) + [3:0] + + + AFSEL9 + Alternate function selection for port x bit y (y=8-15) + [7:4] + + + AFSEL10 + Alternate function selection for port x bit y (y=8-15) + [11:8] + + + AFSEL11 + Alternate function selection for port x bit y (y=8-15) + [15:12] + + + AFSEL12 + Alternate function selection for port x bit y (y=8-15) + [19:16] + + + AFSEL13 + Alternate function selection for port x bit y (y=8-15) + [23:20] + + + AFSEL14 + Alternate function selection for port x bit y (y=8-15) + [27:24] + + + AFSEL15 + Alternate function selection for port x bit y (y=8-15) + [31:28] + + + + + BRR + BRR + port bit reset register + 0x28 + write-only + + + BR0 + Port Reset bit + [0:0] + + + BR1 + Port Reset bit + [1:1] + + + BR2 + Port Reset bit + [2:2] + + + BR3 + Port Reset bit + [3:3] + + + BR4 + Port Reset bit + [4:4] + + + BR5 + Port Reset bit + [5:5] + + + BR6 + Port Reset bit + [6:6] + + + BR7 + Port Reset bit + [7:7] + + + BR8 + Port Reset bit + [8:8] + + + BR9 + Port Reset bit + [9:9] + + + BR10 + Port Reset bit + [10:10] + + + BR11 + Port Reset bit + [11:11] + + + BR12 + Port Reset bit + [12:12] + + + BR13 + Port Reset bit + [13:13] + + + BR14 + Port Reset bit + [14:14] + + + BR15 + Port Reset bit + [15:15] + + + + + + + GPIOB + General-purpose I/Os + GPIO + 0x50000400 + + 0x0 + 0x400 + registers + + + + GPIOC + General-purpose I/Os + GPIO + 0x50000800 + + 0x0 + 0x400 + registers + + + + GPIOF + General-purpose I/Os + GPIO + 0x50001400 + + 0x0 + 0x400 + registers + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global Interrupt + 23 + + + + CR1 + desc CR1 + 0x0 + + + PE + desc PE + [0:0] + + + SMBUS + desc SMBUS + [1:1] + + + SMBTYPE + desc SMBTYPE + [3:3] + + + ENARP + desc ENARP + [4:4] + + + ENPEC + desc ENPEC + [5:5] + + + ENGC + desc ENGC + [6:6] + + + NOSTRETCH + desc NOSTRETCH + [7:7] + + + START + desc START + [8:8] + + + STOP + desc STOP + [9:9] + + + ACK + desc ACK + [10:10] + + + POS + desc POS + [11:11] + + + PEC + desc PEC + [12:12] + + + ALERT + desc ALERT + [13:13] + + + SWRST + desc SWRST + [15:15] + + + + + CR2 + desc CR2 + 0x4 + + + FREQ + desc FREQ + [5:0] + + + ITERREN + desc ITERREN + [8:8] + + + ITEVTEN + desc ITEVTEN + [9:9] + + + ITBUFEN + desc ITBUFEN + [10:10] + + + DMAEN + desc DMAEN + [11:11] + + + LAST + desc LAST + [12:12] + + + + + OAR1 + desc OAR1 + 0x8 + + + ADD0 + desc ADD0 + [0:0] + + + ADD1_7 + desc ADD1_7 + [7:1] + + + ADD8_9 + desc ADD8_9 + [9:8] + + + ADDMODE + desc ADDMODE + [15:15] + + + + + OAR2 + desc OAR2 + 0xC + + + ENDUAL + desc ENDUAL + [0:0] + + + ADD2 + desc ADD2 + [7:1] + + + + + DR + desc DR + 0x10 + + + DR + desc DR + [7:0] + + + + + SR1 + desc SR1 + 0x14 + + + SB + desc SB + [0:0] + read-only + + + ADDR + desc ADDR + [1:1] + read-only + + + BTF + desc BTF + [2:2] + read-only + + + ADD10 + desc ADD10 + [3:3] + read-only + + + STOPF + desc STOPF + [4:4] + read-only + + + RXNE + desc RXNE + [6:6] + read-only + + + TXE + desc TXE + [7:7] + read-only + + + BERR + desc BERR + [8:8] + + + ARLO + desc ARLO + [9:9] + + + AF + desc AF + [10:10] + + + OVR + desc OVR + [11:11] + + + PECERR + desc PECERR + [12:12] + + + TIMEOUT + desc TIMEOUT + [14:14] + + + SMBALERT + desc SMBALERT + [15:15] + + + + + SR2 + desc SR2 + 0x18 + read-only + + + MSL + desc MSL + [0:0] + read-only + + + BUSY + desc BUSY + [1:1] + read-only + + + TRA + desc TRA + [2:2] + read-only + + + GENCALL + desc GENCALL + [4:4] + read-only + + + SMBDEFAULT + desc SMBDEFAULT + [5:5] + read-only + + + SMBHOST + desc SMBHOST + [6:6] + read-only + + + DUALF + desc DUALF + [7:7] + read-only + + + PEC + desc PEC + [15:8] + read-only + + + + + CCR + desc CCR + 0x1C + + + CCR + desc CCR + [11:0] + + + DUTY + desc DUTY + [14:14] + + + FS + desc FS + [15:15] + + + + + TRISE + desc TRISE + 0x20 + 0x2 + + + TRISE + desc TRISE + [5:0] + + + + + + + I2C2 + desc I2C + I2C + 0x40005800 + + 0x0 + 0x400 + registers + + + I2C2 + I2C2 Event Interrupt + 24 + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register (IWDG_KR) + 0x0 + write-only + + + KEY + Key value + [15:0] + + + + + PR + PR + Prescaler register (IWDG_PR) + 0x4 + + + PR + Prescaler divider + [2:0] + + + + + RLR + RLR + Reload register (IWDG_RLR) + 0x8 + 0xFFF + + + RL + Watchdog counter reload value + [11:0] + + + + + SR + SR + Status register (IWDG_SR) + 0xC + read-only + + + PVU + Watchdog prescaler value update + [0:0] + + + RVU + Watchdog counter reload value update + [1:1] + + + + + + + LCD + LCD CONTROLLER + LCD + 0x40002400 + + 0x0 + 0x400 + registers + + + LCD + LCD global Interrupt + 8 + + + + CR0 + CR0 + Control register + 0x0 + + + EN + EN + [0:0] + + + LCDCLK + LCDCLK + [2:1] + + + BIAS + BIAS + [5:5] + + + DUTY + DUTY + [8:6] + + + BSEL + BSEL + [11:9] + + + CONTRAST + CONTRAST + [15:12] + + + + + CR1 + CR1 + CR1 + 0x4 + + + BLINKCNT + BLINKCNT + [5:0] + + + BLINKEN + BLINKEN + [6:6] + + + MODE + MODE + [8:8] + + + IE + IE + [9:9] + + + DMAEN + DMAEN + [10:10] + + + INTF + INTF + [11:11] + + + + + INTCLR + INTCLR + INTCLR + 0x8 + + + INTF_CLR + INTF_CLR + [10:10] + + + + + POEN0 + POEN0 + POEN0 + 0xC + + + S0 + S0 + [0:0] + + + S1 + S1 + [1:1] + + + S2 + S2 + [2:2] + + + S3 + S3 + [3:3] + + + S4 + S4 + [4:4] + + + S5 + S5 + [5:5] + + + S6 + S6 + [6:6] + + + S7 + S7 + [7:7] + + + S8 + S8 + [8:8] + + + S9 + S9 + [9:9] + + + S10 + S10 + [10:10] + + + S11 + S11 + [11:11] + + + S12 + S12 + [12:12] + + + S13 + S13 + [13:13] + + + S14 + S14 + [14:14] + + + S15 + S15 + [15:15] + + + S16 + S16 + [16:16] + + + S17 + S17 + [17:17] + + + S18 + S18 + [18:18] + + + S19 + S19 + [19:19] + + + S20 + S20 + [20:20] + + + S21 + S21 + [21:21] + + + S22 + S22 + [22:22] + + + S23 + S23 + [23:23] + + + S24 + S24 + [24:24] + + + S25 + S25 + [25:25] + + + S26 + S26 + [26:26] + + + S27 + S27 + [27:27] + + + S28 + S28 + [28:28] + + + S29 + S29 + [29:29] + + + S30 + S30 + [30:30] + + + S31 + S31 + [31:31] + + + + + POEN1 + POEN1 + POEN1 + 0x10 + + + S32 + S32 + [0:0] + + + S33 + S33 + [1:1] + + + S34 + S34 + [2:2] + + + S35 + S35 + [3:3] + + + S39C4 + S39 + [4:4] + + + S38C5 + S38 + [5:5] + + + S37C6 + S37 + [6:6] + + + S36C7 + S36 + [7:7] + + + C0 + C0 + [8:8] + + + C1 + C1 + [9:9] + + + C2 + C2 + [10:10] + + + C3 + C3 + [11:11] + + + MUX + MUX + [12:12] + + + + + RAM0 + RAM0 + des RAM0 + 0x14 + + + D + des D + [31:0] + + + + + RAM1 + RAM1 + des RAM1 + 0x18 + + + D + des D + [31:0] + + + + + RAM2 + RAM2 + des RAM2 + 0x1C + + + D + des D + [31:0] + + + + + RAM3 + RAM3 + des RAM3 + 0x20 + + + D + des D + [31:0] + + + + + RAM4 + RAM4 + des RAM4 + 0x24 + + + D + des D + [31:0] + + + + + RAM5 + RAM5 + des RAM5 + 0x28 + + + D + des D + [31:0] + + + + + RAM6 + RAM6 + des RAM6 + 0x2C + + + D + des D + [31:0] + + + + + RAM7 + RAM7 + des RAM7 + 0x30 + + + D + des D + [31:0] + + + + + RAM8 + RAM8 + des RAM8 + 0x34 + + + D + des D + [7:0] + + + + + RAM9 + RAM9 + des RAM9 + 0x38 + + + D + des D + [7:0] + + + + + RAM10 + RAM10 + des RAM10 + 0x3C + + + D + des D + [7:0] + + + + + RAM11 + RAM11 + des RAM11 + 0x40 + + + D + des D + [7:0] + + + + + RAM12 + RAM12 + des RAM12 + 0x44 + + + D + des D + [7:0] + + + + + RAM13 + RAM13 + des RAM13 + 0x48 + + + D + des D + [7:0] + + + + + RAM14 + RAM14 + des RAM14 + 0x4C + + + D + des D + [7:0] + + + + + RAM15 + RAM15 + des RAM15 + 0x50 + + + D + des D + [7:0] + + + + + + + LPTIM1 + Low power timer + LPTIM1 + 0x40007C00 + + 0x0 + 0x400 + registers + + + TIM6_LPTIM1 + TIM6, LPTIM1 global Interrupts + 17 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + read-only + + + ARRM + Autoreload match + [1:1] + + + ARROK + Autoreload match update OK + [4:4] + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + write-only + + + ARRMCF + Autoreload match Clear Flag + [1:1] + + + ARROKCF + Autoreload match update OK Clear Flag + [4:4] + + + + + IER + IER + Interrupt Enable Register + 0x8 + + + ARRMIE + Autoreload matchInterrupt Enable + [1:1] + + + ARROKIE + Autoreload match update OK Interrupt Enable + [4:4] + + + + + CFGR + CFGR + Configuration Register + 0xC + + + PRESC + Clock prescaler + [11:9] + + + PRELOAD + Registers update mode + [22:22] + + + + + CR + CR + Control Register + 0x10 + + + ENABLE + LPTIM Enable + [0:0] + + + SNGSTRT + LPTIM start in single mode + [1:1] + + + CNTSTRT + CNTSTRT + [2:2] + + + COUNTRST + LPTIM counter reset + [3:3] + + + RSTARE + Reset after read enable + [4:4] + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x1 + + + ARR + Auto reload value + [15:0] + + + + + CNT + CNT + Counter Register + 0x1C + read-only + + + CNT + Counter value + [15:0] + + + + + + + OPA + des OPA + OPA + 0x40010300 + + 0x0 + 0x400 + registers + + + + CR0 + CR0 + CR0 register + 0x30 + 0xFFFFFFFF + + + OP1OEN1 + OP1OEN1 + [1:1] + + + OP2OEN1 + OP2OEN1 + [6:6] + + + + + CR1 + CR1 + CR1 register + 0x34 + + + EN1 + EN1 + [5:5] + + + EN2 + EN2 + [6:6] + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Power control register 1 + 0x0 + 0x30000 + + + BIAS_CR + MR Bias current + [2:0] + + + BIAS_CR_SEL + MR Bias current selection + [4:4] + + + DBP + Disable backup domain write protection + [8:8] + + + VOS + Voltage scaling range selection + [10:9] + + + FLS_SLPTIME + Flash wait time after wakeup from the stop mode + [13:12] + + + LPR + Low-power run + [14:14] + + + HSION_CTRL + HSI open time control + [19:19] + + + + + CR2 + CR2 + Power control register 2 + 0x4 + 0x500 + + + PVDE + Power voltage detector enable + [0:0] + + + SRCSEL + Power voltage detector volatage selection + [2:2] + + + PVDT + Power voltage detector threshold selection + [6:4] + + + FLTEN + Digital filter enable + [8:8] + + + FLT_TIME + Digital filter time configuration + [11:9] + + + + + SR + SR + Power status register + 0x14 + read-only + + + PVDO + PVD output + [11:11] + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC_CTC + RCC and CTC global Interrupts + 4 + + + + CR + CR + Clock control register + 0x0 + 0x100 + + + HSION + HSI16 clock enable + [8:8] + + + HSIRDY + HSI16 clock ready flag + [10:10] + + + HSIDIV + HSI16 clock division factor + [13:11] + + + HSEON + HSE clock enable + [16:16] + + + HSERDY + HSE clock ready flag + [17:17] + + + HSEBYP + HSE crystal oscillator bypass + [18:18] + + + CSSON + Clock security system enable + [19:19] + + + ADC_DIV + ADC Frequency Division + [22:21] + + + PLLON + PLL enable + [24:24] + + + PLLRDY + PLL clock ready flag + [25:25] + + + + + ICSCR + ICSCR + Internal clock sources calibration register + 0x4 + 0x10000000 + + + HSI_TRIM + HSI clock trimming + [12:0] + + + HSI_FS + HSI frequency selection + [15:13] + + + LSI_TRIM + LSI clock trimming + [24:16] + + + + + CFGR + CFGR + Clock configuration register + 0x8 + + + SW + System clock switch + [2:0] + + + SWS + System clock switch status + [5:3] + read-only + + + HPRE + AHB prescaler + [11:8] + + + PPRE + APB prescaler + [14:12] + + + MCOSEL + Microcontroller clock output + [26:24] + + + MCOPRE + Microcontroller clock output prescaler + [30:28] + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0xC + + + PLLSRC + PLL clock source selection + [1:0] + + + PLLMUL + PLLMUL + [3:2] + + + + + ECSCR + ECSCR + External clock source control register + 0x10 + + + HSE_DRV + HSE_DRV + [1:0] + + + HSE_STARTUP + HSE_STARTUP + [4:3] + + + LSE_DRIVER + LSE clock driver selection + [17:16] + + + LSE_STARTUP + LSE_STARTUP + [21:20] + + + + + CIER + CIER + Clock interrupt enable register + 0x18 + + + LSIRDYIE + LSI ready interrupt enable + [0:0] + + + LSERDYIE + LSE ready interrupt enable + [1:1] + + + HSIRDYIE + HSI ready interrupt enable + [3:3] + + + HSERDYIE + HSE ready interrupt enable + [4:4] + + + PLLRDYIE + PLL ready interrupt enable + [5:5] + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + read-only + + + LSIRDYF + LSI ready interrupt flag + [0:0] + + + LSERDYF + LSE ready interrupt flag + [1:1] + + + HSIRDYF + HSI ready interrupt flag + [3:3] + + + HSERDYF + HSE ready interrupt flag + [4:4] + + + PLLRDYF + PLL ready interrupt flag + [5:5] + + + CSSF + HSE clock secure system interrupt flag + [8:8] + + + LSECSSF + LSE clock secure system interrupt flag + [9:9] + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + write-only + + + LSIRDYC + LSI ready interrupt clear + [0:0] + + + LSERDYC + LSE ready interrupt clear + [1:1] + + + HSIRDYC + HSI ready interrupt clear + [3:3] + + + HSERDYC + HSE ready interrupt clear + [4:4] + + + PLLRDYC + PLL ready interrupt clear + [5:5] + + + CSSC + clock secure system interrupt flag clear + [8:8] + + + LSECSSC + LSE clock secure system interrupt flag clear + [9:9] + + + + + IOPRSTR + IOPRSTR + GPIO reset register + 0x24 + + + GPIOARST + I/O port A reset + [0:0] + + + GPIOBRST + I/O port B reset + [1:1] + + + GPIOCRST + I/O port F reset + [2:2] + + + GPIOFRST + I/O port F reset + [5:5] + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x28 + + + DMARST + DMA reset + [0:0] + + + CRCRST + CRC reset + [12:12] + + + DIVRST + DIV reset + [24:24] + + + + + APBRSTR1 + APBRSTR1 + APB peripheral reset register 1 + 0x2C + + + TIM2RST + TIM2 timer reset + [0:0] + + + TIM3RST + TIM3 timer reset + [1:1] + + + TIM6RST + TIM6 timer reset + [4:4] + + + TIM7RST + TIM7 timer reset + [5:5] + + + RTCAPBRST + RTCAPB reset + [10:10] + + + WWDGRST + WWDG reset + [11:11] + + + SPI2RST + SPI2 reset + [14:14] + + + USART2RST + USART2 reset + [17:17] + + + USART3RST + USART3 reset + [18:18] + + + USART4RST + USART4 reset + [19:19] + + + I2C1RST + I2C1 reset + [21:21] + + + I2C2RST + I2C2 reset + [22:22] + + + CTCRST + CTCRST + [27:27] + + + PWRRST + Power interface reset + [28:28] + + + OPARST + OPARST + [30:30] + + + LPTIMRST + Low Power Timer reset + [31:31] + + + + + APBRSTR2 + APBRSTR2 + APB peripheral reset register 2 + 0x30 + + + SYSCFGRST + SYSCFG reset + [0:0] + + + ADCRST + ADC reset + [9:9] + + + DBGRST + DBG reset + [10:10] + + + TIM1RST + TIM1 reset + [11:11] + + + SPI1RST + SPI1 reset + [12:12] + + + USART1RST + USART1 reset + [14:14] + + + TIM14RST + TIM14 reset + [15:15] + + + TIM15RST + TIM15 reset + [16:16] + + + TIM16RST + TIM16 reset + [17:17] + + + TIM17RST + TIM17 reset + [18:18] + + + COMP1RST + COMP1 reset + [20:20] + + + COMP2RST + COMP2 reset + [21:21] + + + LCDRST + LCD reset + [23:23] + + + + + IOPENR + IOPENR + GPIO clock enable register + 0x34 + + + GPIOAEN + I/O port A clock enable + [0:0] + + + GPIOBEN + I/O port B clock enable + [1:1] + + + GPIOCEN + I/O port C clock enable + [2:2] + + + GPIOFEN + I/O port F clock enable + [5:5] + + + + + AHBENR + AHBENR + AHB peripheral clock enable register + 0x38 + + + DMAEN + DMA clock enable + [0:0] + + + FLASHEN + Flash memory interface clock enable + [8:8] + + + SRAMEN + SRAM memory interface clock enable + [9:9] + + + CRCEN + CRC clock enable + [12:12] + + + DIVEN + DIVEN + [24:24] + + + + + APBENR1 + APBENR1 + APB peripheral clock enable register 1 + 0x3C + + + TIM2EN + TIM2 timer clock enable + [0:0] + + + TIM3EN + TIM3 timer clock enable + [1:1] + + + TIM6EN + TIM6 timer clock enable + [4:4] + + + TIM7EN + TIM7 timer clock enable + [5:5] + + + RTCAPBEN + RTC APB clock enable + [10:10] + + + WWDGEN + WWDG clock enable + [11:11] + + + SPI2EN + SPI2 clock enable + [14:14] + + + USART2EN + USART2 clock enable + [17:17] + + + USART3EN + USART3 clock enable + [18:18] + + + USART4EN + USART4 clock enable + [19:19] + + + I2C1EN + I2C1 clock enable + [21:21] + + + I2C2EN + I2C2 clock enable + [22:22] + + + CTCEN + CTC clock enable + [27:27] + + + PWREN + Power interface clock enable + [28:28] + + + OPAEN + OPA clock enable + [30:30] + + + LPTIMEN + LPTIM clock enable + [31:31] + + + + + APBENR2 + APBENR2 + APB peripheral clock enable register 2 + 0x40 + + + SYSCFGEN + SYSCFG, COMP and VREFBUF clock enable + [0:0] + + + ADCEN + ADCEN clock enable + [9:9] + + + DBGEN + DBG clock enable + [10:10] + + + TIM1EN + TIM1 clock enable + [11:11] + + + SPI1EN + SPI1 clock enable + [12:12] + + + USART1EN + USART1 clock enable + [14:14] + + + TIM14EN + TIM14 clock enable + [15:15] + + + TIM15EN + TIM15 clock enable + [16:16] + + + TIM16EN + TIM16 clock enable + [17:17] + + + TIM17EN + TIM17 clock enable + [18:18] + + + COMP1EN + COMP1 clock enable + [20:20] + + + COMP2EN + COMP2 clock enable + [21:21] + + + LCDEN + LCD clock enable + [23:23] + + + + + CCIPR + CCIPR + Peripherals independent clock configuration register + 0x54 + + + PVDSEL + PVD detect clock source selection + [7:7] + + + COMP1SEL + COMP1 clock source selection + [8:8] + + + COMP2SEL + COMP2 clock source selection + [9:9] + + + LPTIM1SEL + LPTIM1 clock source selection + [19:18] + + + + + BDCR + BDCR + RTC domain control register + 0x5C + + + LSEON + LSE oscillator enable + [0:0] + + + LSERDY + LSE oscillator ready + [1:1] + + + LSEBYP + LSE oscillator bypass + [2:2] + + + LSECSSON + LSE CSS enable + [5:5] + + + LSECSSD + LSE CSS detect + [6:6] + + + RTCSEL + RTC clock source selection + [9:8] + + + RTCEN + RTC clock source enable + [15:15] + + + BDRST + RTC domain software reset + [16:16] + + + LSCOEN + Low-speed clock output (LSCO) enable + [24:24] + + + LSCOSEL + Low-speed clock output selection + [25:25] + + + + + CSR + CSR + Control/status register + 0x60 + + + LSION + LSI oscillator enable + [0:0] + + + LSIRDY + LSI oscillator ready + [1:1] + + + NRST_FLTDIS + NRST_FLTDIS oscillator ready + [8:8] + + + RMVF + Remove reset flags + [23:23] + + + OBLRSTF + Option byte loader reset flag + [25:25] + + + PINRSTF + Pin reset flag + [26:26] + + + PWRRSTF + BOR or POR/PDR flag + [27:27] + + + SFTRSTF + Software reset flag + [28:28] + + + IWDGRSTF + Independent window watchdog reset flag + [29:29] + + + WWDGRSTF + Window watchdog reset flag + [30:30] + + + + + + + RTC + desc RTC + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC Interrupt through EXTI Lines 19 + 2 + + + + CRH + desc CRH + 0x0 + + + SECIE + desc SECIE + [0:0] + + + ALRIE + desc ALRIE + [1:1] + + + OWIE + desc OWIE + [2:2] + + + + + CRL + desc CRL + 0x4 + 0x20 + + + SECF + desc SECF + [0:0] + + + ALRF + desc ALRF + [1:1] + + + OWF + desc OWF + [2:2] + + + RSF + desc RSF + [3:3] + + + CNF + desc CNF + [4:4] + + + RTOFF + desc RTOFF + [5:5] + read-only + + + + + PRLH + desc PRLH + 0x8 + write-only + + + PRL + desc PRL + [3:0] + write-only + + + + + PRLL + desc PRLL + 0xC + write-only + 0x8000 + + + PRL + desc PRL + [15:0] + write-only + + + + + DIVH + desc DIVH + 0x10 + read-only + + + DIV + desc DIV + [3:0] + read-only + + + + + DIVL + desc DIVL + 0x14 + read-only + 0x8000 + + + DIV + desc DIV + [15:0] + read-only + + + + + CNTH + desc CNTH + 0x18 + + + RTC_CNT + desc RTC_CNT + [15:0] + + + + + CNTL + desc CNTL + 0x1C + + + RTC_CNT + desc RTC_CNT + [15:0] + + + + + ALRH + desc ALRH + 0x20 + 0xFFFF + + + RTC_ALR + desc RTC_ALR + [15:0] + + + + + ALRL + desc ALRL + 0x24 + 0xFFFF + + + RTC_ALR + desc RTC_ALR + [15:0] + + + + + BKP_RTCCR + desc BKP_RTCCR + 0x2C + + + CAL + desc CAL + [6:0] + + + CCO + desc CCO + [7:7] + + + ASOE + desc ASOE + [8:8] + + + ASOS + desc ASOS + [9:9] + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global Interrupt + 25 + + + + CR1 + desc CR1 + 0x0 + + + CPHA + desc CPHA + [0:0] + + + CPOL + desc CPOL + [1:1] + + + MSTR + desc MSTR + [2:2] + + + BR + desc BR + [5:3] + + + SPE + desc SPE + [6:6] + + + LSBFIRST + desc LSBFIRST + [7:7] + + + SSI + desc SSI + [8:8] + + + SSM + desc SSM + [9:9] + + + RXONLY + desc RXONLY + [10:10] + + + DDF + desc DDF + [11:11] + + + CRCNEXT + desc CRCNEXT + [12:12] + + + CRCEN + desc CRCEN + [13:13] + + + BIDIOE + desc BIDIOE + [14:14] + + + BIDIMODE + desc BIDIMODE + [15:15] + + + + + CR2 + desc CR2 + 0x4 + + + RXDMAEN + desc RXDMAEN + [0:0] + + + TXDMAEN + desc TXDMAEN + [1:1] + + + SSOE + desc SSOE + [2:2] + + + CLRTXFIFO + desc CLRTXFIFO + [4:4] + + + ERRIE + desc ERRIE + [5:5] + + + RXNEIE + desc RXNEIE + [6:6] + + + TXEIE + desc TXEIE + [7:7] + + + FRXTH + desc FRXTH + [12:12] + + + LDMA_RX + desc LDMA_RX + [13:13] + + + LDMA_TX + desc LDMA_TX + [14:14] + + + + + SR + desc SR + 0x8 + 0x2 + + + RXNE + desc RXNE + [0:0] + read-only + + + TXE + desc TXE + [1:1] + read-only + + + CHSIDE + desc CHSIDE + [2:2] + read-only + + + UDR + desc UDR + [3:3] + read-only + + + CRCERR + desc CRCERR + [4:4] + + + MODF + desc MODF + [5:5] + read-only + + + OVR + desc OVR + [6:6] + read-only + + + BSY + desc BSY + [7:7] + read-only + + + FRLVL + desc FRLVL + [10:9] + read-only + + + FTLVL + desc FTLVL + [12:11] + read-only + + + + + DR + desc DR + 0xC + + + DR + desc DR + [15:0] + + + + + CRCPR + desc CRCPR + 0x10 + 0x7 + + + CRCPOLY + desc CRCPOLY + [15:0] + + + + + RXCRCR + desc RXCRCR + 0x14 + read-only + + + RXCRC + desc RXCRC + [15:0] + read-only + + + + + TXCRCR + desc TXCRCR + 0x18 + read-only + + + TXCRC + desc TXCRC + [15:0] + read-only + + + + + I2SCFGR + desc I2SCFGR + 0x1C + + + CHLEN + desc CHLEN + [0:0] + + + DATLEN + desc DATLEN + [2:1] + + + CKPOL + desc CKPOL + [3:3] + + + I2SSTD + desc I2SSTD + [5:4] + + + PCMSYNC + desc PCMSYNC + [7:7] + + + I2SCFG + desc I2SCFG + [9:8] + + + I2SE + desc I2SE + [10:10] + + + I2SMOD + desc I2SMOD + [11:11] + + + + + I2SPR + desc I2SPR + 0x20 + 0x2 + + + I2SDIV + desc I2SDIV + [7:0] + + + ODD + desc ODD + [8:8] + + + MCKOE + desc MCKOE + [9:9] + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global Interrupt + 26 + + + + SYSCFG + desc SYSCFG + SYSCFG + 0x40010000 + + 0x0 + 0x200 + registers + + + + CFGR1 + desc CFGR1 + 0x0 + 0xFF0000 + + + MEM_MODE + desc MEM_MODE + [1:0] + + + TIM1_IC1_SRC + desc TIM1_IC1_SRC + [3:2] + + + TIM2_IC4_SRC + desc TIM2_IC4_SRC + [5:4] + + + TIM3_IC1_SRC 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OC2PE + desc OC2PE + [11:11] + + + OC2M + desc OC2M + [14:12] + + + OC2CE + desc OC2CE + [15:15] + + + + + CCMR1_INPUT + desc CCMR1:INPUT + CCMR1_OUTPUT + 0x18 + 0xFFFF + + + CC1S + desc CC1S + [1:0] + + + IC1PSC + desc IC1PSC + [3:2] + + + IC1F + desc IC1F + [7:4] + + + CC2S + desc CC2S + [9:8] + + + IC2PSC + desc IC2PSC + [11:10] + + + IC2F + desc IC2F + [15:12] + + + + + CCER + desc CCER + 0x20 + 0x3333 + + + CC1E + desc CC1E + [0:0] + + + CC1P + desc CC1P + [1:1] + + + CC2E + desc CC2E + [4:4] + + + CC2P + desc CC2P + [5:5] + + + CC3E + desc CC3E + [8:8] + + + CC3P + desc CC3P + [9:9] + + + CC4E + desc CC4E + [12:12] + + + CC4P + desc CC4P + [13:13] + + + + + CNT + desc CNT + 0x24 + 0xFFFF + + + CNT + desc CNT + [15:0] + + + + + PSC + desc PSC + 0x28 + 0xFFFF + + + PSC + desc PSC + [15:0] + + + + + ARR + desc ARR + 0x2C + 0xFFFF + 0xFFFF + + + ARR + desc ARR + [15:0] + + + + + RCR + desc RCR + 0x30 + 0xFFFF + 0xFFFF + + + REP + desc REP + [7:0] + + + + + CCR1 + desc CCR1 + 0x34 + 0xFFFF + + + CCR1 + desc CCR1 + [15:0] + + + + + BDTR + desc BDTR + 0x44 + 0xFFFF + + + DTG + desc DTG + [7:0] + + + LOCK + desc LOCK + [9:8] + + + OSSI + desc OSSI + [10:10] + + + OSSR + desc OSSR + [11:11] + + + BKE + desc BKE + [12:12] + + + BKP + desc BKP + [13:13] + + + AOE + desc AOE + [14:14] + + + MOE + desc MOE + [15:15] + + + + + DCR + desc DCR + 0x48 + 0x1F1F + + + DBA + desc DBA + [4:0] + + + DBL + desc DBL + [12:8] + + + + + DMAR + desc DMAR + 0x4C + 0xFFFF + + + DMAB + desc DMAB + [15:0] + + + + + + + TIM17 + 0x40014800 + + TIM17 + TIM17 global Interrupt + 22 + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global Interrupt + 27 + + + + SR + desc SR + 0x0 + 0xC0 + + + PE + desc PE + [0:0] + read-only + + + FE + desc FE + [1:1] + read-only + + + NE + desc NE + [2:2] + read-only + + + ORE + desc ORE + [3:3] + read-only + + + IDLE + desc IDLE + [4:4] + read-only + + + RXNE + desc RXNE + [5:5] + + + TC + desc TC + [6:6] + + + TXE + desc TXE + [7:7] + read-only + + + LBD + desc LBD + [8:8] + + + CTS + desc CTS + [9:9] + + + ABRF + desc ABRF + [10:10] + read-only + + + ABRE + desc ABRE + [11:11] + read-only + + + ABRRQ + desc ABRRQ + [12:12] + write-only + + + + + DR + desc DR + 0x4 + + + DR + desc DR + [8:0] + + + + + BRR + desc BRR + 0x8 + + + DIV_FRACTION + desc DIV_Fraction + [3:0] + + + DIV_MANTISSA + desc DIV_Mantissa + [15:4] + + + + + CR1 + desc CR1 + 0xC + + + SBK + desc SBK + [0:0] + + + RWU + desc RWU + [1:1] + + + RE + desc RE + [2:2] + + + TE + desc TE + [3:3] + + + IDLEIE + desc IDLEIE + [4:4] + + + RXNEIE + desc RXNEIE + [5:5] + + + TCIE + desc TCIE + [6:6] + + + TXEIE + desc TXEIE + [7:7] + + + PEIE + desc PEIE + [8:8] + + + PS + desc PS + [9:9] + + + PCE + desc PCE + [10:10] + + + WAKE + desc WAKE + [11:11] + + + M + desc M + [12:12] + + + UE + desc UE + [13:13] + + + + + CR2 + desc CR2 + 0x10 + + + ADD + desc ADD + [3:0] + + + LBDL + desc LBDL + [5:5] + + + LBDIE + desc LBDIE + [6:6] + + + LBCL + desc LBCL + [8:8] + + + CPHA + desc CPHA + [9:9] + + + CPOL + desc CPOL + [10:10] + + + CLKEN + desc CLKEN + [11:11] + + + STOP + desc STOP + [13:12] + + + LINEN + desc LINEN + [14:14] + + + + + CR3 + desc CR3 + 0x14 + + + EIE + desc EIE + [0:0] + + + IREN + desc IREN + [1:1] + + + IRLP + desc IRLP + [2:2] + + + HDSEL + desc HDSEL + [3:3] + + + NACK + desc NACK + [4:4] + + + SCEN + desc SCEN + [5:5] + + + DMAR + desc DMAR + [6:6] + + + DMAT + desc DMAT + [7:7] + + + RTSE + desc RTSE + [8:8] + + + CTSE + desc CTSE + [9:9] + + + CTSIE + desc CTSIE + [10:10] + + + OVER8 + desc OVER8 + [11:11] + + + ABREN + desc ABREN + [12:12] + + + ABRMODE + desc ABRMODE + [14:13] + + + + + GTPR + desc GTPR + 0x18 + + + PSC + desc PSC + [7:0] + + + GT + desc GT + [15:8] + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global Interrupt + 28 + + + + USART3 + desc USART + USART + 0x40004800 + + 0x0 + 0x400 + registers + + + USART3_4 + USART3, 4 global Interrupts + 29 + + + + USART4 + desc USART + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + USART3_4 + USART3, 4 global Interrupts + 29 + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window WatchDog Interrupt + 0 + + + + CR + CR + Control register (WWDG_CR) + 0x0 + 0x7F + + + T + 7-bit counter (MSB to LSB) + [6:0] + + + WDGA + Activation bit + [7:7] + + + + + CFR + CFR + Configuration register (WWDG_CFR) + 0x4 + 0x7F + + + W + 7-bit window value + [6:0] + + + WDGTB + Timer Base + [8:7] + + + EWI + Early Wakeup Interrupt + [9:9] + + + + + SR + SR + Status register (WWDG_SR) + 0x8 + + + EWIF + Early Wakeup Interrupt flag + [0:0] + + + + + + + \ No newline at end of file