From 322f2dfca57da908b8b72e37cebb3232185f3270 Mon Sep 17 00:00:00 2001 From: Greg Green Date: Sun, 27 Oct 2024 19:19:24 -0700 Subject: [PATCH 1/2] Added DMA channel clustering --- devices/common_patches/dma_cluster.yaml | 14 ++++++++++++++ devices/common_patches/isr_array.yaml | 21 +++++++++++++++++++++ devices/py32f003.yaml | 4 ++++ devices/py32f030.yaml | 4 ++++ 4 files changed, 43 insertions(+) create mode 100644 devices/common_patches/dma_cluster.yaml create mode 100644 devices/common_patches/isr_array.yaml diff --git a/devices/common_patches/dma_cluster.yaml b/devices/common_patches/dma_cluster.yaml new file mode 100644 index 0000000..cf77f60 --- /dev/null +++ b/devices/common_patches/dma_cluster.yaml @@ -0,0 +1,14 @@ + _cluster: + "CH%s": + description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" + "CCR?": + name: CR + "CNDTR?": + name: NDTR + "CPAR?": + name: PAR + "CMAR?": + name: MAR + + _include: + - isr_array.yaml diff --git a/devices/common_patches/isr_array.yaml b/devices/common_patches/isr_array.yaml new file mode 100644 index 0000000..0da24ce --- /dev/null +++ b/devices/common_patches/isr_array.yaml @@ -0,0 +1,21 @@ +ISR: + _array: + "TEIF*": + description: Channel %s Transfer Error flag + "HTIF*": + description: Channel %s Half Transfer Complete flag + "TCIF*": + description: Channel %s Transfer Complete flag + "GIF*": + description: Channel %s Global interrupt flag + +IFCR: + _array: + "CTEIF*": + description: Channel %s Transfer Error clear + "CHTIF*": + description: Channel %s Half Transfer clear + "CTCIF*": + description: Channel %s Transfer Complete clear + "CGIF*": + description: Channel %s Global interrupt clear diff --git a/devices/py32f003.yaml b/devices/py32f003.yaml index fc00698..ccf9765 100644 --- a/devices/py32f003.yaml +++ b/devices/py32f003.yaml @@ -8,6 +8,10 @@ _svd: ../svd/py32f003.svd _include: - common_patches/usart_dr8.yaml +"DMA, DMA[12]": + _include: + - common_patches/dma_cluster.yaml + _include: - ../peripherals/flash/flash_f0.yaml - ../peripherals/pwr/pwr_f0.yaml diff --git a/devices/py32f030.yaml b/devices/py32f030.yaml index 0b6f54a..01a34b1 100644 --- a/devices/py32f030.yaml +++ b/devices/py32f030.yaml @@ -8,6 +8,10 @@ _svd: ../svd/py32f030.svd _include: - common_patches/usart_dr8.yaml +"DMA, DMA[12]": + _include: + - common_patches/dma_cluster.yaml + _include: - ../peripherals/flash/flash_f0.yaml - ../peripherals/pwr/pwr_f0.yaml From 37ff174ebcd6b7212d2bd01b05ad70b500813cc8 Mon Sep 17 00:00:00 2001 From: Greg Green Date: Tue, 19 Nov 2024 10:37:36 -0800 Subject: [PATCH 2/2] Fixed bitfield typo in SPI cr2 register for py32f002b --- devices/common_patches/spi_f002b.yaml | 6 ++++++ devices/py32f002b.yaml | 1 + 2 files changed, 7 insertions(+) create mode 100644 devices/common_patches/spi_f002b.yaml diff --git a/devices/common_patches/spi_f002b.yaml b/devices/common_patches/spi_f002b.yaml new file mode 100644 index 0000000..f5630e9 --- /dev/null +++ b/devices/common_patches/spi_f002b.yaml @@ -0,0 +1,6 @@ +# Rename DDF field in CR1 to DFF to match datasheet +CR1: + _modify: + DDF: + name: DFF + description: desc DFF diff --git a/devices/py32f002b.yaml b/devices/py32f002b.yaml index 4e93840..542f877 100644 --- a/devices/py32f002b.yaml +++ b/devices/py32f002b.yaml @@ -3,6 +3,7 @@ _svd: ../svd/py32f002b.svd "SPI*": _include: - common_patches/spi_dr8.yaml + - common_patches/spi_f002b.yaml "USART*": _include: