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Add a basic SystemVerilog unit test #1452

Merged
merged 2 commits into from
May 18, 2020
Merged

Add a basic SystemVerilog unit test #1452

merged 2 commits into from
May 18, 2020

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cjdrake
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@cjdrake cjdrake commented May 17, 2020

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Calling it a "complete fragment" didn't make much sense.
@Anteru Anteru merged commit 3b18441 into pygments:master May 18, 2020
@Anteru Anteru self-assigned this May 18, 2020
@Anteru Anteru added the changelog-update Items which need to get mentioned in the changelog label May 18, 2020
@Anteru Anteru added this to the 2.7 milestone May 18, 2020
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Anteru commented May 18, 2020

Thanks, merged for the next release!

@Anteru Anteru removed the changelog-update Items which need to get mentioned in the changelog label May 22, 2020
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2 participants