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Fix a few SystemVerilog type keywords #1454

Merged
merged 2 commits into from May 22, 2020
Merged

Fix a few SystemVerilog type keywords #1454

merged 2 commits into from May 22, 2020

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cjdrake
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@cjdrake cjdrake commented May 18, 2020

First, add a few missing type keywords:
chandle, const, event, string, time, type, var, void

These are most of the 'variable' types listed in 1800-2017 6.8
"Variable declarations".

Currently, this 'Keyword.Type' is not taking effect because the lexer is
finding these keywords in the 'Keyword' list above.
Remove the double declaration so we get the more specific token type.

First, add a few missing type keywords:
chandle, const, event, string, time, type, var, void

These are most of the 'variable' types listed in 1800-2017 6.8
"Variable declarations".

Currently, this 'Keyword.Type' is not taking effect because the lexer is
finding these keywords in the 'Keyword' list above.
Remove the double declaration so we get the more specific token type.
This is what the C/C++ lexer does, so it seems legit.
@Anteru Anteru self-assigned this May 18, 2020
@Anteru Anteru merged commit d4c5d60 into pygments:master May 22, 2020
@Anteru Anteru added this to the 2.7 milestone May 22, 2020
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2 participants