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Improve SystemVerilog class/endclass lexer rules #1471

Merged
merged 1 commit into from
Jun 6, 2020
Merged

Improve SystemVerilog class/endclass lexer rules #1471

merged 1 commit into from
Jun 6, 2020

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cjdrake
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@cjdrake cjdrake commented Jun 2, 2020

The class looks like:

class class_identifier [#(param_decls)] [extends class_identifier #(params)];
...
endclass [: class_identifier]

Using the same Java convention of Keyword.Declaration and Name.Class.

Add a test_systemverilog_classes unit test to test_hdl.

The class looks like:

class class_identifier [#(param_decls)] [extends class_identifier #(params)];
    ...
endclass [: class_identifier]

Using the same Java convention of Keyword.Declaration and Name.Class.

Add a test_systemverilog_classes unit test to test_hdl.
@Anteru Anteru added this to the 2.7 milestone Jun 6, 2020
@Anteru Anteru added the changelog-update Items which need to get mentioned in the changelog label Jun 6, 2020
@Anteru Anteru self-assigned this Jun 6, 2020
@Anteru Anteru merged commit 16bd346 into pygments:master Jun 6, 2020
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Anteru commented Jun 6, 2020

Thanks a lot for your continued contribution! Please keep up the good work :)

@Anteru Anteru removed the changelog-update Items which need to get mentioned in the changelog label Sep 8, 2020
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2 participants