From 782338d184f0e1f3f8ba93d005b665024dff8946 Mon Sep 17 00:00:00 2001
From: lvyinrun <lvyinrun@xiaomi.com>
Date: Wed, 26 Nov 2025 14:00:35 +0800
Subject: [PATCH] QNN Backend: Enable QualComm SM8850 targets #15986

Add SM8850 for QualComm Snapdragon 8 Elite Gen 5.
---
 backends/qualcomm/README.md                          | 1 +
 backends/qualcomm/serialization/qc_compiler_spec.fbs | 1 +
 backends/qualcomm/serialization/qc_schema.py         | 2 ++
 backends/qualcomm/utils/utils.py                     | 3 +++
 4 files changed, 7 insertions(+)

diff --git a/backends/qualcomm/README.md b/backends/qualcomm/README.md
index fa82c38b2fd..48867ade607 100644
--- a/backends/qualcomm/README.md
+++ b/backends/qualcomm/README.md
@@ -21,6 +21,7 @@ Please check `generate_qnn_executorch_compiler_spec()` in
 - Snapdragon 8 Gen 2
 - Snapdragon 8 Gen 3
 - Snapdragon 8 Elite
+- Snapdragon 8 Elite Gen 5
 - SA8295
 - SA8255
 - SSG2115P
diff --git a/backends/qualcomm/serialization/qc_compiler_spec.fbs b/backends/qualcomm/serialization/qc_compiler_spec.fbs
index 85affe3464d..b8f456da346 100644
--- a/backends/qualcomm/serialization/qc_compiler_spec.fbs
+++ b/backends/qualcomm/serialization/qc_compiler_spec.fbs
@@ -40,6 +40,7 @@ enum QcomChipset: int {
   SM8550 = 43,
   SM8650 = 57,
   SM8750 = 69,
+  SM8850 = 87,
   SSG2115P = 46,
   SSG2125P = 58,
   SXR1230P = 45,
diff --git a/backends/qualcomm/serialization/qc_schema.py b/backends/qualcomm/serialization/qc_schema.py
index c188c555c41..69b94da6ef0 100644
--- a/backends/qualcomm/serialization/qc_schema.py
+++ b/backends/qualcomm/serialization/qc_schema.py
@@ -46,6 +46,7 @@ class QcomChipset(IntEnum):
     SM8550 = 43  # v73
     SM8650 = 57  # v75
     SM8750 = 69  # v79
+    SM8850 = 87  # v81
     SSG2115P = 46  # v73
     SSG2125P = 58  # v73
     SXR1230P = 45  # v73
@@ -71,6 +72,7 @@ class SocInfo:
     QcomChipset.SA8255: SocInfo(QcomChipset.SA8255, HtpInfo(HtpArch.V73, 8)),
     QcomChipset.SM8650: SocInfo(QcomChipset.SM8650, HtpInfo(HtpArch.V75, 8)),
     QcomChipset.SM8750: SocInfo(QcomChipset.SM8750, HtpInfo(HtpArch.V79, 8)),
+    QcomChipset.SM8850: SocInfo(QcomChipset.SM8850, HtpInfo(HtpArch.V81, 8)),
     QcomChipset.SSG2115P: SocInfo(QcomChipset.SSG2115P, HtpInfo(HtpArch.V73, 2)),
     QcomChipset.SSG2125P: SocInfo(QcomChipset.SSG2125P, HtpInfo(HtpArch.V73, 2)),
     QcomChipset.SXR1230P: SocInfo(QcomChipset.SXR1230P, HtpInfo(HtpArch.V73, 2)),
diff --git a/backends/qualcomm/utils/utils.py b/backends/qualcomm/utils/utils.py
index 20a1d3c0f72..423f87a2597 100644
--- a/backends/qualcomm/utils/utils.py
+++ b/backends/qualcomm/utils/utils.py
@@ -1002,6 +1002,7 @@ def generate_qnn_executorch_compiler_spec(
             SM8550(Snapdragon 8 Gen 2)
             SM8650(Snapdragon 8 Gen 3)
             SM8750(Snapdragon 8 Elite)
+            SM8850(Snapdragon 8 Elite Gen 5)
         backend_options: Options required by different backends.
         debug: Enable verbose logging. Disclaimer: this option must change in
             the near future.
@@ -1097,6 +1098,7 @@ def get_soc_to_arch_map():
         "SA8255": HtpArch.V73,
         "SM8650": HtpArch.V75,
         "SM8750": HtpArch.V79,
+        "SM8850": HtpArch.V81,
         "SSG2115P": HtpArch.V73,
         "SSG2125P": HtpArch.V73,
         "SXR1230P": HtpArch.V73,
@@ -1117,6 +1119,7 @@ def get_soc_to_chipset_map():
         "SA8255": QcomChipset.SA8255,
         "SM8650": QcomChipset.SM8650,
         "SM8750": QcomChipset.SM8750,
+        "SM8850": QcomChipset.SM8850,
         "SSG2115P": QcomChipset.SSG2115P,
         "SSG2125P": QcomChipset.SSG2125P,
         "SXR1230P": QcomChipset.SXR1230P,