diff --git a/backends/arm/third-party/ethos-u-core-driver b/backends/arm/third-party/ethos-u-core-driver
index 90f9df900ac..78df0006c5f 160000
--- a/backends/arm/third-party/ethos-u-core-driver
+++ b/backends/arm/third-party/ethos-u-core-driver
@@ -1 +1 @@
-Subproject commit 90f9df900acdc0718ecd2dfdc53780664758dec5
+Subproject commit 78df0006c5fa667150d3ee35db7bde1d3f6f58c7
diff --git a/examples/arm/executor_runner/arm_perf_monitor.cpp b/examples/arm/executor_runner/arm_perf_monitor.cpp
index 323010bfd71..b75e510d9dd 100644
--- a/examples/arm/executor_runner/arm_perf_monitor.cpp
+++ b/examples/arm/executor_runner/arm_perf_monitor.cpp
@@ -24,7 +24,14 @@ static std::vector<uint64_t> ethosu_pmuEventCounts(
     ETHOSU_PMU_Get_NumEventCounters(),
     0);
 
+#if defined(ETHOSU55) || defined(ETHOSU65)
 static const uint32_t ethosu_pmuCountersUsed = 4;
+#elif defined(ETHOSU85)
+static const uint32_t ethosu_pmuCountersUsed = 5;
+#else
+#error No NPU target defined
+#endif
+
 // ethosu_pmuCountersUsed should match numbers of counters setup in
 // ethosu_inference_begin() and not be more then the HW supports
 static_assert(ETHOSU_PMU_NCOUNTERS >= ethosu_pmuCountersUsed);
@@ -44,18 +51,26 @@ void ethosu_inference_begin(struct ethosu_driver* drv, void*) {
   ETHOSU_PMU_Set_EVTYPER(drv, 1, ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED);
   ETHOSU_PMU_Set_EVTYPER(drv, 2, ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN);
   ETHOSU_PMU_Set_EVTYPER(drv, 3, ETHOSU_PMU_NPU_IDLE);
+  // Enable the 4 counters
+  ETHOSU_PMU_CNTR_Enable(
+      drv,
+      ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CNT2_Msk | ETHOSU_PMU_CNT3_Msk |
+          ETHOSU_PMU_CNT4_Msk);
 #elif defined(ETHOSU85)
-  ETHOSU_PMU_Set_EVTYPER(drv, 0, ETHOSU_PMU_EXT0_RD_DATA_BEAT_RECEIVED);
-  ETHOSU_PMU_Set_EVTYPER(drv, 1, ETHOSU_PMU_EXT1_RD_DATA_BEAT_RECEIVED);
-  ETHOSU_PMU_Set_EVTYPER(drv, 2, ETHOSU_PMU_EXT0_WR_DATA_BEAT_WRITTEN);
-  ETHOSU_PMU_Set_EVTYPER(drv, 3, ETHOSU_PMU_NPU_IDLE);
+  ETHOSU_PMU_Set_EVTYPER(drv, 0, ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED);
+  ETHOSU_PMU_Set_EVTYPER(drv, 1, ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN);
+  ETHOSU_PMU_Set_EVTYPER(drv, 2, ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED);
+  ETHOSU_PMU_Set_EVTYPER(drv, 3, ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN);
+  ETHOSU_PMU_Set_EVTYPER(drv, 4, ETHOSU_PMU_NPU_IDLE);
+  // Enable the 5 counters
+  ETHOSU_PMU_CNTR_Enable(
+      drv,
+      ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CNT2_Msk | ETHOSU_PMU_CNT3_Msk |
+          ETHOSU_PMU_CNT4_Msk | ETHOSU_PMU_CNT5_Msk);
 #else
 #error No NPU target defined
 #endif
 
-  // Enable 4 counters
-  ETHOSU_PMU_CNTR_Enable(drv, 0xf);
-
   ETHOSU_PMU_CNTR_Enable(drv, ETHOSU_PMU_CCNT_Msk);
   ETHOSU_PMU_CYCCNT_Reset(drv);
 
@@ -177,7 +192,7 @@ void StopMeasurements() {
 #elif defined(ETHOSU85)
   ET_LOG(
       Info,
-      "Ethos-U PMU Events:[ETHOSU_PMU_EXT0_RD_DATA_BEAT_RECEIVED, ETHOSU_PMU_EXT1_RD_DATA_BEAT_RECEIVED, ETHOSU_PMU_EXT0_WR_DATA_BEAT_WRITTEN, ETHOSU_PMU_NPU_IDLE]");
+      "Ethos-U PMU Events:[ETHOSU_PMU_SRAM_RD_DATA_BEAT_RECEIVED, ETHOSU_PMU_SRAM_WR_DATA_BEAT_WRITTEN, ETHOSU_PMU_EXT_RD_DATA_BEAT_RECEIVED, ETHOSU_PMU_EXT_WR_DATA_BEAT_WRITTEN, ETHOSU_PMU_NPU_IDLE]");
 #else
 #error No NPU target defined
 #endif