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Merge tag 'pull-request-2023-12-04' of https://gitlab.com/thuth/qemu … 
…into staging

* Fix wording in iotest 149
* Fix whitespace issues in sh4 code (ignore checkpatch.pl warnings here)
* Make sure to check return values in qtests

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# gpg: Signature made Mon 04 Dec 2023 09:23:56 EST
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2023-12-04' of https://gitlab.com/thuth/qemu:
  tests/qtest: check the return value
  sh4: Coding style: Remove tabs
  tests/qemu-iotests/149: Use more inclusive language in this test

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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Stefan Hajnoczi committed Dec 4, 2023
2 parents 1664d74 + 4d98618 commit 169c4e7
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Showing 10 changed files with 1,045 additions and 1,039 deletions.
204 changes: 102 additions & 102 deletions linux-user/sh4/termbits.h
View file
Expand Up @@ -39,86 +39,86 @@ struct target_termios {
#define TARGET_VEOL2 16

/* c_iflag bits */
#define TARGET_IGNBRK 0000001
#define TARGET_BRKINT 0000002
#define TARGET_IGNPAR 0000004
#define TARGET_PARMRK 0000010
#define TARGET_INPCK 0000020
#define TARGET_ISTRIP 0000040
#define TARGET_INLCR 0000100
#define TARGET_IGNCR 0000200
#define TARGET_ICRNL 0000400
#define TARGET_IUCLC 0001000
#define TARGET_IXON 0002000
#define TARGET_IXANY 0004000
#define TARGET_IXOFF 0010000
#define TARGET_IMAXBEL 0020000
#define TARGET_IUTF8 0040000
#define TARGET_IGNBRK 0000001
#define TARGET_BRKINT 0000002
#define TARGET_IGNPAR 0000004
#define TARGET_PARMRK 0000010
#define TARGET_INPCK 0000020
#define TARGET_ISTRIP 0000040
#define TARGET_INLCR 0000100
#define TARGET_IGNCR 0000200
#define TARGET_ICRNL 0000400
#define TARGET_IUCLC 0001000
#define TARGET_IXON 0002000
#define TARGET_IXANY 0004000
#define TARGET_IXOFF 0010000
#define TARGET_IMAXBEL 0020000
#define TARGET_IUTF8 0040000

/* c_oflag bits */
#define TARGET_OPOST 0000001
#define TARGET_OLCUC 0000002
#define TARGET_ONLCR 0000004
#define TARGET_OCRNL 0000010
#define TARGET_ONOCR 0000020
#define TARGET_ONLRET 0000040
#define TARGET_OFILL 0000100
#define TARGET_OFDEL 0000200
#define TARGET_NLDLY 0000400
#define TARGET_NL0 0000000
#define TARGET_NL1 0000400
#define TARGET_CRDLY 0003000
#define TARGET_CR0 0000000
#define TARGET_CR1 0001000
#define TARGET_CR2 0002000
#define TARGET_CR3 0003000
#define TARGET_TABDLY 0014000
#define TARGET_TAB0 0000000
#define TARGET_TAB1 0004000
#define TARGET_TAB2 0010000
#define TARGET_TAB3 0014000
#define TARGET_XTABS 0014000
#define TARGET_BSDLY 0020000
#define TARGET_BS0 0000000
#define TARGET_BS1 0020000
#define TARGET_VTDLY 0040000
#define TARGET_VT0 0000000
#define TARGET_VT1 0040000
#define TARGET_FFDLY 0100000
#define TARGET_FF0 0000000
#define TARGET_FF1 0100000
#define TARGET_OPOST 0000001
#define TARGET_OLCUC 0000002
#define TARGET_ONLCR 0000004
#define TARGET_OCRNL 0000010
#define TARGET_ONOCR 0000020
#define TARGET_ONLRET 0000040
#define TARGET_OFILL 0000100
#define TARGET_OFDEL 0000200
#define TARGET_NLDLY 0000400
#define TARGET_NL0 0000000
#define TARGET_NL1 0000400
#define TARGET_CRDLY 0003000
#define TARGET_CR0 0000000
#define TARGET_CR1 0001000
#define TARGET_CR2 0002000
#define TARGET_CR3 0003000
#define TARGET_TABDLY 0014000
#define TARGET_TAB0 0000000
#define TARGET_TAB1 0004000
#define TARGET_TAB2 0010000
#define TARGET_TAB3 0014000
#define TARGET_XTABS 0014000
#define TARGET_BSDLY 0020000
#define TARGET_BS0 0000000
#define TARGET_BS1 0020000
#define TARGET_VTDLY 0040000
#define TARGET_VT0 0000000
#define TARGET_VT1 0040000
#define TARGET_FFDLY 0100000
#define TARGET_FF0 0000000
#define TARGET_FF1 0100000

/* c_cflag bit meaning */
#define TARGET_CBAUD 0010017
#define TARGET_B0 0000000 /* hang up */
#define TARGET_B50 0000001
#define TARGET_B75 0000002
#define TARGET_B110 0000003
#define TARGET_B134 0000004
#define TARGET_B150 0000005
#define TARGET_B200 0000006
#define TARGET_B300 0000007
#define TARGET_B600 0000010
#define TARGET_B1200 0000011
#define TARGET_B1800 0000012
#define TARGET_B2400 0000013
#define TARGET_B4800 0000014
#define TARGET_B9600 0000015
#define TARGET_B19200 0000016
#define TARGET_B38400 0000017
#define TARGET_CBAUD 0010017
#define TARGET_B0 0000000 /* hang up */
#define TARGET_B50 0000001
#define TARGET_B75 0000002
#define TARGET_B110 0000003
#define TARGET_B134 0000004
#define TARGET_B150 0000005
#define TARGET_B200 0000006
#define TARGET_B300 0000007
#define TARGET_B600 0000010
#define TARGET_B1200 0000011
#define TARGET_B1800 0000012
#define TARGET_B2400 0000013
#define TARGET_B4800 0000014
#define TARGET_B9600 0000015
#define TARGET_B19200 0000016
#define TARGET_B38400 0000017
#define TARGET_EXTA B19200
#define TARGET_EXTB B38400
#define TARGET_CSIZE 0000060
#define TARGET_CS5 0000000
#define TARGET_CS6 0000020
#define TARGET_CS7 0000040
#define TARGET_CS8 0000060
#define TARGET_CSTOPB 0000100
#define TARGET_CREAD 0000200
#define TARGET_PARENB 0000400
#define TARGET_PARODD 0001000
#define TARGET_HUPCL 0002000
#define TARGET_CLOCAL 0004000
#define TARGET_CSIZE 0000060
#define TARGET_CS5 0000000
#define TARGET_CS6 0000020
#define TARGET_CS7 0000040
#define TARGET_CS8 0000060
#define TARGET_CSTOPB 0000100
#define TARGET_CREAD 0000200
#define TARGET_PARENB 0000400
#define TARGET_PARODD 0001000
#define TARGET_HUPCL 0002000
#define TARGET_CLOCAL 0004000
#define TARGET_CBAUDEX 0010000
#define TARGET_B57600 0010001
#define TARGET_B115200 0010002
Expand All @@ -135,44 +135,44 @@ struct target_termios {
#define TARGET_B3000000 0010015
#define TARGET_B3500000 0010016
#define TARGET_B4000000 0010017
#define TARGET_CIBAUD 002003600000 /* input baud rate (not used) */
#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */
#define TARGET_CRTSCTS 020000000000 /* flow control */
#define TARGET_CIBAUD 002003600000 /* input baud rate (not used) */
#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */
#define TARGET_CRTSCTS 020000000000 /* flow control */

/* c_lflag bits */
#define TARGET_ISIG 0000001
#define TARGET_ICANON 0000002
#define TARGET_XCASE 0000004
#define TARGET_ECHO 0000010
#define TARGET_ECHOE 0000020
#define TARGET_ECHOK 0000040
#define TARGET_ECHONL 0000100
#define TARGET_NOFLSH 0000200
#define TARGET_TOSTOP 0000400
#define TARGET_ECHOCTL 0001000
#define TARGET_ECHOPRT 0002000
#define TARGET_ECHOKE 0004000
#define TARGET_FLUSHO 0010000
#define TARGET_PENDIN 0040000
#define TARGET_IEXTEN 0100000
#define TARGET_ISIG 0000001
#define TARGET_ICANON 0000002
#define TARGET_XCASE 0000004
#define TARGET_ECHO 0000010
#define TARGET_ECHOE 0000020
#define TARGET_ECHOK 0000040
#define TARGET_ECHONL 0000100
#define TARGET_NOFLSH 0000200
#define TARGET_TOSTOP 0000400
#define TARGET_ECHOCTL 0001000
#define TARGET_ECHOPRT 0002000
#define TARGET_ECHOKE 0004000
#define TARGET_FLUSHO 0010000
#define TARGET_PENDIN 0040000
#define TARGET_IEXTEN 0100000
#define TARGET_EXTPROC 0200000


/* tcflow() and TCXONC use these */
#define TARGET_TCOOFF 0
#define TARGET_TCOON 1
#define TARGET_TCIOFF 2
#define TARGET_TCION 3
#define TARGET_TCOOFF 0
#define TARGET_TCOON 1
#define TARGET_TCIOFF 2
#define TARGET_TCION 3

/* tcflush() and TCFLSH use these */
#define TARGET_TCIFLUSH 0
#define TARGET_TCOFLUSH 1
#define TARGET_TCIOFLUSH 2
#define TARGET_TCIFLUSH 0
#define TARGET_TCOFLUSH 1
#define TARGET_TCIOFLUSH 2

/* tcsetattr uses these */
#define TARGET_TCSANOW 0
#define TARGET_TCSADRAIN 1
#define TARGET_TARGET_TCSAFLUSH 2
#define TARGET_TCSANOW 0
#define TARGET_TCSADRAIN 1
#define TARGET_TARGET_TCSAFLUSH 2

/* ioctl */
#define TARGET_FIOCLEX TARGET_IO('f', 1)
Expand Down
80 changes: 40 additions & 40 deletions target/sh4/cpu.h
View file
Expand Up @@ -107,19 +107,19 @@
TB_FLAG_GUSA_MASK)

typedef struct tlb_t {
uint32_t vpn; /* virtual page number */
uint32_t ppn; /* physical page number */
uint32_t size; /* mapped page size in bytes */
uint8_t asid; /* address space identifier */
uint8_t v:1; /* validity */
uint8_t sz:2; /* page size */
uint8_t sh:1; /* share status */
uint8_t c:1; /* cacheability */
uint8_t pr:2; /* protection key */
uint8_t d:1; /* dirty */
uint8_t wt:1; /* write through */
uint8_t sa:3; /* space attribute (PCMCIA) */
uint8_t tc:1; /* timing control */
uint32_t vpn; /* virtual page number */
uint32_t ppn; /* physical page number */
uint32_t size; /* mapped page size in bytes */
uint8_t asid; /* address space identifier */
uint8_t v:1; /* validity */
uint8_t sz:2; /* page size */
uint8_t sh:1; /* share status */
uint8_t c:1; /* cacheability */
uint8_t pr:2; /* protection key */
uint8_t d:1; /* dirty */
uint8_t wt:1; /* write through */
uint8_t sa:3; /* space attribute (PCMCIA) */
uint8_t tc:1; /* timing control */
} tlb_t;

#define UTLB_SIZE 64
Expand All @@ -139,44 +139,44 @@ typedef struct memory_content {
} memory_content;

typedef struct CPUArchState {
uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */
float32 fregs[32]; /* floating point registers */
uint32_t flags; /* general execution flags */
uint32_t gregs[24]; /* general registers */
float32 fregs[32]; /* floating point registers */
uint32_t sr; /* status register (with T split out) */
uint32_t sr_m; /* M bit of status register */
uint32_t sr_q; /* Q bit of status register */
uint32_t sr_t; /* T bit of status register */
uint32_t ssr; /* saved status register */
uint32_t spc; /* saved program counter */
uint32_t gbr; /* global base register */
uint32_t vbr; /* vector base register */
uint32_t sgr; /* saved global register 15 */
uint32_t dbr; /* debug base register */
uint32_t pc; /* program counter */
uint32_t ssr; /* saved status register */
uint32_t spc; /* saved program counter */
uint32_t gbr; /* global base register */
uint32_t vbr; /* vector base register */
uint32_t sgr; /* saved global register 15 */
uint32_t dbr; /* debug base register */
uint32_t pc; /* program counter */
uint32_t delayed_pc; /* target of delayed branch */
uint32_t delayed_cond; /* condition of delayed branch */
uint32_t mach; /* multiply and accumulate high */
uint32_t macl; /* multiply and accumulate low */
uint32_t pr; /* procedure register */
uint32_t fpscr; /* floating point status/control register */
uint32_t fpul; /* floating point communication register */
uint32_t mach; /* multiply and accumulate high */
uint32_t macl; /* multiply and accumulate low */
uint32_t pr; /* procedure register */
uint32_t fpscr; /* floating point status/control register */
uint32_t fpul; /* floating point communication register */

/* float point status register */
float_status fp_status;

/* Those belong to the specific unit (SH7750) but are handled here */
uint32_t mmucr; /* MMU control register */
uint32_t pteh; /* page table entry high register */
uint32_t ptel; /* page table entry low register */
uint32_t ptea; /* page table entry assistance register */
uint32_t mmucr; /* MMU control register */
uint32_t pteh; /* page table entry high register */
uint32_t ptel; /* page table entry low register */
uint32_t ptea; /* page table entry assistance register */
uint32_t ttb; /* translation table base register */
uint32_t tea; /* TLB exception address register */
uint32_t tra; /* TRAPA exception register */
uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */
uint32_t tea; /* TLB exception address register */
uint32_t tra; /* TRAPA exception register */
uint32_t expevt; /* exception event register */
uint32_t intevt; /* interrupt event register */

tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
tlb_t utlb[UTLB_SIZE]; /* unified translation table */

/* LDST = LOCK_ADDR != -1. */
uint32_t lock_addr;
Expand All @@ -186,13 +186,13 @@ typedef struct CPUArchState {
struct {} end_reset_fields;

/* Fields from here on are preserved over CPU reset. */
int id; /* CPU model */
int id; /* CPU model */

/* The features that we should emulate. See sh_features above. */
uint32_t features;

void *intc_handle;
int in_sleep; /* SR_BL ignored during sleep */
int in_sleep; /* SR_BL ignored during sleep */
memory_content *movcal_backup;
memory_content **movcal_backup_tail;
} CPUSH4State;
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