From 19e6c50d2d843220efbdd3b2db21d83c122c364a Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Wed, 5 Dec 2012 00:29:10 +0100 Subject: [PATCH] target-mips: Fix incorrect shift for SHILO and SHILOV helper_shilo has not been shifting an accumulator value correctly for negative values in 'shift' field. Minor optimization for shift=0 case. This change also adds tests that will trigger issue and check for regressions. Signed-off-by: Petar Jovanovic Reviewed-by: Richard Henderson Reviewed-by: Eric Johnson Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 17 +++++++++-------- tests/tcg/mips/mips32-dsp/shilo.c | 18 ++++++++++++++++++ tests/tcg/mips/mips32-dsp/shilov.c | 20 ++++++++++++++++++++ 3 files changed, 47 insertions(+), 8 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index fda5f0460bd5..14daf91950b5 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env) rs5_0 = rs & 0x3F; rs5_0 = (int8_t)(rs5_0 << 2) >> 2; - rs5_0 = MIPSDSP_ABS(rs5_0); + + if (unlikely(rs5_0 == 0)) { + return; + } + acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) | ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); - if (rs5_0 == 0) { - temp = acc; + + if (rs5_0 > 0) { + temp = acc >> rs5_0; } else { - if (rs5_0 > 0) { - temp = acc >> rs5_0; - } else { - temp = acc << rs5_0; - } + temp = acc << -rs5_0; } env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32); diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-dsp/shilo.c index b686616d8010..ce8ebc69c2ac 100644 --- a/tests/tcg/mips/mips32-dsp/shilo.c +++ b/tests/tcg/mips/mips32-dsp/shilo.c @@ -23,5 +23,23 @@ int main() assert(ach == resulth); assert(acl == resultl); + + ach = 0x1; + acl = 0x80000000; + + resulth = 0x3; + resultl = 0x0; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilo $ac1, -1\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + ); + assert(ach == resulth); + assert(acl == resultl); + return 0; } diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-dsp/shilov.c index f186032a14c8..e1d6cea4b6de 100644 --- a/tests/tcg/mips/mips32-dsp/shilov.c +++ b/tests/tcg/mips/mips32-dsp/shilov.c @@ -25,5 +25,25 @@ int main() assert(ach == resulth); assert(acl == resultl); + + rs = 0xffffffff; + ach = 0x1; + acl = 0x80000000; + + resulth = 0x3; + resultl = 0x0; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilov $ac1, %2\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs) + ); + assert(ach == resulth); + assert(acl == resultl); + return 0; }