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target/loongarch: Implement vbitsel vset 
This patch includes:
- VBITSEL.V;
- VBITSELI.B;
- VSET{EQZ/NEZ}.V;
- VSETANYEQZ.{B/H/W/D};
- VSETALLNEZ.{B/H/W/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-38-gaosong@loongson.cn>
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@gaosong-loongson
gaosong-loongson committed May 5, 2023
1 parent 46f0ab3 commit 1b9656c
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Showing 5 changed files with 174 additions and 0 deletions.
20 changes: 20 additions & 0 deletions target/loongarch/disas.c
View file
Expand Up @@ -792,6 +792,12 @@ static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
return true; \
}

static void output_cv(DisasContext *ctx, arg_cv *a,
const char *mnemonic)
{
output(ctx, mnemonic, "fcc%d, v%d", a->cd, a->vj);
}

static void output_vvv(DisasContext *ctx, arg_vvv *a, const char *mnemonic)
{
output(ctx, mnemonic, "v%d, v%d, v%d", a->vd, a->vj, a->vk);
Expand Down Expand Up @@ -1541,3 +1547,17 @@ static bool trans_vfcmp_cond_##suffix(DisasContext *ctx, \

LSX_FCMP_INSN(s)
LSX_FCMP_INSN(d)

INSN_LSX(vbitsel_v, vvvv)
INSN_LSX(vbitseli_b, vv_i)

INSN_LSX(vseteqz_v, cv)
INSN_LSX(vsetnez_v, cv)
INSN_LSX(vsetanyeqz_b, cv)
INSN_LSX(vsetanyeqz_h, cv)
INSN_LSX(vsetanyeqz_w, cv)
INSN_LSX(vsetanyeqz_d, cv)
INSN_LSX(vsetallnez_b, cv)
INSN_LSX(vsetallnez_h, cv)
INSN_LSX(vsetallnez_w, cv)
INSN_LSX(vsetallnez_d, cv)
11 changes: 11 additions & 0 deletions target/loongarch/helper.h
View file
Expand Up @@ -642,3 +642,14 @@ DEF_HELPER_5(vfcmp_c_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfcmp_s_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfcmp_c_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfcmp_s_d, void, env, i32, i32, i32, i32)

DEF_HELPER_FLAGS_4(vbitseli_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)

DEF_HELPER_3(vsetanyeqz_b, void, env, i32, i32)
DEF_HELPER_3(vsetanyeqz_h, void, env, i32, i32)
DEF_HELPER_3(vsetanyeqz_w, void, env, i32, i32)
DEF_HELPER_3(vsetanyeqz_d, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_b, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_h, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_w, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_d, void, env, i32, i32)
74 changes: 74 additions & 0 deletions target/loongarch/insn_trans/trans_lsx.c.inc
View file
Expand Up @@ -65,6 +65,17 @@ static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a,
return true;
}

static bool gen_cv(DisasContext *ctx, arg_cv *a,
void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32))
{
TCGv_i32 vj = tcg_constant_i32(a->vj);
TCGv_i32 cd = tcg_constant_i32(a->cd);

CHECK_SXE;
func(cpu_env, cd, vj);
return true;
}

static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t))
Expand Down Expand Up @@ -3749,3 +3760,66 @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a)

return true;
}

static bool trans_vbitsel_v(DisasContext *ctx, arg_vvvv *a)
{
CHECK_SXE;

tcg_gen_gvec_bitsel(MO_64, vec_full_offset(a->vd), vec_full_offset(a->va),
vec_full_offset(a->vk), vec_full_offset(a->vj),
16, ctx->vl/8);
return true;
}

static void gen_vbitseli(unsigned vece, TCGv_vec a, TCGv_vec b, int64_t imm)
{
tcg_gen_bitsel_vec(vece, a, a, tcg_constant_vec_matching(a, vece, imm), b);
}

static bool trans_vbitseli_b(DisasContext *ctx, arg_vv_i *a)
{
static const GVecGen2i op = {
.fniv = gen_vbitseli,
.fnoi = gen_helper_vbitseli_b,
.vece = MO_8,
.load_dest = true
};

CHECK_SXE;

tcg_gen_gvec_2i(vec_full_offset(a->vd), vec_full_offset(a->vj),
16, ctx->vl/8, a->imm, &op);
return true;
}

#define VSET(NAME, COND) \
static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \
{ \
TCGv_i64 t1, al, ah; \
\
al = tcg_temp_new_i64(); \
ah = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
\
get_vreg64(ah, a->vj, 1); \
get_vreg64(al, a->vj, 0); \
\
CHECK_SXE; \
tcg_gen_or_i64(t1, al, ah); \
tcg_gen_setcondi_i64(COND, t1, t1, 0); \
tcg_gen_st8_tl(t1, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7])); \
\
return true; \
}

VSET(vseteqz_v, TCG_COND_EQ)
VSET(vsetnez_v, TCG_COND_NE)

TRANS(vsetanyeqz_b, gen_cv, gen_helper_vsetanyeqz_b)
TRANS(vsetanyeqz_h, gen_cv, gen_helper_vsetanyeqz_h)
TRANS(vsetanyeqz_w, gen_cv, gen_helper_vsetanyeqz_w)
TRANS(vsetanyeqz_d, gen_cv, gen_helper_vsetanyeqz_d)
TRANS(vsetallnez_b, gen_cv, gen_helper_vsetallnez_b)
TRANS(vsetallnez_h, gen_cv, gen_helper_vsetallnez_h)
TRANS(vsetallnez_w, gen_cv, gen_helper_vsetallnez_w)
TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d)
17 changes: 17 additions & 0 deletions target/loongarch/insns.decode
View file
Expand Up @@ -491,6 +491,7 @@ dbcl 0000 00000010 10101 ............... @i15
#

&vv vd vj
&cv cd vj
&vvv vd vj vk
&vv_i vd vj imm
&vvvv vd vj vk va
Expand All @@ -500,6 +501,7 @@ dbcl 0000 00000010 10101 ............... @i15
# LSX Formats
#
@vv .... ........ ..... ..... vj:5 vd:5 &vv
@cv .... ........ ..... ..... vj:5 .. cd:3 &cv
@vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv
@vv_ui3 .... ........ ..... .. imm:3 vj:5 vd:5 &vv_i
@vv_ui4 .... ........ ..... . imm:4 vj:5 vd:5 &vv_i
Expand Down Expand Up @@ -1150,3 +1152,18 @@ vslti_du 0111 00101000 10011 ..... ..... ..... @vv_ui5

vfcmp_cond_s 0000 11000101 ..... ..... ..... ..... @vvv_fcond
vfcmp_cond_d 0000 11000110 ..... ..... ..... ..... @vvv_fcond

vbitsel_v 0000 11010001 ..... ..... ..... ..... @vvvv

vbitseli_b 0111 00111100 01 ........ ..... ..... @vv_ui8

vseteqz_v 0111 00101001 11001 00110 ..... 00 ... @cv
vsetnez_v 0111 00101001 11001 00111 ..... 00 ... @cv
vsetanyeqz_b 0111 00101001 11001 01000 ..... 00 ... @cv
vsetanyeqz_h 0111 00101001 11001 01001 ..... 00 ... @cv
vsetanyeqz_w 0111 00101001 11001 01010 ..... 00 ... @cv
vsetanyeqz_d 0111 00101001 11001 01011 ..... 00 ... @cv
vsetallnez_b 0111 00101001 11001 01100 ..... 00 ... @cv
vsetallnez_h 0111 00101001 11001 01101 ..... 00 ... @cv
vsetallnez_w 0111 00101001 11001 01110 ..... 00 ... @cv
vsetallnez_d 0111 00101001 11001 01111 ..... 00 ... @cv
52 changes: 52 additions & 0 deletions target/loongarch/lsx_helper.c
View file
Expand Up @@ -11,6 +11,7 @@
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
#include "internals.h"
#include "tcg/tcg.h"

#define DO_ADD(a, b) (a + b)
#define DO_SUB(a, b) (a - b)
Expand Down Expand Up @@ -2714,3 +2715,54 @@ VFCMP(vfcmp_c_s, 32, UW, float32_compare_quiet)
VFCMP(vfcmp_s_s, 32, UW, float32_compare)
VFCMP(vfcmp_c_d, 64, UD, float64_compare_quiet)
VFCMP(vfcmp_s_d, 64, UD, float64_compare)

void HELPER(vbitseli_b)(void *vd, void *vj, uint64_t imm, uint32_t v)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;

for (i = 0; i < 16; i++) {
Vd->B(i) = (~Vd->B(i) & Vj->B(i)) | (Vd->B(i) & imm);
}
}

/* Copy from target/arm/tcg/sve_helper.c */
static inline bool do_match2(uint64_t n, uint64_t m0, uint64_t m1, int esz)
{
uint64_t bits = 8 << esz;
uint64_t ones = dup_const(esz, 1);
uint64_t signs = ones << (bits - 1);
uint64_t cmp0, cmp1;

cmp1 = dup_const(esz, n);
cmp0 = cmp1 ^ m0;
cmp1 = cmp1 ^ m1;
cmp0 = (cmp0 - ones) & ~cmp0;
cmp1 = (cmp1 - ones) & ~cmp1;
return (cmp0 | cmp1) & signs;
}

#define SETANYEQZ(NAME, MO) \
void HELPER(NAME)(CPULoongArchState *env, uint32_t cd, uint32_t vj) \
{ \
VReg *Vj = &(env->fpr[vj].vreg); \
\
env->cf[cd & 0x7] = do_match2(0, Vj->D(0), Vj->D(1), MO); \
}
SETANYEQZ(vsetanyeqz_b, MO_8)
SETANYEQZ(vsetanyeqz_h, MO_16)
SETANYEQZ(vsetanyeqz_w, MO_32)
SETANYEQZ(vsetanyeqz_d, MO_64)

#define SETALLNEZ(NAME, MO) \
void HELPER(NAME)(CPULoongArchState *env, uint32_t cd, uint32_t vj) \
{ \
VReg *Vj = &(env->fpr[vj].vreg); \
\
env->cf[cd & 0x7]= !do_match2(0, Vj->D(0), Vj->D(1), MO); \
}
SETALLNEZ(vsetallnez_b, MO_8)
SETALLNEZ(vsetallnez_h, MO_16)
SETALLNEZ(vsetallnez_w, MO_32)
SETALLNEZ(vsetallnez_d, MO_64)

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