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target/riscv: Fix lines with over 80 characters 
Fix lines with over 80 characters for both code and comments.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@alistair23
Weiwei Li authored and alistair23 committed May 5, 2023
1 parent 3b57254 commit 246f879
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Showing 9 changed files with 91 additions and 56 deletions.
3 changes: 2 additions & 1 deletion target/riscv/cpu.c
View file
Expand Up @@ -1700,7 +1700,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, riscv_cpu_properties);
}

static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
int max_str_len)
{
char *old = *isa_str;
char *new = *isa_str;
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4 changes: 2 additions & 2 deletions target/riscv/cpu.h
View file
Expand Up @@ -591,8 +591,8 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr);
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
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3 changes: 2 additions & 1 deletion target/riscv/cpu_helper.c
View file
Expand Up @@ -1121,7 +1121,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
RISCV_EXCP_STORE_PAGE_FAULT :
RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
}
break;
default:
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38 changes: 21 additions & 17 deletions target/riscv/csr.c
View file
Expand Up @@ -1137,7 +1137,8 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP |
SIP_LCOFIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;

const bool valid_vm_1_10_32[16] = {
Expand Down Expand Up @@ -1298,7 +1299,8 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
Int128 *val)
{
*val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
*val = int128_make128(env->mstatus, add_status_sd(MXL_RV128,
env->mstatus));
return RISCV_EXCP_NONE;
}

Expand Down Expand Up @@ -2823,7 +2825,8 @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
{
env->hstatus = val;
if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
qemu_log_mask(LOG_UNIMP,
"QEMU does not support mixed HSXLEN options.");
}
if (get_field(val, HSTATUS_VSBE) != 0) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
Expand Down Expand Up @@ -3490,9 +3493,9 @@ static RISCVException write_mmte(CPURISCVState *env, int csrno,
target_ulong wpri_val = val & MMTE_MASK;

if (val != wpri_val) {
qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
"MMTE: WPRI violation written 0x", val,
"vs expected 0x", wpri_val);
qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x",
val, "vs expected 0x", wpri_val);
}
/* for machine mode pm.current is hardwired to 1 */
wpri_val |= MMTE_M_PM_CURRENT;
Expand Down Expand Up @@ -3521,9 +3524,9 @@ static RISCVException write_smte(CPURISCVState *env, int csrno,
target_ulong wpri_val = val & SMTE_MASK;

if (val != wpri_val) {
qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
"SMTE: WPRI violation written 0x", val,
"vs expected 0x", wpri_val);
qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x",
val, "vs expected 0x", wpri_val);
}

/* if pm.current==0 we can't modify current PM CSRs */
Expand All @@ -3549,9 +3552,9 @@ static RISCVException write_umte(CPURISCVState *env, int csrno,
target_ulong wpri_val = val & UMTE_MASK;

if (val != wpri_val) {
qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
"UMTE: WPRI violation written 0x", val,
"vs expected 0x", wpri_val);
qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x",
val, "vs expected 0x", wpri_val);
}

if (check_pm_current_disabled(env, csrno)) {
Expand Down Expand Up @@ -3941,7 +3944,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
* Fall back to 64-bit version for now, if the 128-bit alternative isn't
* at all defined.
* Note, some CSRs don't need to extend to MXLEN (64 upper bits non
* significant), for those, this fallback is correctly handling the accesses
* significant), for those, this fallback is correctly handling the
* accesses
*/
target_ulong old_value;
ret = riscv_csrrw_do64(env, csrno, &old_value,
Expand Down Expand Up @@ -4154,11 +4158,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {

/* Supervisor Trap Setup */
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus,
NULL, read_sstatus_i128 },
[CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
[CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
NULL, read_sstatus_i128 },
[CSR_SIE] = { "sie", smode, NULL, NULL, rmw_sie },
[CSR_STVEC] = { "stvec", smode, read_stvec, write_stvec },
[CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren,
write_scounteren },
write_scounteren },

/* Supervisor Trap Handling */
[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch,
Expand Down
11 changes: 6 additions & 5 deletions target/riscv/debug.c
View file
Expand Up @@ -282,8 +282,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,
/* validate size encoding */
size = type2_breakpoint_size(env, ctrl);
if (access_size[size] == -1) {
qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
size);
qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
"SIZE_ANY\n", size);
} else {
val |= (ctrl & TYPE2_SIZELO);
if (riscv_cpu_mxl(env) == MXL_RV64) {
Expand Down Expand Up @@ -411,8 +411,8 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
/* validate size encoding */
size = extract32(ctrl, 16, 4);
if (access_size[size] == -1) {
qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
size);
qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using "
"SIZE_ANY\n", size);
} else {
val |= (ctrl & TYPE6_SIZE);
}
Expand Down Expand Up @@ -696,7 +696,8 @@ target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
int trigger_type;
switch (tdata_index) {
case TDATA1:
trigger_type = extract_trigger_type(env, env->tdata1[env->trigger_cur]);
trigger_type = extract_trigger_type(env,
env->tdata1[env->trigger_cur]);
if ((trigger_type == TRIGGER_TYPE_INST_CNT) && icount_enabled()) {
return deposit64(env->tdata1[env->trigger_cur], 10, 14,
itrigger_get_adjust_count(env));
Expand Down
3 changes: 2 additions & 1 deletion target/riscv/gdbstub.c
View file
Expand Up @@ -321,7 +321,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
}
if (env->misa_ext & RVV) {
int base_reg = cs->gdb_num_regs;
gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
riscv_gdb_set_vector,
ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0);
}
Expand Down
6 changes: 4 additions & 2 deletions target/riscv/pmp.c
View file
Expand Up @@ -129,7 +129,8 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
}
}

static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
static void pmp_decode_napot(target_ulong a, target_ulong *sa,
target_ulong *ea)
{
/*
* aaaa...aaa0 8-byte NAPOT range
Expand Down Expand Up @@ -217,7 +218,8 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
pmp_update_rule_nums(env);
}

static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr)
static int pmp_is_in_range(CPURISCVState *env, int pmp_index,
target_ulong addr)
{
int result = 0;

Expand Down
3 changes: 2 additions & 1 deletion target/riscv/pmu.c
View file
Expand Up @@ -419,7 +419,8 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
} else {
return -1;
}
overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_ns;
overflow_at = (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
overflow_ns;

if (overflow_at > INT64_MAX) {
overflow_left += overflow_at - INT64_MAX;
Expand Down

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