Skip to content

Commit

Permalink
Browse files Browse the repository at this point in the history
target/riscv: Enable PC-relative translation 
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
  • Loading branch information
@alistair23
Weiwei Li authored and alistair23 committed Jun 13, 2023
1 parent 227fb82 commit 356c13f
Show file tree
Hide file tree
Showing 4 changed files with 74 additions and 20 deletions.
31 changes: 21 additions & 10 deletions target/riscv/cpu.c
View file
Expand Up @@ -721,16 +721,18 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
if (!(tb_cflags(tb) & CF_PCREL)) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);

tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));

if (xl == MXL_RV32) {
env->pc = (int32_t) tb->pc;
} else {
env->pc = tb->pc;
if (xl == MXL_RV32) {
env->pc = (int32_t) tb->pc;
} else {
env->pc = tb->pc;
}
}
}

Expand All @@ -756,11 +758,18 @@ static void riscv_restore_state_to_opc(CPUState *cs,
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
target_ulong pc;

if (tb_cflags(tb) & CF_PCREL) {
pc = (env->pc & TARGET_PAGE_MASK) | data[0];
} else {
pc = data[0];
}

if (xl == MXL_RV32) {
env->pc = (int32_t)data[0];
env->pc = (int32_t)pc;
} else {
env->pc = data[0];
env->pc = pc;
}
env->bins = data[1];
}
Expand Down Expand Up @@ -1343,6 +1352,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}

#ifndef CONFIG_USER_ONLY
cs->tcg_cflags |= CF_PCREL;

if (cpu->cfg.ext_sstc) {
riscv_timer_init(cpu);
}
Expand Down
12 changes: 10 additions & 2 deletions target/riscv/insn_trans/trans_rvi.c.inc
View file
Expand Up @@ -38,7 +38,9 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)

static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
TCGv target_pc = dest_gpr(ctx, a->rd);
gen_pc_plus_diff(target_pc, ctx, a->imm);
gen_set_gpr(ctx, a->rd, target_pc);
return true;
}

Expand All @@ -52,6 +54,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{
TCGLabel *misaligned = NULL;
TCGv target_pc = tcg_temp_new();
TCGv succ_pc = dest_gpr(ctx, a->rd);

tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2);
Expand All @@ -68,7 +71,9 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
}

gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
gen_set_gpr(ctx, a->rd, succ_pc);

tcg_gen_mov_tl(cpu_pc, target_pc);
lookup_and_goto_ptr(ctx);

Expand Down Expand Up @@ -158,6 +163,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
TCGLabel *l = gen_new_label();
TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
target_ulong orig_pc_save = ctx->pc_save;

if (get_xl(ctx) == MXL_RV128) {
TCGv src1h = get_gprh(ctx, a->rs1);
Expand All @@ -171,6 +177,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
tcg_gen_brcond_tl(cond, src1, src2, l);
}
gen_goto_tb(ctx, 1, ctx->cur_insn_len);
ctx->pc_save = orig_pc_save;

gen_set_label(l); /* branch taken */

Expand All @@ -183,6 +190,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
} else {
gen_goto_tb(ctx, 0, a->imm);
}
ctx->pc_save = -1;
ctx->base.is_jmp = DISAS_NORETURN;

return true;
Expand Down
4 changes: 3 additions & 1 deletion target/riscv/insn_trans/trans_rvzce.c.inc
View file
Expand Up @@ -302,7 +302,9 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)

/* c.jt vs c.jalt depends on the index. */
if (a->index >= 32) {
gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
TCGv succ_pc = dest_gpr(ctx, xRA);
gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
gen_set_gpr(ctx, xRA, succ_pc);
}

tcg_gen_lookup_and_goto_ptr();
Expand Down
47 changes: 40 additions & 7 deletions target/riscv/translate.c
View file
Expand Up @@ -62,6 +62,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong cur_insn_len;
target_ulong pc_save;
target_ulong priv_ver;
RISCVMXL misa_mxl_max;
RISCVMXL xl;
Expand Down Expand Up @@ -230,15 +231,24 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
{
target_ulong dest = ctx->base.pc_next + diff;

if (get_xl(ctx) == MXL_RV32) {
dest = (int32_t)dest;
assert(ctx->pc_save != -1);
if (tb_cflags(ctx->base.tb) & CF_PCREL) {
tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save);
if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32s_tl(target, target);
}
} else {
if (get_xl(ctx) == MXL_RV32) {
dest = (int32_t)dest;
}
tcg_gen_movi_tl(target, dest);
}
tcg_gen_movi_tl(target, dest);
}

static void gen_update_pc(DisasContext *ctx, target_long diff)
{
gen_pc_plus_diff(cpu_pc, ctx, diff);
ctx->pc_save = ctx->base.pc_next + diff;
}

static void generate_exception(DisasContext *ctx, int excp)
Expand Down Expand Up @@ -294,8 +304,21 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
* direct block chain benefits will be small.
*/
if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
tcg_gen_goto_tb(n);
gen_update_pc(ctx, diff);
/*
* For pcrel, the pc must always be up-to-date on entry to
* the linked TB, so that it can use simple additions for all
* further adjustments. For !pcrel, the linked TB is compiled
* to know its full virtual address, so we can delay the
* update to pc to the unlinked path. A long chain of links
* can thus avoid many updates to the PC.
*/
if (tb_cflags(ctx->base.tb) & CF_PCREL) {
gen_update_pc(ctx, diff);
tcg_gen_goto_tb(n);
} else {
tcg_gen_goto_tb(n);
gen_update_pc(ctx, diff);
}
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
gen_update_pc(ctx, diff);
Expand Down Expand Up @@ -549,6 +572,8 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)

static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
TCGv succ_pc = dest_gpr(ctx, rd);

/* check misaligned: */
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if ((imm & 0x3) != 0) {
Expand All @@ -559,7 +584,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
}
}

gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
gen_set_gpr(ctx, rd, succ_pc);

gen_goto_tb(ctx, 0, imm); /* must use this for safety */
ctx->base.is_jmp = DISAS_NORETURN;
}
Expand Down Expand Up @@ -1157,6 +1184,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t tb_flags = ctx->base.tb->flags;

ctx->pc_save = ctx->base.pc_first;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
Expand Down Expand Up @@ -1192,8 +1220,13 @@ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
target_ulong pc_next = ctx->base.pc_next;

if (tb_cflags(dcbase->tb) & CF_PCREL) {
pc_next &= ~TARGET_PAGE_MASK;
}

tcg_gen_insn_start(ctx->base.pc_next, 0);
tcg_gen_insn_start(pc_next, 0);
ctx->insn_start = tcg_last_op();
}

Expand Down

0 comments on commit 356c13f

Please sign in to comment.