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Merge tag 'pull-tricore-20230607' of https://github.com/bkoppelmann/qemu 
 into staging

- Refactor PCXI/ICR field handling in newer ISA versions
- Add simple tests written in C

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# gpg:                using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14
# gpg:                issuer "kbastian@mail.uni-paderborn.de"
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [unknown]
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# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E  6E37 0AD2 C639 6B69 CA14

* tag 'pull-tricore-20230607' of https://github.com/bkoppelmann/qemu:
  tests/tcg/tricore: Add recursion test for CSAs
  target/tricore: Fix wrong PSW for call insns
  target/tricore: Refactor PCXI/ICR register fields
  tests/tcg/tricore: Add first C program
  tests/tcg/tricore: Uses label for memory addresses
  tests/tcg/tricore: Move asm tests into 'asm' directory

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed Jun 7, 2023
2 parents 62cfa77 + e926c94 commit 45ae979
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Showing 28 changed files with 572 additions and 91 deletions.
1 change: 1 addition & 0 deletions configure
View file
Expand Up @@ -1383,6 +1383,7 @@ probe_target_compiler() {
container_cross_prefix=tricore-
container_cross_as=tricore-as
container_cross_ld=tricore-ld
container_cross_cc=tricore-gcc
break
;;
x86_64)
Expand Down
39 changes: 28 additions & 11 deletions target/tricore/cpu.h
View file
Expand Up @@ -21,6 +21,7 @@
#define TRICORE_CPU_H

#include "cpu-qom.h"
#include "hw/registerfields.h"
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
#include "tricore-defs.h"
Expand Down Expand Up @@ -199,13 +200,33 @@ struct ArchCPU {
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);


#define MASK_PCXI_PCPN 0xff000000
#define MASK_PCXI_PIE_1_3 0x00800000
#define MASK_PCXI_PIE_1_6 0x00200000
#define MASK_PCXI_UL 0x00400000
#define MASK_PCXI_PCXS 0x000f0000
#define MASK_PCXI_PCXO 0x0000ffff
FIELD(PCXI, PCPN_13, 24, 8)
FIELD(PCXI, PCPN_161, 22, 8)
FIELD(PCXI, PIE_13, 23, 1)
FIELD(PCXI, PIE_161, 21, 1)
FIELD(PCXI, UL_13, 22, 1)
FIELD(PCXI, UL_161, 20, 1)
FIELD(PCXI, PCXS, 16, 4)
FIELD(PCXI, PCXO, 0, 16)
uint32_t pcxi_get_ul(CPUTriCoreState *env);
uint32_t pcxi_get_pie(CPUTriCoreState *env);
uint32_t pcxi_get_pcpn(CPUTriCoreState *env);
uint32_t pcxi_get_pcxs(CPUTriCoreState *env);
uint32_t pcxi_get_pcxo(CPUTriCoreState *env);
void pcxi_set_ul(CPUTriCoreState *env, uint32_t val);
void pcxi_set_pie(CPUTriCoreState *env, uint32_t val);
void pcxi_set_pcpn(CPUTriCoreState *env, uint32_t val);

FIELD(ICR, IE_161, 15, 1)
FIELD(ICR, IE_13, 8, 1)
FIELD(ICR, PIPN, 16, 8)
FIELD(ICR, CCPN, 0, 8)

uint32_t icr_get_ie(CPUTriCoreState *env);
uint32_t icr_get_ccpn(CPUTriCoreState *env);

void icr_set_ccpn(CPUTriCoreState *env, uint32_t val);
void icr_set_ie(CPUTriCoreState *env, uint32_t val);

#define MASK_PSW_USB 0xff000000
#define MASK_USB_C 0x80000000
Expand All @@ -228,10 +249,6 @@ void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
#define MASK_CPUID_MOD_32B 0x0000ff00
#define MASK_CPUID_REV 0x000000ff

#define MASK_ICR_PIPN 0x00ff0000
#define MASK_ICR_IE_1_3 0x00000100
#define MASK_ICR_IE_1_6 0x00008000
#define MASK_ICR_CCPN 0x000000ff

#define MASK_FCX_FCXS 0x000f0000
#define MASK_FCX_FCXO 0x0000ffff
Expand Down
45 changes: 45 additions & 0 deletions target/tricore/helper.c
View file
Expand Up @@ -17,6 +17,7 @@

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/registerfields.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "fpu/softfloat-helpers.h"
Expand Down Expand Up @@ -152,3 +153,47 @@ void psw_write(CPUTriCoreState *env, uint32_t val)

fpu_set_state(env);
}

#define FIELD_GETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \
uint32_t NAME(CPUTriCoreState *env) \
{ \
if (tricore_feature(env, TRICORE_FEATURE_##FEATURE)) { \
return FIELD_EX32(env->REG, REG, FIELD ## _ ## FEATURE); \
} \
return FIELD_EX32(env->REG, REG, FIELD ## _13); \
}

#define FIELD_GETTER(NAME, REG, FIELD) \
uint32_t NAME(CPUTriCoreState *env) \
{ \
return FIELD_EX32(env->REG, REG, FIELD); \
}

#define FIELD_SETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \
void NAME(CPUTriCoreState *env, uint32_t val) \
{ \
if (tricore_feature(env, TRICORE_FEATURE_##FEATURE)) { \
env->REG = FIELD_DP32(env->REG, REG, FIELD ## _ ## FEATURE, val); \
} \
env->REG = FIELD_DP32(env->REG, REG, FIELD ## _13, val); \
}

#define FIELD_SETTER(NAME, REG, FIELD) \
void NAME(CPUTriCoreState *env, uint32_t val) \
{ \
env->REG = FIELD_DP32(env->REG, REG, FIELD, val); \
}

FIELD_GETTER_WITH_FEATURE(pcxi_get_pcpn, PCXI, PCPN, 161)
FIELD_SETTER_WITH_FEATURE(pcxi_set_pcpn, PCXI, PCPN, 161)
FIELD_GETTER_WITH_FEATURE(pcxi_get_pie, PCXI, PIE, 161)
FIELD_SETTER_WITH_FEATURE(pcxi_set_pie, PCXI, PIE, 161)
FIELD_GETTER_WITH_FEATURE(pcxi_get_ul, PCXI, UL, 161)
FIELD_SETTER_WITH_FEATURE(pcxi_set_ul, PCXI, UL, 161)
FIELD_GETTER(pcxi_get_pcxs, PCXI, PCXS)
FIELD_GETTER(pcxi_get_pcxo, PCXI, PCXO)

FIELD_GETTER_WITH_FEATURE(icr_get_ie, ICR, IE, 161)
FIELD_SETTER_WITH_FEATURE(icr_set_ie, ICR, IE, 161)
FIELD_GETTER(icr_get_ccpn, ICR, CCPN)
FIELD_SETTER(icr_set_ccpn, ICR, CCPN)
87 changes: 44 additions & 43 deletions target/tricore/op_helper.c
View file
Expand Up @@ -84,11 +84,10 @@ void raise_exception_sync_internal(CPUTriCoreState *env, uint32_t class, int tin
ICR.IE and ICR.CCPN are saved */

/* PCXI.PIE = ICR.IE */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
pcxi_set_pie(env, icr_get_ie(env));

/* PCXI.PCPN = ICR.CCPN */
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
pcxi_set_pcpn(env, icr_get_ccpn(env));
/* Update PC using the trap vector table */
env->PC = env->BTV | (class << 5);

Expand Down Expand Up @@ -2448,6 +2447,8 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)
}
/* PSW.CDE = 1;*/
psw |= MASK_PSW_CDE;
psw_write(env, psw);

/* tmp_FCX = FCX; */
tmp_FCX = env->FCX;
/* EA = {FCX.FCXS, 6'b0, FCX.FCXO, 6'b0}; */
Expand All @@ -2461,13 +2462,11 @@ void helper_call(CPUTriCoreState *env, uint32_t next_pc)
save_context_upper(env, ea);

/* PCXI.PCPN = ICR.CCPN; */
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
pcxi_set_pcpn(env, icr_get_ccpn(env));
/* PCXI.PIE = ICR.IE; */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
pcxi_set_pie(env, icr_get_ie(env));
/* PCXI.UL = 1; */
env->PCXI |= MASK_PCXI_UL;
pcxi_set_ul(env, 1);

/* PCXI[19: 0] = FCX[19: 0]; */
env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
Expand Down Expand Up @@ -2506,7 +2505,7 @@ void helper_ret(CPUTriCoreState *env)
raise_exception_sync_helper(env, TRAPC_CTX_MNG, TIN3_CSU, GETPC());
}
/* if (PCXI.UL == 0) then trap(CTYP); */
if ((env->PCXI & MASK_PCXI_UL) == 0) {
if (pcxi_get_ul(env) == 0) {
/* CTYP trap */
cdc_increment(&psw); /* restore to the start of helper */
psw_write(env, psw);
Expand All @@ -2516,8 +2515,8 @@ void helper_ret(CPUTriCoreState *env)
env->PC = env->gpr_a[11] & 0xfffffffe;

/* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
((env->PCXI & MASK_PCXI_PCXO) << 6);
ea = (pcxi_get_pcxs(env) << 28) |
(pcxi_get_pcxo(env) << 6);
/* {new_PCXI, new_PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
restore_context_upper(env, ea, &new_PCXI, &new_PSW);
Expand Down Expand Up @@ -2559,21 +2558,21 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const9)


/* PCXI.PCPN = ICR.CCPN */
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
pcxi_set_pcpn(env, icr_get_ccpn(env));
/* PCXI.PIE = ICR.IE */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
pcxi_set_pie(env, icr_get_ie(env));
/* PCXI.UL = 0 */
env->PCXI &= ~(MASK_PCXI_UL);
pcxi_set_ul(env, 0);

/* PCXI[19: 0] = FCX[19: 0] */
env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
/* FXC[19: 0] = new_FCX[19: 0] */
env->FCX = (env->FCX & 0xfff00000) + (new_FCX & 0xfffff);

/* ICR.IE = 1 */
env->ICR |= MASK_ICR_IE_1_3;
icr_set_ie(env, 1);

env->ICR |= const9; /* ICR.CCPN = const9[7: 0];*/
icr_set_ccpn(env, const9);

if (tmp_FCX == env->LCX) {
/* FCD trap */
Expand All @@ -2592,7 +2591,7 @@ void helper_rfe(CPUTriCoreState *env)
raise_exception_sync_helper(env, TRAPC_CTX_MNG, TIN3_CSU, GETPC());
}
/* if (PCXI.UL == 0) then trap(CTYP); */
if ((env->PCXI & MASK_PCXI_UL) == 0) {
if (pcxi_get_ul(env) == 0) {
/* raise CTYP trap */
raise_exception_sync_helper(env, TRAPC_CTX_MNG, TIN3_CTYP, GETPC());
}
Expand All @@ -2603,14 +2602,15 @@ void helper_rfe(CPUTriCoreState *env)
}
env->PC = env->gpr_a[11] & ~0x1;
/* ICR.IE = PCXI.PIE; */
env->ICR = (env->ICR & ~MASK_ICR_IE_1_3)
+ ((env->PCXI & MASK_PCXI_PIE_1_3) >> 15);
icr_set_ie(env, pcxi_get_pie(env));

/* ICR.CCPN = PCXI.PCPN; */
env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
((env->PCXI & MASK_PCXI_PCPN) >> 24);
icr_set_ccpn(env, pcxi_get_pcpn(env));

/*EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};*/
ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
((env->PCXI & MASK_PCXI_PCXO) << 6);
ea = (pcxi_get_pcxs(env) << 28) |
(pcxi_get_pcxo(env) << 6);

/*{new_PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
restore_context_upper(env, ea, &new_PCXI, &new_PSW);
Expand All @@ -2628,11 +2628,10 @@ void helper_rfm(CPUTriCoreState *env)
{
env->PC = (env->gpr_a[11] & ~0x1);
/* ICR.IE = PCXI.PIE; */
env->ICR = (env->ICR & ~MASK_ICR_IE_1_3)
| ((env->PCXI & MASK_PCXI_PIE_1_3) >> 15);
icr_set_ie(env, pcxi_get_pie(env));
/* ICR.CCPN = PCXI.PCPN; */
env->ICR = (env->ICR & ~MASK_ICR_CCPN) |
((env->PCXI & MASK_PCXI_PCPN) >> 24);
icr_set_ccpn(env, pcxi_get_pcpn(env));

/* {PCXI, PSW, A[10], A[11]} = M(DCX, 4 * word); */
env->PCXI = cpu_ldl_data(env, env->DCX);
psw_write(env, cpu_ldl_data(env, env->DCX+4));
Expand Down Expand Up @@ -2691,13 +2690,13 @@ void helper_svlcx(CPUTriCoreState *env)
save_context_lower(env, ea);

/* PCXI.PCPN = ICR.CCPN; */
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
pcxi_set_pcpn(env, icr_get_ccpn(env));

/* PCXI.PIE = ICR.IE; */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
pcxi_set_pie(env, icr_get_ie(env));

/* PCXI.UL = 0; */
env->PCXI &= ~MASK_PCXI_UL;
pcxi_set_ul(env, 0);

/* PCXI[19: 0] = FCX[19: 0]; */
env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
Expand Down Expand Up @@ -2734,13 +2733,13 @@ void helper_svucx(CPUTriCoreState *env)
save_context_upper(env, ea);

/* PCXI.PCPN = ICR.CCPN; */
env->PCXI = (env->PCXI & 0xffffff) +
((env->ICR & MASK_ICR_CCPN) << 24);
pcxi_set_pcpn(env, icr_get_ccpn(env));

/* PCXI.PIE = ICR.IE; */
env->PCXI = ((env->PCXI & ~MASK_PCXI_PIE_1_3) +
((env->ICR & MASK_ICR_IE_1_3) << 15));
pcxi_set_pie(env, icr_get_ie(env));

/* PCXI.UL = 1; */
env->PCXI |= MASK_PCXI_UL;
pcxi_set_ul(env, 1);

/* PCXI[19: 0] = FCX[19: 0]; */
env->PCXI = (env->PCXI & 0xfff00000) + (env->FCX & 0xfffff);
Expand All @@ -2764,13 +2763,15 @@ void helper_rslcx(CPUTriCoreState *env)
raise_exception_sync_helper(env, TRAPC_CTX_MNG, TIN3_CSU, GETPC());
}
/* if (PCXI.UL == 1) then trap(CTYP); */
if ((env->PCXI & MASK_PCXI_UL) != 0) {
if (pcxi_get_ul(env) == 1) {
/* CTYP trap */
raise_exception_sync_helper(env, TRAPC_CTX_MNG, TIN3_CTYP, GETPC());
}
/* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
((env->PCXI & MASK_PCXI_PCXO) << 6);
/* EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0}; */
ea = (pcxi_get_pcxs(env) << 28) |
(pcxi_get_pcxo(env) << 6);

/* {new_PCXI, A[11], A[10], A[11], D[8], D[9], D[10], D[11], A[12],
A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word); */
restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI);
Expand Down
10 changes: 8 additions & 2 deletions target/tricore/translate.c
View file
Expand Up @@ -75,6 +75,7 @@ typedef struct DisasContext {
int mem_idx;
uint32_t hflags, saved_hflags;
uint64_t features;
uint32_t icr_ie_mask;
} DisasContext;

static int has_feature(DisasContext *ctx, int feature)
Expand Down Expand Up @@ -7850,12 +7851,12 @@ static void decode_sys_interrupts(DisasContext *ctx)
/* raise EXCP_DEBUG */
break;
case OPC2_32_SYS_DISABLE:
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3);
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
break;
case OPC2_32_SYS_DSYNC:
break;
case OPC2_32_SYS_ENABLE:
tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3);
tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
break;
case OPC2_32_SYS_ISYNC:
break;
Expand Down Expand Up @@ -8259,6 +8260,11 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
ctx->mem_idx = cpu_mmu_index(env, false);
ctx->hflags = (uint32_t)ctx->base.tb->flags;
ctx->features = env->features;
if (has_feature(ctx, TRICORE_FEATURE_161)) {
ctx->icr_ie_mask = R_ICR_IE_161_MASK;
} else {
ctx->icr_ie_mask = R_ICR_IE_13_MASK;
}
}

static void tricore_tr_tb_start(DisasContextBase *db, CPUState *cpu)
Expand Down

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