From 570ef3093b5ed327249397ad0295cf01c67d9db4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 20 Jul 2020 13:23:58 +0100 Subject: [PATCH] tcg: update comments for save_iotlb_data in cputlb MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I missed Emilio's review comments: Message-ID: <20200718205107.GA994221@sff> and the patch got merged. Correcting the comments now. Reviewed-by: Emilio G. Cota Signed-off-by: Alex Bennée Message-Id: <20200720122358.26881-1-alex.bennee@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d370aedb475a..56982927490c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1075,10 +1075,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, /* * Save a potentially trashed IOTLB entry for later lookup by plugin. - * - * We also need to track the thread storage address because the RCU - * cleanup that runs when we leave the critical region (the current - * execution) is actually in a different thread. + * This is read by tlb_plugin_lookup if the iotlb entry doesn't match + * because of the side effect of io_writex changing memory layout. */ static void save_iotlb_data(CPUState *cs, hwaddr addr, MemoryRegionSection *section, hwaddr mr_offset) @@ -1408,8 +1406,9 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, * This almost never fails as the memory access being instrumented * should have just filled the TLB. The one corner case is io_writex * which can cause TLB flushes and potential resizing of the TLBs - * loosing the information we need. In those cases we need to recover - * data from a copy of the io_tlb entry. + * losing the information we need. In those cases we need to recover + * data from a copy of the iotlbentry. As long as this always occurs + * from the same thread (which a mem callback will be) this is safe. */ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,