Skip to content

Commit

Permalink
Merge tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu…
Browse files Browse the repository at this point in the history 
… into staging

hw/nvme fixes

- use the stl/ldl pci dma api

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmTGuc8ACgkQTeGvMW1P
# Dek41wgAwqgRmtUhmmaQJJpF5Pya3J7n3Zkbp+cULdnSp/su7W7yIUTcTzdbr34d
# 9LbNHmWerXYinlIxG08ZWw2lq0TwApKj+8gv/wf8H7dG86/pBYfoQvOlkNx2QKyR
# vtRNlILCEbJpbSfY3LbFNvRGOkArr6HkzT4hZprUIfCvRg58u5oIxEx/ZYa+m3WU
# ED0y/46e7HbVbmbwJKrn4EK3k0zGdFyeINRZ5TB5DML3lCTX6eaZTLUXGIb7LLcK
# Xyv6/TCkPTggDszTam24kx0A7DhC+3f2C8DsJg7H8jnWb1F+oq/2EJam/0HU22Uk
# n348MrWOusuF7kbHMCP9h28gYT3aWw==
# =KjVO
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 30 Jul 2023 12:28:15 PM PDT
# gpg:                using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9
# gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown]
# gpg:                 aka "Klaus Jensen <k.jensen@samsung.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468  4272 63D5 6FC5 E55D A838
#      Subkey fingerprint: 5228 33AA 75E2 DCE6 A247  66C0 4DE1 AF31 6D4F 0DE9

* tag 'nvme-next-pull-request' of https://gitlab.com/birkelund/qemu:
  hw/nvme: use stl/ldl pci dma api

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
  • Loading branch information
@rth7680
rth7680 committed Jul 30, 2023
2 parents ccb86f0 + c1e244b commit 8cb945b
Showing 1 changed file with 13 additions and 29 deletions.
42 changes: 13 additions & 29 deletions hw/nvme/ctrl.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1468,20 +1468,16 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset,

static void nvme_update_cq_eventidx(const NvmeCQueue *cq)
{
uint32_t v = cpu_to_le32(cq->head);

trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head);

pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &v, sizeof(v));
stl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->ei_addr, cq->head,
MEMTXATTRS_UNSPECIFIED);
}

static void nvme_update_cq_head(NvmeCQueue *cq)
{
uint32_t v;

pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &v, sizeof(v));

cq->head = le32_to_cpu(v);
ldl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head,
MEMTXATTRS_UNSPECIFIED);

trace_pci_nvme_update_cq_head(cq->cqid, cq->head);
}
Expand Down Expand Up @@ -6801,7 +6797,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
PCIDevice *pci = PCI_DEVICE(n);
uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1);
uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2);
uint32_t v;
int i;

/* Address should be page aligned */
Expand All @@ -6819,16 +6814,14 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
NvmeCQueue *cq = n->cq[i];

if (sq) {
v = cpu_to_le32(sq->tail);

/*
* CAP.DSTRD is 0, so offset of ith sq db_addr is (i<<3)
* nvme_process_db() uses this hard-coded way to calculate
* doorbell offsets. Be consistent with that here.
*/
sq->db_addr = dbs_addr + (i << 3);
sq->ei_addr = eis_addr + (i << 3);
pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail));
stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIFIED);

if (n->params.ioeventfd && sq->sqid != 0) {
if (!nvme_init_sq_ioeventfd(sq)) {
Expand All @@ -6838,12 +6831,10 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
}

if (cq) {
v = cpu_to_le32(cq->head);

/* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2) */
cq->db_addr = dbs_addr + (i << 3) + (1 << 2);
cq->ei_addr = eis_addr + (i << 3) + (1 << 2);
pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head));
stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIFIED);

if (n->params.ioeventfd && cq->cqid != 0) {
if (!nvme_init_cq_ioeventfd(cq)) {
Expand Down Expand Up @@ -6974,20 +6965,16 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)

static void nvme_update_sq_eventidx(const NvmeSQueue *sq)
{
uint32_t v = cpu_to_le32(sq->tail);

trace_pci_nvme_update_sq_eventidx(sq->sqid, sq->tail);

pci_dma_write(PCI_DEVICE(sq->ctrl), sq->ei_addr, &v, sizeof(v));
stl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->ei_addr, sq->tail,
MEMTXATTRS_UNSPECIFIED);
}

static void nvme_update_sq_tail(NvmeSQueue *sq)
{
uint32_t v;

pci_dma_read(PCI_DEVICE(sq->ctrl), sq->db_addr, &v, sizeof(v));

sq->tail = le32_to_cpu(v);
ldl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->db_addr, &sq->tail,
MEMTXATTRS_UNSPECIFIED);

trace_pci_nvme_update_sq_tail(sq->sqid, sq->tail);
}
Expand Down Expand Up @@ -7592,7 +7579,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
{
PCIDevice *pci = PCI_DEVICE(n);
uint32_t qid, v;
uint32_t qid;

if (unlikely(addr & ((1 << 2) - 1))) {
NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned,
Expand Down Expand Up @@ -7659,8 +7646,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
start_sqs = nvme_cq_full(cq) ? 1 : 0;
cq->head = new_head;
if (!qid && n->dbbuf_enabled) {
v = cpu_to_le32(cq->head);
pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head));
stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIFIED);
}
if (start_sqs) {
NvmeSQueue *sq;
Expand Down Expand Up @@ -7720,8 +7706,6 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)

sq->tail = new_tail;
if (!qid && n->dbbuf_enabled) {
v = cpu_to_le32(sq->tail);

/*
* The spec states "the host shall also update the controller's
* corresponding doorbell property to match the value of that entry
Expand All @@ -7735,7 +7719,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
* including ones that run on Linux, are not updating Admin Queues,
* so we can't trust reading it for an appropriate sq tail.
*/
pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail));
stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIFIED);
}

qemu_bh_schedule(sq->bh);
Expand Down

0 comments on commit 8cb945b

Please sign in to comment.