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target/loongarch: Implement LSX fpu arith instructions 
This patch includes:
- VF{ADD/SUB/MUL/DIV}.{S/D};
- VF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- VF{MAX/MIN}.{S/D};
- VF{MAXA/MINA}.{S/D};
- VFLOGB.{S/D};
- VFCLASS.{S/D};
- VF{SQRT/RECIP/RSQRT}.{S/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-34-gaosong@loongson.cn>
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@gaosong-loongson
gaosong-loongson committed May 6, 2023
1 parent ac95a0b commit aca6747
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Showing 8 changed files with 377 additions and 1 deletion.
4 changes: 4 additions & 0 deletions target/loongarch/cpu.h
View file
Expand Up @@ -55,6 +55,10 @@ FIELD(FCSR0, CAUSE, 24, 5)
do { \
(REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
} while (0)
#define UPDATE_FP_CAUSE(REG, V) \
do { \
(REG) |= FIELD_DP32(0, FCSR0, CAUSE, V); \
} while (0)

#define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES)
#define SET_FP_ENABLES(REG, V) \
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46 changes: 46 additions & 0 deletions target/loongarch/disas.c
View file
Expand Up @@ -807,6 +807,11 @@ static void output_vv(DisasContext *ctx, arg_vv *a, const char *mnemonic)
output(ctx, mnemonic, "v%d, v%d", a->vd, a->vj);
}

static void output_vvvv(DisasContext *ctx, arg_vvvv *a, const char *mnemonic)
{
output(ctx, mnemonic, "v%d, v%d, v%d, v%d", a->vd, a->vj, a->vk, a->va);
}

INSN_LSX(vadd_b, vvv)
INSN_LSX(vadd_h, vvv)
INSN_LSX(vadd_w, vvv)
Expand Down Expand Up @@ -1302,3 +1307,44 @@ INSN_LSX(vfrstp_b, vvv)
INSN_LSX(vfrstp_h, vvv)
INSN_LSX(vfrstpi_b, vv_i)
INSN_LSX(vfrstpi_h, vv_i)

INSN_LSX(vfadd_s, vvv)
INSN_LSX(vfadd_d, vvv)
INSN_LSX(vfsub_s, vvv)
INSN_LSX(vfsub_d, vvv)
INSN_LSX(vfmul_s, vvv)
INSN_LSX(vfmul_d, vvv)
INSN_LSX(vfdiv_s, vvv)
INSN_LSX(vfdiv_d, vvv)

INSN_LSX(vfmadd_s, vvvv)
INSN_LSX(vfmadd_d, vvvv)
INSN_LSX(vfmsub_s, vvvv)
INSN_LSX(vfmsub_d, vvvv)
INSN_LSX(vfnmadd_s, vvvv)
INSN_LSX(vfnmadd_d, vvvv)
INSN_LSX(vfnmsub_s, vvvv)
INSN_LSX(vfnmsub_d, vvvv)

INSN_LSX(vfmax_s, vvv)
INSN_LSX(vfmax_d, vvv)
INSN_LSX(vfmin_s, vvv)
INSN_LSX(vfmin_d, vvv)

INSN_LSX(vfmaxa_s, vvv)
INSN_LSX(vfmaxa_d, vvv)
INSN_LSX(vfmina_s, vvv)
INSN_LSX(vfmina_d, vvv)

INSN_LSX(vflogb_s, vv)
INSN_LSX(vflogb_d, vv)

INSN_LSX(vfclass_s, vv)
INSN_LSX(vfclass_d, vv)

INSN_LSX(vfsqrt_s, vv)
INSN_LSX(vfsqrt_d, vv)
INSN_LSX(vfrecip_s, vv)
INSN_LSX(vfrecip_d, vv)
INSN_LSX(vfrsqrt_s, vv)
INSN_LSX(vfrsqrt_d, vv)
2 changes: 1 addition & 1 deletion target/loongarch/fpu_helper.c
View file
Expand Up @@ -33,7 +33,7 @@ void restore_fp_status(CPULoongArchState *env)
set_flush_to_zero(0, &env->fp_status);
}

static int ieee_ex_to_loongarch(int xcpt)
int ieee_ex_to_loongarch(int xcpt)
{
int ret = 0;
if (xcpt & float_flag_invalid) {
Expand Down
41 changes: 41 additions & 0 deletions target/loongarch/helper.h
View file
Expand Up @@ -517,3 +517,44 @@ DEF_HELPER_4(vfrstp_b, void, env, i32, i32, i32)
DEF_HELPER_4(vfrstp_h, void, env, i32, i32, i32)
DEF_HELPER_4(vfrstpi_b, void, env, i32, i32, i32)
DEF_HELPER_4(vfrstpi_h, void, env, i32, i32, i32)

DEF_HELPER_4(vfadd_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfadd_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfsub_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfsub_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmul_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmul_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfdiv_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfdiv_d, void, env, i32, i32, i32)

DEF_HELPER_5(vfmadd_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmadd_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmsub_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmsub_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmadd_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmadd_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmsub_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmsub_d, void, env, i32, i32, i32, i32)

DEF_HELPER_4(vfmax_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmax_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmin_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmin_d, void, env, i32, i32, i32)

DEF_HELPER_4(vfmaxa_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmaxa_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmina_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmina_d, void, env, i32, i32, i32)

DEF_HELPER_3(vflogb_s, void, env, i32, i32)
DEF_HELPER_3(vflogb_d, void, env, i32, i32)

DEF_HELPER_3(vfclass_s, void, env, i32, i32)
DEF_HELPER_3(vfclass_d, void, env, i32, i32)

DEF_HELPER_3(vfsqrt_s, void, env, i32, i32)
DEF_HELPER_3(vfsqrt_d, void, env, i32, i32)
DEF_HELPER_3(vfrecip_s, void, env, i32, i32)
DEF_HELPER_3(vfrecip_d, void, env, i32, i32)
DEF_HELPER_3(vfrsqrt_s, void, env, i32, i32)
DEF_HELPER_3(vfrsqrt_d, void, env, i32, i32)
55 changes: 55 additions & 0 deletions target/loongarch/insn_trans/trans_lsx.c.inc
View file
Expand Up @@ -15,6 +15,20 @@
#define CHECK_SXE
#endif

static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a,
void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32,
TCGv_i32, TCGv_i32))
{
TCGv_i32 vd = tcg_constant_i32(a->vd);
TCGv_i32 vj = tcg_constant_i32(a->vj);
TCGv_i32 vk = tcg_constant_i32(a->vk);
TCGv_i32 va = tcg_constant_i32(a->va);

CHECK_SXE;
func(cpu_env, vd, vj, vk, va);
return true;
}

static bool gen_vvv(DisasContext *ctx, arg_vvv *a,
void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
{
Expand Down Expand Up @@ -3421,3 +3435,44 @@ TRANS(vfrstp_b, gen_vvv, gen_helper_vfrstp_b)
TRANS(vfrstp_h, gen_vvv, gen_helper_vfrstp_h)
TRANS(vfrstpi_b, gen_vv_i, gen_helper_vfrstpi_b)
TRANS(vfrstpi_h, gen_vv_i, gen_helper_vfrstpi_h)

TRANS(vfadd_s, gen_vvv, gen_helper_vfadd_s)
TRANS(vfadd_d, gen_vvv, gen_helper_vfadd_d)
TRANS(vfsub_s, gen_vvv, gen_helper_vfsub_s)
TRANS(vfsub_d, gen_vvv, gen_helper_vfsub_d)
TRANS(vfmul_s, gen_vvv, gen_helper_vfmul_s)
TRANS(vfmul_d, gen_vvv, gen_helper_vfmul_d)
TRANS(vfdiv_s, gen_vvv, gen_helper_vfdiv_s)
TRANS(vfdiv_d, gen_vvv, gen_helper_vfdiv_d)

TRANS(vfmadd_s, gen_vvvv, gen_helper_vfmadd_s)
TRANS(vfmadd_d, gen_vvvv, gen_helper_vfmadd_d)
TRANS(vfmsub_s, gen_vvvv, gen_helper_vfmsub_s)
TRANS(vfmsub_d, gen_vvvv, gen_helper_vfmsub_d)
TRANS(vfnmadd_s, gen_vvvv, gen_helper_vfnmadd_s)
TRANS(vfnmadd_d, gen_vvvv, gen_helper_vfnmadd_d)
TRANS(vfnmsub_s, gen_vvvv, gen_helper_vfnmsub_s)
TRANS(vfnmsub_d, gen_vvvv, gen_helper_vfnmsub_d)

TRANS(vfmax_s, gen_vvv, gen_helper_vfmax_s)
TRANS(vfmax_d, gen_vvv, gen_helper_vfmax_d)
TRANS(vfmin_s, gen_vvv, gen_helper_vfmin_s)
TRANS(vfmin_d, gen_vvv, gen_helper_vfmin_d)

TRANS(vfmaxa_s, gen_vvv, gen_helper_vfmaxa_s)
TRANS(vfmaxa_d, gen_vvv, gen_helper_vfmaxa_d)
TRANS(vfmina_s, gen_vvv, gen_helper_vfmina_s)
TRANS(vfmina_d, gen_vvv, gen_helper_vfmina_d)

TRANS(vflogb_s, gen_vv, gen_helper_vflogb_s)
TRANS(vflogb_d, gen_vv, gen_helper_vflogb_d)

TRANS(vfclass_s, gen_vv, gen_helper_vfclass_s)
TRANS(vfclass_d, gen_vv, gen_helper_vfclass_d)

TRANS(vfsqrt_s, gen_vv, gen_helper_vfsqrt_s)
TRANS(vfsqrt_d, gen_vv, gen_helper_vfsqrt_d)
TRANS(vfrecip_s, gen_vv, gen_helper_vfrecip_s)
TRANS(vfrecip_d, gen_vv, gen_helper_vfrecip_d)
TRANS(vfrsqrt_s, gen_vv, gen_helper_vfrsqrt_s)
TRANS(vfrsqrt_d, gen_vv, gen_helper_vfrsqrt_d)
43 changes: 43 additions & 0 deletions target/loongarch/insns.decode
View file
Expand Up @@ -493,6 +493,7 @@ dbcl 0000 00000010 10101 ............... @i15
&vv vd vj
&vvv vd vj vk
&vv_i vd vj imm
&vvvv vd vj vk va

#
# LSX Formats
Expand All @@ -506,6 +507,7 @@ dbcl 0000 00000010 10101 ............... @i15
@vv_ui7 .... ........ ... imm:7 vj:5 vd:5 &vv_i
@vv_ui8 .... ........ .. imm:8 vj:5 vd:5 &vv_i
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
@vvvv .... ........ va:5 vk:5 vj:5 vd:5 &vvvv

vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
vadd_h 0111 00000000 10101 ..... ..... ..... @vvv
Expand Down Expand Up @@ -1003,3 +1005,44 @@ vfrstp_b 0111 00010010 10110 ..... ..... ..... @vvv
vfrstp_h 0111 00010010 10111 ..... ..... ..... @vvv
vfrstpi_b 0111 00101001 10100 ..... ..... ..... @vv_ui5
vfrstpi_h 0111 00101001 10101 ..... ..... ..... @vv_ui5

vfadd_s 0111 00010011 00001 ..... ..... ..... @vvv
vfadd_d 0111 00010011 00010 ..... ..... ..... @vvv
vfsub_s 0111 00010011 00101 ..... ..... ..... @vvv
vfsub_d 0111 00010011 00110 ..... ..... ..... @vvv
vfmul_s 0111 00010011 10001 ..... ..... ..... @vvv
vfmul_d 0111 00010011 10010 ..... ..... ..... @vvv
vfdiv_s 0111 00010011 10101 ..... ..... ..... @vvv
vfdiv_d 0111 00010011 10110 ..... ..... ..... @vvv

vfmadd_s 0000 10010001 ..... ..... ..... ..... @vvvv
vfmadd_d 0000 10010010 ..... ..... ..... ..... @vvvv
vfmsub_s 0000 10010101 ..... ..... ..... ..... @vvvv
vfmsub_d 0000 10010110 ..... ..... ..... ..... @vvvv
vfnmadd_s 0000 10011001 ..... ..... ..... ..... @vvvv
vfnmadd_d 0000 10011010 ..... ..... ..... ..... @vvvv
vfnmsub_s 0000 10011101 ..... ..... ..... ..... @vvvv
vfnmsub_d 0000 10011110 ..... ..... ..... ..... @vvvv

vfmax_s 0111 00010011 11001 ..... ..... ..... @vvv
vfmax_d 0111 00010011 11010 ..... ..... ..... @vvv
vfmin_s 0111 00010011 11101 ..... ..... ..... @vvv
vfmin_d 0111 00010011 11110 ..... ..... ..... @vvv

vfmaxa_s 0111 00010100 00001 ..... ..... ..... @vvv
vfmaxa_d 0111 00010100 00010 ..... ..... ..... @vvv
vfmina_s 0111 00010100 00101 ..... ..... ..... @vvv
vfmina_d 0111 00010100 00110 ..... ..... ..... @vvv

vflogb_s 0111 00101001 11001 10001 ..... ..... @vv
vflogb_d 0111 00101001 11001 10010 ..... ..... @vv

vfclass_s 0111 00101001 11001 10101 ..... ..... @vv
vfclass_d 0111 00101001 11001 10110 ..... ..... @vv

vfsqrt_s 0111 00101001 11001 11001 ..... ..... @vv
vfsqrt_d 0111 00101001 11001 11010 ..... ..... @vv
vfrecip_s 0111 00101001 11001 11101 ..... ..... @vv
vfrecip_d 0111 00101001 11001 11110 ..... ..... @vv
vfrsqrt_s 0111 00101001 11010 00001 ..... ..... @vv
vfrsqrt_d 0111 00101001 11010 00010 ..... ..... @vv
1 change: 1 addition & 0 deletions target/loongarch/internals.h
View file
Expand Up @@ -53,6 +53,7 @@ void G_NORETURN do_raise_exception(CPULoongArchState *env,

const char *loongarch_exception_name(int32_t exception);

int ieee_ex_to_loongarch(int xcpt);
void restore_fp_status(CPULoongArchState *env);

#ifndef CONFIG_USER_ONLY
Expand Down

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