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target/loongarch: Implement vsll vsrl vsra vrotr
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This patch includes:
- VSLL[I].{B/H/W/D};
- VSRL[I].{B/H/W/D};
- VSRA[I].{B/H/W/D};
- VROTR[I].{B/H/W/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-23-gaosong@loongson.cn>
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gaosong-loongson committed May 6, 2023
1 parent f205a53 commit b281d69
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Showing 3 changed files with 108 additions and 0 deletions.
36 changes: 36 additions & 0 deletions target/loongarch/disas.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1103,3 +1103,39 @@ INSN_LSX(vandi_b, vv_i)
INSN_LSX(vori_b, vv_i)
INSN_LSX(vxori_b, vv_i)
INSN_LSX(vnori_b, vv_i)

INSN_LSX(vsll_b, vvv)
INSN_LSX(vsll_h, vvv)
INSN_LSX(vsll_w, vvv)
INSN_LSX(vsll_d, vvv)
INSN_LSX(vslli_b, vv_i)
INSN_LSX(vslli_h, vv_i)
INSN_LSX(vslli_w, vv_i)
INSN_LSX(vslli_d, vv_i)

INSN_LSX(vsrl_b, vvv)
INSN_LSX(vsrl_h, vvv)
INSN_LSX(vsrl_w, vvv)
INSN_LSX(vsrl_d, vvv)
INSN_LSX(vsrli_b, vv_i)
INSN_LSX(vsrli_h, vv_i)
INSN_LSX(vsrli_w, vv_i)
INSN_LSX(vsrli_d, vv_i)

INSN_LSX(vsra_b, vvv)
INSN_LSX(vsra_h, vvv)
INSN_LSX(vsra_w, vvv)
INSN_LSX(vsra_d, vvv)
INSN_LSX(vsrai_b, vv_i)
INSN_LSX(vsrai_h, vv_i)
INSN_LSX(vsrai_w, vv_i)
INSN_LSX(vsrai_d, vv_i)

INSN_LSX(vrotr_b, vvv)
INSN_LSX(vrotr_h, vvv)
INSN_LSX(vrotr_w, vvv)
INSN_LSX(vrotr_d, vvv)
INSN_LSX(vrotri_b, vv_i)
INSN_LSX(vrotri_h, vv_i)
INSN_LSX(vrotri_w, vv_i)
INSN_LSX(vrotri_d, vv_i)
36 changes: 36 additions & 0 deletions target/loongarch/insn_trans/trans_lsx.c.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -2930,3 +2930,39 @@ static void do_vnori_b(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,
}

TRANS(vnori_b, gvec_vv_i, MO_8, do_vnori_b)

TRANS(vsll_b, gvec_vvv, MO_8, tcg_gen_gvec_shlv)
TRANS(vsll_h, gvec_vvv, MO_16, tcg_gen_gvec_shlv)
TRANS(vsll_w, gvec_vvv, MO_32, tcg_gen_gvec_shlv)
TRANS(vsll_d, gvec_vvv, MO_64, tcg_gen_gvec_shlv)
TRANS(vslli_b, gvec_vv_i, MO_8, tcg_gen_gvec_shli)
TRANS(vslli_h, gvec_vv_i, MO_16, tcg_gen_gvec_shli)
TRANS(vslli_w, gvec_vv_i, MO_32, tcg_gen_gvec_shli)
TRANS(vslli_d, gvec_vv_i, MO_64, tcg_gen_gvec_shli)

TRANS(vsrl_b, gvec_vvv, MO_8, tcg_gen_gvec_shrv)
TRANS(vsrl_h, gvec_vvv, MO_16, tcg_gen_gvec_shrv)
TRANS(vsrl_w, gvec_vvv, MO_32, tcg_gen_gvec_shrv)
TRANS(vsrl_d, gvec_vvv, MO_64, tcg_gen_gvec_shrv)
TRANS(vsrli_b, gvec_vv_i, MO_8, tcg_gen_gvec_shri)
TRANS(vsrli_h, gvec_vv_i, MO_16, tcg_gen_gvec_shri)
TRANS(vsrli_w, gvec_vv_i, MO_32, tcg_gen_gvec_shri)
TRANS(vsrli_d, gvec_vv_i, MO_64, tcg_gen_gvec_shri)

TRANS(vsra_b, gvec_vvv, MO_8, tcg_gen_gvec_sarv)
TRANS(vsra_h, gvec_vvv, MO_16, tcg_gen_gvec_sarv)
TRANS(vsra_w, gvec_vvv, MO_32, tcg_gen_gvec_sarv)
TRANS(vsra_d, gvec_vvv, MO_64, tcg_gen_gvec_sarv)
TRANS(vsrai_b, gvec_vv_i, MO_8, tcg_gen_gvec_sari)
TRANS(vsrai_h, gvec_vv_i, MO_16, tcg_gen_gvec_sari)
TRANS(vsrai_w, gvec_vv_i, MO_32, tcg_gen_gvec_sari)
TRANS(vsrai_d, gvec_vv_i, MO_64, tcg_gen_gvec_sari)

TRANS(vrotr_b, gvec_vvv, MO_8, tcg_gen_gvec_rotrv)
TRANS(vrotr_h, gvec_vvv, MO_16, tcg_gen_gvec_rotrv)
TRANS(vrotr_w, gvec_vvv, MO_32, tcg_gen_gvec_rotrv)
TRANS(vrotr_d, gvec_vvv, MO_64, tcg_gen_gvec_rotrv)
TRANS(vrotri_b, gvec_vv_i, MO_8, tcg_gen_gvec_rotri)
TRANS(vrotri_h, gvec_vv_i, MO_16, tcg_gen_gvec_rotri)
TRANS(vrotri_w, gvec_vv_i, MO_32, tcg_gen_gvec_rotri)
TRANS(vrotri_d, gvec_vv_i, MO_64, tcg_gen_gvec_rotri)
36 changes: 36 additions & 0 deletions target/loongarch/insns.decode
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Original file line number Diff line number Diff line change
Expand Up @@ -803,3 +803,39 @@ vandi_b 0111 00111101 00 ........ ..... ..... @vv_ui8
vori_b 0111 00111101 01 ........ ..... ..... @vv_ui8
vxori_b 0111 00111101 10 ........ ..... ..... @vv_ui8
vnori_b 0111 00111101 11 ........ ..... ..... @vv_ui8

vsll_b 0111 00001110 10000 ..... ..... ..... @vvv
vsll_h 0111 00001110 10001 ..... ..... ..... @vvv
vsll_w 0111 00001110 10010 ..... ..... ..... @vvv
vsll_d 0111 00001110 10011 ..... ..... ..... @vvv
vslli_b 0111 00110010 11000 01 ... ..... ..... @vv_ui3
vslli_h 0111 00110010 11000 1 .... ..... ..... @vv_ui4
vslli_w 0111 00110010 11001 ..... ..... ..... @vv_ui5
vslli_d 0111 00110010 1101 ...... ..... ..... @vv_ui6

vsrl_b 0111 00001110 10100 ..... ..... ..... @vvv
vsrl_h 0111 00001110 10101 ..... ..... ..... @vvv
vsrl_w 0111 00001110 10110 ..... ..... ..... @vvv
vsrl_d 0111 00001110 10111 ..... ..... ..... @vvv
vsrli_b 0111 00110011 00000 01 ... ..... ..... @vv_ui3
vsrli_h 0111 00110011 00000 1 .... ..... ..... @vv_ui4
vsrli_w 0111 00110011 00001 ..... ..... ..... @vv_ui5
vsrli_d 0111 00110011 0001 ...... ..... ..... @vv_ui6

vsra_b 0111 00001110 11000 ..... ..... ..... @vvv
vsra_h 0111 00001110 11001 ..... ..... ..... @vvv
vsra_w 0111 00001110 11010 ..... ..... ..... @vvv
vsra_d 0111 00001110 11011 ..... ..... ..... @vvv
vsrai_b 0111 00110011 01000 01 ... ..... ..... @vv_ui3
vsrai_h 0111 00110011 01000 1 .... ..... ..... @vv_ui4
vsrai_w 0111 00110011 01001 ..... ..... ..... @vv_ui5
vsrai_d 0111 00110011 0101 ...... ..... ..... @vv_ui6

vrotr_b 0111 00001110 11100 ..... ..... ..... @vvv
vrotr_h 0111 00001110 11101 ..... ..... ..... @vvv
vrotr_w 0111 00001110 11110 ..... ..... ..... @vvv
vrotr_d 0111 00001110 11111 ..... ..... ..... @vvv
vrotri_b 0111 00101010 00000 01 ... ..... ..... @vv_ui3
vrotri_h 0111 00101010 00000 1 .... ..... ..... @vv_ui4
vrotri_w 0111 00101010 00001 ..... ..... ..... @vv_ui5
vrotri_d 0111 00101010 0001 ...... ..... ..... @vv_ui6

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