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tcg: Introduce tcg_target_has_memory_bswap 
Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro
with a function with a memop argument.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed May 16, 2023
1 parent acde61c commit c2be4f7
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Showing 22 changed files with 63 additions and 26 deletions.
5 changes: 5 additions & 0 deletions tcg/aarch64/tcg-target.c.inc
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Expand Up @@ -1595,6 +1595,11 @@ typedef struct {
TCGType index_ext;
} HostAddress;

bool tcg_target_has_memory_bswap(MemOp memop)
{
return false;
}

static const TCGLdstHelperParam ldst_helper_param = {
.ntmp = 1, .tmp = { TCG_REG_TMP }
};
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1 change: 0 additions & 1 deletion tcg/aarch64/tcg-target.h
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Expand Up @@ -154,7 +154,6 @@ extern bool have_lse2;
#define TCG_TARGET_HAS_cmpsel_vec 0

#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
#define TCG_TARGET_NEED_LDST_LABELS
#define TCG_TARGET_NEED_POOL_LABELS

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5 changes: 5 additions & 0 deletions tcg/arm/tcg-target.c.inc
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Expand Up @@ -1325,6 +1325,11 @@ typedef struct {
bool index_scratch;
} HostAddress;

bool tcg_target_has_memory_bswap(MemOp memop)
{
return false;
}

static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg)
{
/* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */
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1 change: 0 additions & 1 deletion tcg/arm/tcg-target.h
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Expand Up @@ -150,7 +150,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_cmpsel_vec 0

#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 0
#define TCG_TARGET_NEED_LDST_LABELS
#define TCG_TARGET_NEED_POOL_LABELS

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5 changes: 5 additions & 0 deletions tcg/i386/tcg-target.c.inc
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Expand Up @@ -1776,6 +1776,11 @@ typedef struct {
int seg;
} HostAddress;

bool tcg_target_has_memory_bswap(MemOp memop)
{
return have_movbe;
}

/*
* Because i686 has no register parameters and because x86_64 has xchg
* to handle addr/data register overlap, we have placed all input arguments
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3 changes: 0 additions & 3 deletions tcg/i386/tcg-target.h
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Expand Up @@ -240,9 +240,6 @@ extern bool have_atomic16;
#include "tcg/tcg-mo.h"

#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)

#define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe

#define TCG_TARGET_NEED_LDST_LABELS
#define TCG_TARGET_NEED_POOL_LABELS

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5 changes: 5 additions & 0 deletions tcg/loongarch64/tcg-target.c.inc
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Expand Up @@ -828,6 +828,11 @@ typedef struct {
TCGReg index;
} HostAddress;

bool tcg_target_has_memory_bswap(MemOp memop)
{
return false;
}

/*
* For softmmu, perform the TLB load and compare.
* For useronly, perform any required alignment tests.
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2 changes: 0 additions & 2 deletions tcg/loongarch64/tcg-target.h
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Expand Up @@ -173,6 +173,4 @@ typedef enum {

#define TCG_TARGET_NEED_LDST_LABELS

#define TCG_TARGET_HAS_MEMORY_BSWAP 0

#endif /* LOONGARCH_TCG_TARGET_H */
5 changes: 5 additions & 0 deletions tcg/mips/tcg-target.c.inc
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Expand Up @@ -1141,6 +1141,11 @@ typedef struct {
MemOp align;
} HostAddress;

bool tcg_target_has_memory_bswap(MemOp memop)
{
return false;
}

/*
* For softmmu, perform the TLB load and compare.
* For useronly, perform any required alignment tests.
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2 changes: 0 additions & 2 deletions tcg/mips/tcg-target.h
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Expand Up @@ -205,8 +205,6 @@ extern bool use_mips32r2_instructions;
#endif

#define TCG_TARGET_DEFAULT_MO 0
#define TCG_TARGET_HAS_MEMORY_BSWAP 0

#define TCG_TARGET_NEED_LDST_LABELS

#endif
5 changes: 5 additions & 0 deletions tcg/ppc/tcg-target.c.inc
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Expand Up @@ -2017,6 +2017,11 @@ typedef struct {
TCGReg index;
} HostAddress;

bool tcg_target_has_memory_bswap(MemOp memop)
{
return true;
}

/*
* For softmmu, perform the TLB load and compare.
* For useronly, perform any required alignment tests.
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1 change: 0 additions & 1 deletion tcg/ppc/tcg-target.h
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Expand Up @@ -179,7 +179,6 @@ extern bool have_vsx;
#define TCG_TARGET_HAS_cmpsel_vec 0

#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
#define TCG_TARGET_NEED_LDST_LABELS
#define TCG_TARGET_NEED_POOL_LABELS

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5 changes: 5 additions & 0 deletions tcg/riscv/tcg-target.c.inc
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Expand Up @@ -853,6 +853,11 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
tcg_debug_assert(ok);
}

bool tcg_target_has_memory_bswap(MemOp memop)
{
return false;
}

/* We have three temps, we might as well expose them. */
static const TCGLdstHelperParam ldst_helper_param = {
.ntmp = 3, .tmp = { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 }
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2 changes: 0 additions & 2 deletions tcg/riscv/tcg-target.h
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Expand Up @@ -168,6 +168,4 @@ typedef enum {
#define TCG_TARGET_NEED_LDST_LABELS
#define TCG_TARGET_NEED_POOL_LABELS

#define TCG_TARGET_HAS_MEMORY_BSWAP 0

#endif
5 changes: 5 additions & 0 deletions tcg/s390x/tcg-target.c.inc
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Expand Up @@ -1574,6 +1574,11 @@ typedef struct {
int disp;
} HostAddress;

bool tcg_target_has_memory_bswap(MemOp memop)
{
return true;
}

static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
HostAddress h)
{
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2 changes: 0 additions & 2 deletions tcg/s390x/tcg-target.h
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Expand Up @@ -172,8 +172,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF

#define TCG_TARGET_HAS_MEMORY_BSWAP 1

#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
#define TCG_TARGET_NEED_LDST_LABELS
#define TCG_TARGET_NEED_POOL_LABELS
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5 changes: 5 additions & 0 deletions tcg/sparc64/tcg-target.c.inc
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Expand Up @@ -1011,6 +1011,11 @@ typedef struct {
TCGReg index;
} HostAddress;

bool tcg_target_has_memory_bswap(MemOp memop)
{
return true;
}

/*
* For softmmu, perform the TLB load and compare.
* For useronly, perform any required alignment tests.
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1 change: 0 additions & 1 deletion tcg/sparc64/tcg-target.h
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Expand Up @@ -154,7 +154,6 @@ extern bool use_vis3_instructions;
#define TCG_AREG0 TCG_REG_I0

#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
#define TCG_TARGET_NEED_LDST_LABELS
#define TCG_TARGET_NEED_POOL_LABELS

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2 changes: 2 additions & 0 deletions tcg/tcg-internal.h
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Expand Up @@ -126,4 +126,6 @@ static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t)
return temp_tcgv_i64(tcgv_i128_temp(t) + o);
}

bool tcg_target_has_memory_bswap(MemOp memop);

#endif /* TCG_INTERNAL_H */
20 changes: 11 additions & 9 deletions tcg/tcg-op.c
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Expand Up @@ -2959,7 +2959,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
oi = make_memop_idx(memop, idx);

orig_memop = memop;
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) {
memop &= ~MO_BSWAP;
/* The bswap primitive benefits from zero-extended input. */
if ((memop & MO_SSIZE) == MO_SW) {
Expand Down Expand Up @@ -2996,7 +2996,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
memop = tcg_canonicalize_memop(memop, 0, 1);
oi = make_memop_idx(memop, idx);

if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) {
swap = tcg_temp_ebb_new_i32();
switch (memop & MO_SIZE) {
case MO_16:
Expand Down Expand Up @@ -3045,7 +3045,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
oi = make_memop_idx(memop, idx);

orig_memop = memop;
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) {
memop &= ~MO_BSWAP;
/* The bswap primitive benefits from zero-extended input. */
if ((memop & MO_SIGN) && (memop & MO_SIZE) < MO_64) {
Expand Down Expand Up @@ -3091,7 +3091,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
memop = tcg_canonicalize_memop(memop, 1, 1);
oi = make_memop_idx(memop, idx);

if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
if ((memop & MO_BSWAP) && !tcg_target_has_memory_bswap(memop)) {
swap = tcg_temp_ebb_new_i64();
switch (memop & MO_SIZE) {
case MO_16:
Expand Down Expand Up @@ -3157,11 +3157,6 @@ static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig)
tcg_debug_assert((orig & MO_SIZE) == MO_128);
tcg_debug_assert((orig & MO_SIGN) == 0);

/* Use a memory ordering implemented by the host. */
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (orig & MO_BSWAP)) {
mop_1 &= ~MO_BSWAP;
}

/* Reduce the size to 64-bit. */
mop_1 = (mop_1 & ~MO_SIZE) | MO_64;

Expand Down Expand Up @@ -3191,6 +3186,13 @@ static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig)
default:
g_assert_not_reached();
}

/* Use a memory ordering implemented by the host. */
if ((orig & MO_BSWAP) && !tcg_target_has_memory_bswap(mop_1)) {
mop_1 &= ~MO_BSWAP;
mop_2 &= ~MO_BSWAP;
}

ret[0] = mop_1;
ret[1] = mop_2;
}
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5 changes: 5 additions & 0 deletions tcg/tci/tcg-target.c.inc
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Expand Up @@ -963,3 +963,8 @@ static void tcg_target_init(TCGContext *s)
static inline void tcg_target_qemu_prologue(TCGContext *s)
{
}

bool tcg_target_has_memory_bswap(MemOp memop)
{
return true;
}
2 changes: 0 additions & 2 deletions tcg/tci/tcg-target.h
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Expand Up @@ -176,6 +176,4 @@ typedef enum {
We prefer consistency across hosts on this. */
#define TCG_TARGET_DEFAULT_MO (0)

#define TCG_TARGET_HAS_MEMORY_BSWAP 1

#endif /* TCG_TARGET_H */

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