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target/i386: ignore CPL0-specific features in user mode emulation 
Features such as PCID are only accessible through privileged operations,
and therefore have no impact on any user-mode operation.  Allow reporting
them to programs running under user mode emulation, so that "-cpu" can be
used with more named CPU models.

XSAVES would be similar, but it doesn't make sense to provide it until
XSAVEC is implemented.

With this change, all CPUs up to Broadwell-v4 can be emulate.  Skylake-Client
requires XSAVEC, while EPYC also requires SHA-NI, MISALIGNSSE and TOPOEXT.
MISALIGNSSE is not hard to implement, but I am not sure it is worth using
a precious hflags bit for it.

Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1534
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@bonzini
bonzini committed Jun 29, 2023
1 parent 9fb4f5f commit d903259
Showing 1 changed file with 76 additions and 7 deletions.
83 changes: 76 additions & 7 deletions target/i386/cpu.c
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Expand Up @@ -623,13 +623,25 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
/* missing:
CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */

/*
* Kernel-only features that can be shown to usermode programs even if
* they aren't actually supported by TCG, because qemu-user only runs
* in CPL=3; remove them if they are ever implemented for system emulation.
*/
#if defined CONFIG_USER_ONLY
#define CPUID_EXT_KERNEL_FEATURES (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER | \
CPUID_EXT_X2APIC)
#else
#define CPUID_EXT_KERNEL_FEATURES 0
#endif
#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \
CPUID_EXT_FMA)
CPUID_EXT_FMA | CPUID_EXT_KERNEL_FEATURES)
/* missing:
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
Expand All @@ -642,22 +654,63 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_EXT2_X86_64_FEATURES 0
#endif

/*
* CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable
* in usermode or by 32-bit programs. Those are added to supported
* TCG features unconditionally in user-mode emulation mode. This may
* indeed seem strange or incorrect, but it works because code running
* under usermode emulation cannot access them.
*
* Even for long mode, qemu-i386 is not running "a userspace program on a
* 32-bit CPU"; it's running "a userspace program with a 32-bit code segment"
* and therefore using the 32-bit ABI; the CPU itself might be 64-bit
* but again the difference is only visible in kernel mode.
*/
#if defined CONFIG_USER_ONLY
#define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR
#else
#define CPUID_EXT2_KERNEL_FEATURES 0
#endif

#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES)
CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \
CPUID_EXT2_KERNEL_FEATURES)

#if defined CONFIG_USER_ONLY
#define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW
#else
#define CPUID_EXT3_KERNEL_FEATURES 0
#endif

#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
CPUID_EXT3_3DNOWPREFETCH)
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES)

#define TCG_EXT4_FEATURES 0

#if defined CONFIG_USER_ONLY
#define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI)
#else
#define CPUID_SVM_KERNEL_FEATURES 0
#endif
#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
CPUID_SVM_SVME_ADDR_CHK)
CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES)

#define TCG_KVM_FEATURES 0

#if defined CONFIG_USER_ONLY
#define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID
#else
#define CPUID_7_0_EBX_KERNEL_FEATURES 0
#endif
#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED)
CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \
CPUID_7_0_EBX_KERNEL_FEATURES)
/* missing:
CPUID_7_0_EBX_HLE
CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
Expand All @@ -672,7 +725,14 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \
TCG_7_0_ECX_RDPID)

#define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
#if defined CONFIG_USER_ONLY
#define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \
CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD)
#else
#define CPUID_7_0_EDX_KERNEL_FEATURES 0
#endif
#define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES)

#define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
CPUID_7_1_EAX_FSRC)
#define TCG_7_1_EDX_FEATURES 0
Expand All @@ -686,8 +746,17 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_SGX_12_0_EBX_FEATURES 0
#define TCG_SGX_12_1_EAX_FEATURES 0

#if defined CONFIG_USER_ONLY
#define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \
CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \
CPUID_8000_0008_EBX_AMD_PSFD)
#else
#define CPUID_8000_0008_EBX_KERNEL_FEATURES 0
#endif

#define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \
CPUID_8000_0008_EBX_WBNOINVD)
CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES)

FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_1_EDX] = {
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