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Merge tag 'pull-loongarch-20230526' of https://gitlab.com/gaosong/qemu … 
…into staging

pull-loongarch-20230526

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* tag 'pull-loongarch-20230526' of https://gitlab.com/gaosong/qemu:
  target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredump
  target/loongarch: Fix LD/ST{LE/GT} instructions get wrong CSR_ERA and CSR_BADV

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@rth7680
rth7680 committed May 26, 2023
2 parents 9cb47a1 + 65bfaaa commit f9bdb38
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Showing 3 changed files with 31 additions and 16 deletions.
2 changes: 1 addition & 1 deletion target/loongarch/cpu.c
View file
Expand Up @@ -187,10 +187,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
case EXCCODE_IPE:
case EXCCODE_FPD:
case EXCCODE_FPE:
case EXCCODE_BCE:
case EXCCODE_SXD:
env->CSR_BADV = env->pc;
QEMU_FALLTHROUGH;
case EXCCODE_BCE:
case EXCCODE_ADEM:
case EXCCODE_PIL:
case EXCCODE_PIS:
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39 changes: 26 additions & 13 deletions target/loongarch/insn_trans/trans_lsx.c.inc
View file
Expand Up @@ -3963,106 +3963,119 @@ TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d)

static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
tcg_gen_st8_i64(cpu_gpr[a->rj], cpu_env,
tcg_gen_st8_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm)));
return true;
}

static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
tcg_gen_st16_i64(cpu_gpr[a->rj], cpu_env,
tcg_gen_st16_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm)));
return true;
}

static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
tcg_gen_st32_i64(cpu_gpr[a->rj], cpu_env,
tcg_gen_st32_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm)));
return true;
}

static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;
tcg_gen_st_i64(cpu_gpr[a->rj], cpu_env,
tcg_gen_st_i64(src, cpu_env,
offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm)));
return true;
}

static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
tcg_gen_ld8s_i64(cpu_gpr[a->rd], cpu_env,
tcg_gen_ld8s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}

static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
tcg_gen_ld16s_i64(cpu_gpr[a->rd], cpu_env,
tcg_gen_ld16s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
return true;
}

static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
tcg_gen_ld32s_i64(cpu_gpr[a->rd], cpu_env,
tcg_gen_ld32s_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
return true;
}

static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env,
tcg_gen_ld_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
return true;
}

static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
tcg_gen_ld8u_i64(cpu_gpr[a->rd], cpu_env,
tcg_gen_ld8u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));
return true;
}

static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
tcg_gen_ld16u_i64(cpu_gpr[a->rd], cpu_env,
tcg_gen_ld16u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));
return true;
}

static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
tcg_gen_ld32u_i64(cpu_gpr[a->rd], cpu_env,
tcg_gen_ld32u_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));
return true;
}

static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)
{
TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);
CHECK_SXE;
tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env,
tcg_gen_ld_i64(dst, cpu_env,
offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));
return true;
}

static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
CHECK_SXE;

tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
16, ctx->vl/8, cpu_gpr[a->rj]);
16, ctx->vl/8, src);
return true;
}

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6 changes: 4 additions & 2 deletions target/loongarch/op_helper.c
View file
Expand Up @@ -49,14 +49,16 @@ target_ulong helper_bitswap(target_ulong v)
void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj > rk) {
do_raise_exception(env, EXCCODE_BCE, 0);
env->CSR_BADV = rj;
do_raise_exception(env, EXCCODE_BCE, GETPC());
}
}

void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
{
if (rj <= rk) {
do_raise_exception(env, EXCCODE_BCE, 0);
env->CSR_BADV = rj;
do_raise_exception(env, EXCCODE_BCE, GETPC());
}
}

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