Commits on Aug 11, 2023

1. target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids() …

   cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write
   a target_ulong val, i.e. a 64 bit field in a 64 bit host.
   
   Given that we're passing a pointer to the mvendorid field, the reg is
   reading 64 bits starting from mvendorid and going 32 bits in the next
   field, marchid. Here's an example:
   
   $ ./qemu-system-riscv64 -machine virt,accel=kvm -m 2G -smp 1 \
      -cpu rv64,marchid=0xab,mvendorid=0xcd,mimpid=0xef(...)
   
   (inside the guest)
    # cat /proc/cpuinfo
   processor	: 0
   hart		: 0
   isa		: rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc
   mmu		: sv57
   mvendorid	: 0xab000000cd
   marchid		: 0xab
   mimpid		: 0xef
   
   'mvendorid' was written as a combination of 0xab (the value from the
   adjacent field, marchid) and its intended value 0xcd.
   
   Fix it by assigning cpu->cfg.mvendorid to a target_ulong var 'reg' and
   use it as input for kvm_set_one_reg(). Here's the result with this patch
   applied and using the same QEMU command line:
   
    # cat /proc/cpuinfo
   processor	: 0
   hart		: 0
   isa		: rv64imafdc_zicbom_zicboz_zihintpause_zbb_sstc
   mmu		: sv57
   mvendorid	: 0xcd
   marchid		: 0xab
   mimpid		: 0xef
   
   This bug affects only the generic (rv64) CPUs when running with KVM in a
   64 bit env since the 'host' CPU does not allow the machine IDs to be
   changed via command line.
   
   Fixes: 1fb5a62 ("target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs")
   Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
   Acked-by: Alistair Francis <alistair.francis@wdc.com>
   Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
   Message-ID: <20230802180058.281385-1-dbarboza@ventanamicro.com>
   Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

   

   danielhb authored and alistair23 committed Aug 11, 2023
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2. hw/riscv/virt.c: change 'aclint' TCG check …

   The 'aclint' property is being conditioned with tcg acceleration in
   virt_machine_class_init(). But acceleration code starts later than the
   class init of the board, meaning that tcg_enabled() will be always be
   false during class_init(), and the option is never being declared even
   when declaring TCG accel:
   
   $ ./build/qemu-system-riscv64 -M virt,accel=tcg,aclint=on
   qemu-system-riscv64: Property 'virt-machine.aclint' not found
   
   Fix it by moving the check from class_init() to machine_init(). Tune the
   description to mention that the option is TCG only.
   
   Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
   Fixes: c0716c8 ("hw/riscv/virt: Restrict ACLINT to TCG")
   Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1823
   Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
   Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
   Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
   Message-ID: <20230811160224.440697-2-dbarboza@ventanamicro.com>
   Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

   

   danielhb authored and alistair23 committed Aug 11, 2023
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3. Merge tag 'pull-riscv-to-apply-20230811-3' of https://github.com/alis… …

   …tair23/qemu into staging
   
   Sixth RISC-V PR for 8.1
   
   This is a last minute PR for RISC-V.
   
   The main goal is to fix
   https://gitlab.com/qemu-project/qemu/-/issues/1823
   which is a regression that means the aclint option
   cannot be enabled.
   
   While we are here we also fixup KVM issue.
   
    * KVM: fix mvendorid size
    * Fixup aclint check
   
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   # gpg: Signature made Fri 11 Aug 2023 11:23:41 AM PDT
   # gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
   # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
   # gpg: WARNING: This key is not certified with a trusted signature!
   # gpg:          There is no indication that the signature belongs to the owner.
   # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013
   
   * tag 'pull-riscv-to-apply-20230811-3' of https://github.com/alistair23/qemu:
     hw/riscv/virt.c: change 'aclint' TCG check
     target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()
   
   Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

   

   rth7680 committed Aug 11, 2023
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