Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: qemu/qemu
base: c586691e6762
Choose a base ref
...
head repository: qemu/qemu
compare: 4ebc33f3f3b6
Choose a head ref
  • 13 commits
  • 18 files changed
  • 5 contributors

Commits on May 2, 2023

  1. softmmu: Tidy dirtylimit_dirty_ring_full_time 

    Drop inline marker: let compiler decide.

Change return type to uint64_t: this matches the computation in the
return statement and the local variable assignment in the caller.

Rename local to dirty_ring_size_MB to fix typo.
Simplify conversion to MiB via qemu_target_page_bits and right shift.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @rth7680
    rth7680 committed May 2, 2023
    Copy the full SHA
    6a6447f View commit details
    Browse the repository at this point in the history

  2. accel/tcg: Uncache the host address for instruction fetch when tlb si… 

    …ze < 1

When PMP entry overlap part of the page, we'll set the tlb_size to 1, which
will make the address in tlb entry set with TLB_INVALID_MASK, and the next
access will again go through tlb_fill.However, this way will not work in
tb_gen_code() => get_page_addr_code_hostp(): the TLB host address will be
cached, and the following instructions can use this host address directly
which may lead to the bypass of PMP related check.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1542.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230422130329.23555-6-liweiwei@iscas.ac.cn>
    @rth7680
    Weiwei Li authored and rth7680 committed May 2, 2023
    Copy the full SHA
    ac01ec6 View commit details
    Browse the repository at this point in the history

  3. qemu/bitops.h: Limit rotate amounts 

    Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.)  This fixes a problem with riscv
vector rotate instructions.

Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
[rth: Mask shifts in both directions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @dickonthree @rth7680
    dickonthree authored and rth7680 committed May 2, 2023
    Copy the full SHA
    8841c81 View commit details
    Browse the repository at this point in the history

  4. qemu/host-utils.h: Add clz and ctz functions for lower-bit integers 

    This is for use in the RISC-V vclz and vctz instructions (implemented in
proceeding commit).

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-11-lawrence.hunter@codethink.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @CardboardTurkey @rth7680
    CardboardTurkey authored and rth7680 committed May 2, 2023
    Copy the full SHA
    31fe256 View commit details
    Browse the repository at this point in the history

  5. tcg: Add tcg_gen_gvec_andcs 

    Add tcg expander and helper functions for and-compliment
vector with scalar operand.

Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk>
[rth: Split out of larger patch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @nazar-codethink @rth7680
    nazar-codethink authored and rth7680 committed May 2, 2023
    Copy the full SHA
    4221aa4 View commit details
    Browse the repository at this point in the history

  6. tcg: Add tcg_gen_gvec_rotrs 

    Add tcg expander and helper functions for rotate right
vector with scalar operand.

Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk>
[rth: Split out of larger patch; mask rotation count.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @nazar-codethink @rth7680
    nazar-codethink authored and rth7680 committed May 2, 2023
    Copy the full SHA
    bef317d View commit details
    Browse the repository at this point in the history

  7. qemu/int128: Re-shuffle Int128Alias members 

    Clang 14, with --enable-tcg-interpreter errors with

include/qemu/int128.h:487:16: error: alignment of field 'i' (128 bits)
  does not match the alignment of the first field in transparent union;
  transparent_union attribute ignored [-Werror,-Wignored-attributes]
    __int128_t i;
               ^
include/qemu/int128.h:486:12: note: alignment of first field is 64 bits
    Int128 s;
           ^
1 error generated.

By placing the __uint128_t member first, this is avoided.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230501204625.277361-1-richard.henderson@linaro.org>
    @rth7680
    rth7680 committed May 2, 2023
    Copy the full SHA
    c407535 View commit details
    Browse the repository at this point in the history

  8. migration/xbzrle: Use __attribute__((target)) for avx512 

    Use the attribute, which is supported by clang, instead of
the #pragma, which is not supported and, for some reason,
also not detected by the meson probe, so we fail by -Werror.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20230501210555.289806-1-richard.henderson@linaro.org>
    @rth7680
    rth7680 committed May 2, 2023
    Copy the full SHA
    dc165fc View commit details
    Browse the repository at this point in the history

  9. accel/tcg: Add cpu_ld*_code_mmu 

    At least RISC-V has the need to be able to perform a read
using execute permissions, outside of translation.
Add helpers to facilitate this.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-9-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-9-richard.henderson@linaro.org>
    @rth7680
    rth7680 committed May 2, 2023
    Copy the full SHA
    2899062 View commit details
    Browse the repository at this point in the history

  10. tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 

    Since TCG_TYPE_I32 values are kept sign-extended in registers,
via ".w" instructions, we need not extend if the register matches.
This is already relied upon by comparisons.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @rth7680
    rth7680 committed May 2, 2023
    Copy the full SHA
    341ac0a View commit details
    Browse the repository at this point in the history

  11. tcg/mips: Conditionalize tcg_out_exts_i32_i64 

    Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not
extend if the register matches.  This is already relied upon by comparisons.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @rth7680
    rth7680 committed May 2, 2023
    Copy the full SHA
    c6a9861 View commit details
    Browse the repository at this point in the history

  12. tcg: Introduce tcg_out_movext2 

    This is common code in most qemu_{ld,st} slow paths, moving two
registers when there may be overlap between sources and destinations.
At present, this is only used by 32-bit hosts for 64-bit data,
but will shortly be used for more than that.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @rth7680
    rth7680 committed May 2, 2023
    Copy the full SHA
    129f1f9 View commit details
    Browse the repository at this point in the history

  13. Merge tag 'pull-tcg-20230502-2' of https://gitlab.com/rth7680/qemu in… 

    …to staging

Misc tcg-related patch queue.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmRRb30dHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+obAgAmL4F1gdkbUUPKnkv
# poYwutCX+c3kog22TF29BlKgC8vJa6UbRLMphz5q7v3wbCKQJMeNV/sKa+mhnHBK
# CB3wP8xXVAahWFARmWTIZEqlB3HQ/RIzhc5saKkiSzcGIrtXUj6fdfrz7mae+w/g
# kDGCbK8hGyuE580j9QAIPbpfqPoNhIPziECFA1AsNf5Krpxc1nDqIfZEuUzTLtLO
# 1WoSaUVbiGDQrTe2OVKF2mtrGbr2vWI1vnHJl67Lom6rG0LzOjb3W/8IN+n0+46E
# 7pMlUCDT1zeTxevRxBvDmwgCYA/QjFosd4enUuhVReTxTNhUc69+QyuOAhHO/IEq
# T0V3eA==
# =qZDQ
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 02 May 2023 09:15:57 PM BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230502-2' of https://gitlab.com/rth7680/qemu:
  tcg: Introduce tcg_out_movext2
  tcg/mips: Conditionalize tcg_out_exts_i32_i64
  tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
  accel/tcg: Add cpu_ld*_code_mmu
  migration/xbzrle: Use __attribute__((target)) for avx512
  qemu/int128: Re-shuffle Int128Alias members
  tcg: Add tcg_gen_gvec_rotrs
  tcg: Add tcg_gen_gvec_andcs
  qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
  qemu/bitops.h: Limit rotate amounts
  accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
  softmmu: Tidy dirtylimit_dirty_ring_full_time

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    @rth7680
    rth7680 committed May 2, 2023
    Copy the full SHA
    4ebc33f View commit details
    Browse the repository at this point in the history