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base repository: qemu/qemu
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  • 4 commits
  • 4 files changed
  • 2 contributors

Commits on May 11, 2023

  1. target/openrisc: Allow fpcsr access in user mode

    As per OpenRISC spec 1.4 FPCSR can be read and written in user mode.
    
    Update mtspr and mfspr helpers to support this by moving the is_user
    check into the helper.
    
    Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
    Signed-off-by: Stafford Horne <shorne@gmail.com>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    stffrdhrn committed May 11, 2023
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  2. target/openrisc: Set PC to cpu state on FPU exception

    Store the PC to ensure the correct value can be read in the exception
    handler.
    
    Signed-off-by: Stafford Horne <shorne@gmail.com>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    stffrdhrn committed May 11, 2023
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  3. target/openrisc: Setup FPU for detecting tininess before rounding

    OpenRISC defines tininess to be detected before rounding.  Setup qemu to
    obey this.
    
    Signed-off-by: Stafford Horne <shorne@gmail.com>
    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
    stffrdhrn committed May 11, 2023
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Commits on May 13, 2023

  1. Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhr…

    …n/qemu into staging
    
    OpenRISC FPU Updates for 8.1
    
    A few fixes and updates to bring OpenRISC inline with the latest
    architecture spec updates:
    
     - Allow FPCSR to be accessed in user mode
     - Select tininess detection before rounding
     - Fix FPE Exception PC value
    
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    * tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu:
      target/openrisc: Setup FPU for detecting tininess before rounding
      target/openrisc: Set PC to cpu state on FPU exception
      target/openrisc: Allow fpcsr access in user mode
    
    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    rth7680 committed May 13, 2023
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