80 changes: 44 additions & 36 deletions hw/ide/core.c
View file
Expand Up @@ -24,6 +24,7 @@
*/

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "migration/vmstate.h"
#include "qemu/error-report.h"
Expand Down Expand Up @@ -653,7 +654,7 @@ void ide_set_sector(IDEState *s, int64_t sector_num)

static void ide_rw_error(IDEState *s) {
ide_abort_command(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}

static void ide_buffered_readv_cb(void *opaque, int ret)
Expand Down Expand Up @@ -772,7 +773,7 @@ static void ide_sector_read_cb(void *opaque, int ret)
s->nsector -= n;
/* Allow the guest to read the io_buffer */
ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}

static void ide_sector_read(IDEState *s)
Expand Down Expand Up @@ -836,7 +837,7 @@ void ide_dma_error(IDEState *s)
dma_buf_commit(s, 0);
ide_abort_command(s);
ide_set_inactive(s, false);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}

int ide_handle_rw_error(IDEState *s, int error, int op)
Expand Down Expand Up @@ -906,7 +907,7 @@ static void ide_dma_cb(void *opaque, int ret)
/* end of transfer ? */
if (s->nsector == 0) {
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
goto eot;
}

Expand Down Expand Up @@ -1006,7 +1007,7 @@ static void ide_sector_write(IDEState *s);
static void ide_sector_write_timer_cb(void *opaque)
{
IDEState *s = opaque;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}

static void ide_sector_write_cb(void *opaque, int ret)
Expand Down Expand Up @@ -1054,7 +1055,7 @@ static void ide_sector_write_cb(void *opaque, int ret)
timer_mod(s->sector_write_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(NANOSECONDS_PER_SECOND / 1000));
} else {
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
}

Expand Down Expand Up @@ -1105,7 +1106,7 @@ static void ide_flush_cb(void *opaque, int ret)
}
s->status = READY_STAT | SEEK_STAT;
ide_cmd_done(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}

static void ide_flush_cache(IDEState *s)
Expand Down Expand Up @@ -1194,7 +1195,7 @@ static void ide_cd_change_cb(void *opaque, bool load, Error **errp)
s->cdrom_changed = 1;
s->events.new_media = true;
s->events.eject_request = false;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}

static void ide_cd_eject_request_cb(void *opaque, bool force)
Expand All @@ -1205,7 +1206,7 @@ static void ide_cd_eject_request_cb(void *opaque, bool force)
if (force) {
s->tray_locked = false;
}
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}

static void ide_cmd_lba48_transform(IDEState *s, int lba48)
Expand Down Expand Up @@ -1264,7 +1265,7 @@ const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {
void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
int reg_num = addr & 7;

trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);
Expand Down Expand Up @@ -1326,7 +1327,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
case ATA_IOPORT_WR_COMMAND:
ide_clear_hob(bus);
qemu_irq_lower(bus->irq);
ide_exec_cmd(bus, val);
ide_bus_exec_cmd(bus, val);
break;
}
}
Expand Down Expand Up @@ -1439,7 +1440,7 @@ static bool cmd_identify(IDEState *s, uint8_t cmd)
}
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
} else {
if (s->drive_kind == IDE_CD) {
Expand Down Expand Up @@ -1629,7 +1630,7 @@ static bool cmd_specify(IDEState *s, uint8_t cmd)
if (s->blk && s->drive_kind != IDE_CD) {
s->heads = (s->select & (ATA_DEV_HS)) + 1;
s->sectors = s->nsector;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
} else {
ide_abort_command(s);
}
Expand Down Expand Up @@ -1730,7 +1731,7 @@ static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
ide_atapi_identify(s);
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;
}

Expand All @@ -1755,7 +1756,7 @@ static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
* They are part of the regular output (this is why ERR_STAT isn't set)
* Device 0 passed, Device 1 passed or not present. */
s->error = 0x01;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}

return false;
Expand Down Expand Up @@ -1787,7 +1788,7 @@ static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
{
s->error = 0x09; /* miscellaneous error */
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);

return false;
}
Expand Down Expand Up @@ -1826,7 +1827,7 @@ static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
s->io_buffer[0x1a] = 0x01; /* Hot count */

ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);

return false;
}
Expand All @@ -1850,7 +1851,7 @@ static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)

ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
s->status = 0x00; /* NOTE: READY is _not_ set */
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);

return false;
}
Expand Down Expand Up @@ -1933,7 +1934,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)

s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;

case SMART_READ_DATA:
Expand Down Expand Up @@ -1974,7 +1975,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)

s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;

case SMART_READ_LOG:
Expand Down Expand Up @@ -2013,7 +2014,7 @@ static bool cmd_smart(IDEState *s, uint8_t cmd)
}
s->status = READY_STAT | SEEK_STAT;
ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return false;

case SMART_EXECUTE_OFFLINE:
Expand Down Expand Up @@ -2122,13 +2123,13 @@ static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
&& (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
}

void ide_exec_cmd(IDEBus *bus, uint32_t val)
void ide_bus_exec_cmd(IDEBus *bus, uint32_t val)
{
IDEState *s;
bool complete;

s = idebus_active_if(bus);
trace_ide_exec_cmd(bus, s, val);
s = ide_bus_active_if(bus);
trace_ide_bus_exec_cmd(bus, s, val);

/* ignore commands to non existent slave */
if (s != bus->ifs && !s->blk) {
Expand All @@ -2145,7 +2146,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)

if (!ide_cmd_permitted(s, val)) {
ide_abort_command(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
return;
}

Expand All @@ -2163,7 +2164,7 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)
}

ide_cmd_done(s);
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
}
}

Expand Down Expand Up @@ -2194,7 +2195,7 @@ const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {
uint32_t ide_ioport_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint32_t reg_num;
int ret, hob;

Expand Down Expand Up @@ -2280,7 +2281,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)
uint32_t ide_status_read(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
int ret;

if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
Expand Down Expand Up @@ -2369,7 +2370,7 @@ static bool ide_is_pio_out(IDEState *s)
void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;

trace_ide_data_writew(addr, val, bus, s);
Expand Down Expand Up @@ -2405,7 +2406,7 @@ void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
uint32_t ide_data_readw(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
int ret;

Expand Down Expand Up @@ -2443,7 +2444,7 @@ uint32_t ide_data_readw(void *opaque, uint32_t addr)
void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;

trace_ide_data_writel(addr, val, bus, s);
Expand Down Expand Up @@ -2471,7 +2472,7 @@ void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
uint32_t ide_data_readl(void *opaque, uint32_t addr)
{
IDEBus *bus = opaque;
IDEState *s = idebus_active_if(bus);
IDEState *s = ide_bus_active_if(bus);
uint8_t *p;
int ret;

Expand Down Expand Up @@ -2710,7 +2711,7 @@ static void ide_restart_bh(void *opaque)
return;
}

s = idebus_active_if(bus);
s = ide_bus_active_if(bus);
is_read = (bus->error_status & IDE_RETRY_READ) != 0;

/* The error status must be cleared before resubmitting the request: The
Expand Down Expand Up @@ -2758,7 +2759,7 @@ static void ide_restart_cb(void *opaque, bool running, RunState state)
}
}

void ide_register_restart_cb(IDEBus *bus)
void ide_bus_register_restart_cb(IDEBus *bus)
{
if (bus->dma->ops->restart_dma) {
bus->vmstate = qemu_add_vm_change_state_handler(ide_restart_cb, bus);
Expand All @@ -2770,18 +2771,25 @@ static IDEDMA ide_dma_nop = {
.aiocb = NULL,
};

void ide_init2(IDEBus *bus, qemu_irq irq)
void ide_bus_init_output_irq(IDEBus *bus, qemu_irq irq_out)
{
int i;

for(i = 0; i < 2; i++) {
ide_init1(bus, i);
ide_reset(&bus->ifs[i]);
}
bus->irq = irq;
bus->irq = irq_out;
bus->dma = &ide_dma_nop;
}

void ide_bus_set_irq(IDEBus *bus)
{
if (!(bus->cmd & IDE_CTRL_DISABLE_IRQ)) {
qemu_irq_raise(bus->irq);
}
}

void ide_exit(IDEState *s)
{
timer_free(s->sector_write_timer);
Expand Down
1 change: 1 addition & 0 deletions hw/ide/ich.c
View file
Expand Up @@ -61,6 +61,7 @@
*/

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
Expand Down
10 changes: 0 additions & 10 deletions hw/ide/ioport.c
View file
Expand Up @@ -25,16 +25,6 @@

#include "qemu/osdep.h"
#include "hw/isa/isa.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "sysemu/blockdev.h"
#include "sysemu/dma.h"
#include "hw/block/block.h"
#include "sysemu/block-backend.h"
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "sysemu/replay.h"

#include "hw/ide/internal.h"
#include "trace.h"

Expand Down
22 changes: 9 additions & 13 deletions hw/ide/isa.c
View file
Expand Up @@ -31,23 +31,20 @@
#include "qemu/module.h"
#include "sysemu/dma.h"

#include "hw/ide/isa.h"
#include "hw/ide/internal.h"
#include "qom/object.h"

/***********************************************************/
/* ISA IDE definitions */

#define TYPE_ISA_IDE "isa-ide"
OBJECT_DECLARE_SIMPLE_TYPE(ISAIDEState, ISA_IDE)

struct ISAIDEState {
ISADevice parent_obj;

IDEBus bus;
uint32_t iobase;
uint32_t iobase2;
uint32_t isairq;
qemu_irq irq;
uint32_t irqnum;
};

static void isa_ide_reset(DeviceState *d)
Expand Down Expand Up @@ -75,13 +72,12 @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp)

ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
s->irq = isa_get_irq(isadev, s->isairq);
ide_init2(&s->bus, s->irq);
ide_bus_init_output_irq(&s->bus, isa_get_irq(isadev, s->irqnum));
vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_isa, s);
ide_register_restart_cb(&s->bus);
ide_bus_register_restart_cb(&s->bus);
}

ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int irqnum,
DriveInfo *hd0, DriveInfo *hd1)
{
DeviceState *dev;
Expand All @@ -92,23 +88,23 @@ ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
dev = DEVICE(isadev);
qdev_prop_set_uint32(dev, "iobase", iobase);
qdev_prop_set_uint32(dev, "iobase2", iobase2);
qdev_prop_set_uint32(dev, "irq", isairq);
qdev_prop_set_uint32(dev, "irq", irqnum);
isa_realize_and_unref(isadev, bus, &error_fatal);

s = ISA_IDE(dev);
if (hd0) {
ide_create_drive(&s->bus, 0, hd0);
ide_bus_create_drive(&s->bus, 0, hd0);
}
if (hd1) {
ide_create_drive(&s->bus, 1, hd1);
ide_bus_create_drive(&s->bus, 1, hd1);
}
return isadev;
}

static Property isa_ide_properties[] = {
DEFINE_PROP_UINT32("iobase", ISAIDEState, iobase, 0x1f0),
DEFINE_PROP_UINT32("iobase2", ISAIDEState, iobase2, 0x3f6),
DEFINE_PROP_UINT32("irq", ISAIDEState, isairq, 14),
DEFINE_PROP_UINT32("irq", ISAIDEState, irqnum, 14),
DEFINE_PROP_END_OF_LIST(),
};

Expand Down
15 changes: 8 additions & 7 deletions hw/ide/macio.c
View file
Expand Up @@ -24,6 +24,7 @@
*/

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/ppc/mac_dbdma.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
Expand Down Expand Up @@ -59,7 +60,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
int64_t offset;

MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
Expand Down Expand Up @@ -135,7 +136,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);
int64_t offset;

MACIO_DPRINTF("pmac_ide_transfer_cb\n");
Expand All @@ -159,7 +160,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
MACIO_DPRINTF("End of IDE transfer\n");
qemu_sglist_destroy(&s->sg);
s->status = READY_STAT | SEEK_STAT;
ide_set_irq(s->bus);
ide_bus_set_irq(s->bus);
m->dma_active = false;
goto done;
}
Expand Down Expand Up @@ -219,7 +220,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
static void pmac_ide_transfer(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);

MACIO_DPRINTF("\n");

Expand Down Expand Up @@ -250,7 +251,7 @@ static void pmac_ide_transfer(DBDMA_io *io)
static void pmac_ide_flush(DBDMA_io *io)
{
MACIOIDEState *m = io->opaque;
IDEState *s = idebus_active_if(&m->bus);
IDEState *s = ide_bus_active_if(&m->bus);

if (s->bus->dma->aiocb) {
blk_drain(s->blk);
Expand Down Expand Up @@ -419,7 +420,7 @@ static void macio_ide_realizefn(DeviceState *dev, Error **errp)
{
MACIOIDEState *s = MACIO_IDE(dev);

ide_init2(&s->bus, s->ide_irq);
ide_bus_init_output_irq(&s->bus, s->ide_irq);

/* Register DMA callbacks */
s->dma.ops = &dbdma_ops;
Expand Down Expand Up @@ -500,7 +501,7 @@ void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)

for (i = 0; i < 2; i++) {
if (hd_table[i]) {
ide_create_drive(&s->bus, i, hd_table[i]);
ide_bus_create_drive(&s->bus, i, hd_table[i]);
}
}
}
Expand Down
9 changes: 5 additions & 4 deletions hw/ide/microdrive.c
View file
Expand Up @@ -29,6 +29,7 @@
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "hw/irq.h"

#include "hw/ide/internal.h"
#include "qom/object.h"
Expand Down Expand Up @@ -249,14 +250,14 @@ static uint16_t md_common_read(PCMCIACardState *card, uint32_t at)
case 0xd: /* Error */
return ide_ioport_read(&s->bus, 0x1);
case 0xe: /* Alternate Status */
ifs = idebus_active_if(&s->bus);
ifs = ide_bus_active_if(&s->bus);
if (ifs->blk) {
return ifs->status;
} else {
return 0;
}
case 0xf: /* Device Address */
ifs = idebus_active_if(&s->bus);
ifs = ide_bus_active_if(&s->bus);
return 0xc2 | ((~ifs->select << 2) & 0x3c);
default:
return ide_ioport_read(&s->bus, at);
Expand Down Expand Up @@ -565,7 +566,7 @@ PCMCIACardState *dscm1xxxx_init(DriveInfo *dinfo)
qdev_realize(DEVICE(md), NULL, &error_fatal);

if (dinfo != NULL) {
ide_create_drive(&md->bus, 0, dinfo);
ide_bus_create_drive(&md->bus, 0, dinfo);
}
md->bus.ifs[0].drive_kind = IDE_CFATA;
md->bus.ifs[0].mdata_size = METADATA_SIZE;
Expand Down Expand Up @@ -598,7 +599,7 @@ static void microdrive_realize(DeviceState *dev, Error **errp)
{
MicroDriveState *md = MICRODRIVE(dev);

ide_init2(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
ide_bus_init_output_irq(&md->bus, qemu_allocate_irq(md_set_irq, md, 0));
}

static void microdrive_init(Object *obj)
Expand Down
37 changes: 16 additions & 21 deletions hw/ide/mmio.c
View file
Expand Up @@ -29,21 +29,16 @@
#include "qemu/module.h"
#include "sysemu/dma.h"

#include "hw/ide/mmio.h"
#include "hw/ide/internal.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"

/***********************************************************/
/* MMIO based ide port
* This emulates IDE device connected directly to the CPU bus without
* dedicated ide controller, which is often seen on embedded boards.
*/

#define TYPE_MMIO_IDE "mmio-ide"
typedef struct MMIOIDEState MMIOState;
DECLARE_INSTANCE_CHECKER(MMIOState, MMIO_IDE,
TYPE_MMIO_IDE)

struct MMIOIDEState {
/*< private >*/
SysBusDevice parent_obj;
Expand All @@ -58,15 +53,15 @@ struct MMIOIDEState {

static void mmio_ide_reset(DeviceState *dev)
{
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);

ide_bus_reset(&s->bus);
}

static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
addr >>= s->shift;
if (addr & 7)
return ide_ioport_read(&s->bus, addr);
Expand All @@ -77,7 +72,7 @@ static uint64_t mmio_ide_read(void *opaque, hwaddr addr,
static void mmio_ide_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
addr >>= s->shift;
if (addr & 7)
ide_ioport_write(&s->bus, addr, val);
Expand All @@ -94,14 +89,14 @@ static const MemoryRegionOps mmio_ide_ops = {
static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr,
unsigned size)
{
MMIOState *s= opaque;
MMIOIDEState *s = opaque;
return ide_status_read(&s->bus, 0);
}

static void mmio_ide_ctrl_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
MMIOIDEState *s = opaque;
ide_ctrl_write(&s->bus, 0, val);
}

Expand All @@ -116,18 +111,18 @@ static const VMStateDescription vmstate_ide_mmio = {
.version_id = 3,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_IDE_BUS(bus, MMIOState),
VMSTATE_IDE_DRIVES(bus.ifs, MMIOState),
VMSTATE_IDE_BUS(bus, MMIOIDEState),
VMSTATE_IDE_DRIVES(bus.ifs, MMIOIDEState),
VMSTATE_END_OF_LIST()
}
};

static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
{
SysBusDevice *d = SYS_BUS_DEVICE(dev);
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);

ide_init2(&s->bus, s->irq);
ide_bus_init_output_irq(&s->bus, s->irq);

memory_region_init_io(&s->iomem1, OBJECT(s), &mmio_ide_ops, s,
"ide-mmio.1", 16 << s->shift);
Expand All @@ -140,14 +135,14 @@ static void mmio_ide_realizefn(DeviceState *dev, Error **errp)
static void mmio_ide_initfn(Object *obj)
{
SysBusDevice *d = SYS_BUS_DEVICE(obj);
MMIOState *s = MMIO_IDE(obj);
MMIOIDEState *s = MMIO_IDE(obj);

ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
sysbus_init_irq(d, &s->irq);
}

static Property mmio_ide_properties[] = {
DEFINE_PROP_UINT32("shift", MMIOState, shift, 0),
DEFINE_PROP_UINT32("shift", MMIOIDEState, shift, 0),
DEFINE_PROP_END_OF_LIST()
};

Expand All @@ -164,7 +159,7 @@ static void mmio_ide_class_init(ObjectClass *oc, void *data)
static const TypeInfo mmio_ide_type_info = {
.name = TYPE_MMIO_IDE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MMIOState),
.instance_size = sizeof(MMIOIDEState),
.instance_init = mmio_ide_initfn,
.class_init = mmio_ide_class_init,
};
Expand All @@ -176,13 +171,13 @@ static void mmio_ide_register_types(void)

void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1)
{
MMIOState *s = MMIO_IDE(dev);
MMIOIDEState *s = MMIO_IDE(dev);

if (hd0 != NULL) {
ide_create_drive(&s->bus, 0, hd0);
ide_bus_create_drive(&s->bus, 0, hd0);
}
if (hd1 != NULL) {
ide_create_drive(&s->bus, 1, hd1);
ide_bus_create_drive(&s->bus, 1, hd1);
}
}

Expand Down
11 changes: 9 additions & 2 deletions hw/ide/pci.c
View file
Expand Up @@ -24,6 +24,7 @@
*/

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "sysemu/dma.h"
Expand Down Expand Up @@ -103,6 +104,12 @@ const MemoryRegionOps pci_ide_data_le_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};

static IDEState *bmdma_active_if(BMDMAState *bmdma)
{
assert(bmdma->bus->retry_unit != (uint8_t)-1);
return bmdma->bus->ifs + bmdma->bus->retry_unit;
}

static void bmdma_start_dma(const IDEDMA *dma, IDEState *s,
BlockCompletionFunc *dma_cb)
{
Expand Down Expand Up @@ -295,7 +302,7 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
/* Ignore writes to SSBM if it keeps the old value */
if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
if (!(val & BM_CMD_START)) {
ide_cancel_dma_sync(idebus_active_if(bm->bus));
ide_cancel_dma_sync(ide_bus_active_if(bm->bus));
bm->status &= ~BM_STATUS_DMAING;
} else {
bm->cur_addr = bm->addr;
Expand Down Expand Up @@ -488,7 +495,7 @@ void pci_ide_create_devs(PCIDevice *dev)
ide_drive_get(hd_table, ARRAY_SIZE(hd_table));
for (i = 0; i < 4; i++) {
if (hd_table[i]) {
ide_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
ide_bus_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
}
}
}
Expand Down
48 changes: 21 additions & 27 deletions hw/ide/piix.c
View file
Expand Up @@ -28,14 +28,9 @@
*/

#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "sysemu/dma.h"

#include "hw/pci/pci.h"
#include "hw/ide/piix.h"
#include "hw/ide/pci.h"
#include "trace.h"
Expand Down Expand Up @@ -126,7 +121,7 @@ static void piix_ide_reset(DeviceState *dev)
pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */
}

static int pci_piix_init_ports(PCIIDEState *d)
static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp)
{
static const struct {
int iobase;
Expand All @@ -136,30 +131,29 @@ static int pci_piix_init_ports(PCIIDEState *d)
{0x1f0, 0x3f6, 14},
{0x170, 0x376, 15},
};
int i, ret;

for (i = 0; i < 2; i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
if (ret) {
return ret;
}
ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));

bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_register_restart_cb(&d->bus[i]);
int ret;

ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
port_info[i].iobase2);
if (ret) {
error_setg_errno(errp, -ret, "Failed to realize %s port %u",
object_get_typename(OBJECT(d)), i);
return false;
}
ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));

return 0;
bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_bus_register_restart_cb(&d->bus[i]);

return true;
}

static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
uint8_t *pci_conf = dev->config;
int rc;

pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode

Expand All @@ -168,10 +162,10 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)

vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);

rc = pci_piix_init_ports(d);
if (rc) {
error_setg_errno(errp, -rc, "Failed to realize %s",
object_get_typename(OBJECT(dev)));
for (unsigned i = 0; i < 2; i++) {
if (!pci_piix_init_bus(d, i, errp)) {
return;
}
}
}

Expand Down
2 changes: 1 addition & 1 deletion hw/ide/qdev.c
View file
Expand Up @@ -124,7 +124,7 @@ static void ide_qdev_realize(DeviceState *qdev, Error **errp)
dc->realize(dev, errp);
}

IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive)
IDEDevice *ide_bus_create_drive(IDEBus *bus, int unit, DriveInfo *drive)
{
DeviceState *dev;

Expand Down
4 changes: 2 additions & 2 deletions hw/ide/sii3112.c
View file
Expand Up @@ -284,11 +284,11 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
qdev_init_gpio_in(ds, sii3112_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i));
ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i));

bmdma_init(&s->bus[i], &s->bmdma[i], s);
s->bmdma[i].bus = &s->bus[i];
ide_register_restart_cb(&s->bus[i]);
ide_bus_register_restart_cb(&s->bus[i]);
}
}

Expand Down
3 changes: 2 additions & 1 deletion hw/ide/trace-events
View file
Expand Up @@ -12,7 +12,7 @@ ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s)
ide_data_readl(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO rd @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState %p"
ide_data_writel(uint32_t addr, uint32_t val, void *bus, void *s) "IDE PIO wr @ 0x%"PRIx32" (Data: Long); val 0x%08"PRIx32"; bus %p; IDEState %p"
# misc
ide_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; state %p; cmd 0x%02x"
ide_bus_exec_cmd(void *bus, void *state, uint32_t cmd) "IDE exec cmd: bus %p; state %p; cmd 0x%02x"
ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffered request %p with -ECANCELED"
ide_cancel_dma_sync_remaining(void) "draining all remaining requests"
ide_sector_read(int64_t sector_num, int nsectors) "sector=%"PRId64" nsectors=%d"
Expand Down Expand Up @@ -91,6 +91,7 @@ ahci_populate_sglist_short_map(void *s, int port) "ahci(%p)[%d]: mapped less tha
ahci_populate_sglist_bad_offset(void *s, int port, int off_idx, int64_t off_pos) "ahci(%p)[%d]: Incorrect offset! off_idx: %d, off_pos: %"PRId64
ncq_finish(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: NCQ transfer finished"
execute_ncq_command_read(void *s, int port, uint8_t tag, int count, int64_t lba) "ahci(%p)[%d][tag:%d]: NCQ reading %d sectors from LBA %"PRId64
execute_ncq_command_write(void *s, int port, uint8_t tag, int count, int64_t lba) "ahci(%p)[%d][tag:%d]: NCQ writing %d sectors to LBA %"PRId64
execute_ncq_command_unsup(void *s, int port, uint8_t tag, uint8_t cmd) "ahci(%p)[%d][tag:%d]: error: unsupported NCQ command (0x%02x) received"
process_ncq_command_mismatch(void *s, int port, uint8_t tag, uint8_t slot) "ahci(%p)[%d][tag:%d]: Warning: NCQ slot (%d) did not match the given tag"
process_ncq_command_aux(void *s, int port, uint8_t tag) "ahci(%p)[%d][tag:%d]: Warn: Attempt to use NCQ auxiliary fields"
Expand Down
16 changes: 8 additions & 8 deletions hw/ide/via.c
View file
Expand Up @@ -90,7 +90,7 @@ static void bmdma_setup_bar(PCIIDEState *d)
int i;

memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
for(i = 0;i < 2; i++) {
for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) {
BMDMAState *bm = &d->bmdma[i];

memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
Expand Down Expand Up @@ -122,7 +122,7 @@ static void via_ide_reset(DeviceState *dev)
uint8_t *pci_conf = pd->config;
int i;

for (i = 0; i < 2; i++) {
for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
ide_bus_reset(&d->bus[i]);
}

Expand Down Expand Up @@ -188,14 +188,14 @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
bmdma_setup_bar(d);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);

qdev_init_gpio_in(ds, via_ide_set_irq, 2);
for (i = 0; i < 2; i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
qdev_init_gpio_in(ds, via_ide_set_irq, ARRAY_SIZE(d->bus));
for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, MAX_IDE_DEVS);
ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));

bmdma_init(&d->bus[i], &d->bmdma[i], d);
d->bmdma[i].bus = &d->bus[i];
ide_register_restart_cb(&d->bus[i]);
ide_bus_register_restart_cb(&d->bus[i]);
}
}

Expand All @@ -204,7 +204,7 @@ static void via_ide_exitfn(PCIDevice *dev)
PCIIDEState *d = PCI_IDE(dev);
unsigned i;

for (i = 0; i < 2; ++i) {
for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) {
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
}
Expand Down
2 changes: 1 addition & 1 deletion hw/intc/apic.c
View file
Expand Up @@ -20,7 +20,7 @@
#include "qemu/thread.h"
#include "hw/i386/apic_internal.h"
#include "hw/i386/apic.h"
#include "hw/i386/ioapic.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/i8259.h"
#include "hw/intc/kvm_irqcount.h"
#include "hw/pci/msi.h"
Expand Down
4 changes: 2 additions & 2 deletions hw/intc/i8259.c
View file
Expand Up @@ -406,7 +406,7 @@ static void pic_realize(DeviceState *dev, Error **errp)
pc->parent_realize(dev, errp);
}

qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in)
{
qemu_irq *irq_set;
DeviceState *dev;
Expand All @@ -418,7 +418,7 @@ qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
isadev = i8259_init_chip(TYPE_I8259, bus, true);
dev = DEVICE(isadev);

qdev_connect_gpio_out(dev, 0, parent_irq);
qdev_connect_gpio_out(dev, 0, parent_irq_in);
for (i = 0 ; i < 8; i++) {
irq_set[i] = qdev_get_gpio_in(dev, i);
}
Expand Down
4 changes: 2 additions & 2 deletions hw/intc/ioapic.c
View file
Expand Up @@ -24,10 +24,10 @@
#include "qapi/error.h"
#include "monitor/monitor.h"
#include "hw/i386/apic.h"
#include "hw/i386/ioapic.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/i386/x86.h"
#include "hw/intc/i8259.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/ioapic_internal.h"
#include "hw/pci/msi.h"
#include "hw/qdev-properties.h"
#include "sysemu/kvm.h"
Expand Down
4 changes: 2 additions & 2 deletions hw/intc/ioapic_common.c
View file
Expand Up @@ -24,9 +24,9 @@
#include "qemu/module.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/i386/ioapic.h"
#include "hw/i386/ioapic_internal.h"
#include "hw/intc/intc.h"
#include "hw/intc/ioapic.h"
#include "hw/intc/ioapic_internal.h"
#include "hw/sysbus.h"

/* ioapic_no count start from 0 to MAX_IOAPICS,
Expand Down
8 changes: 4 additions & 4 deletions include/hw/i386/ioapic_internal.h → hw/intc/ioapic_internal.h
View file
Expand Up @@ -19,11 +19,11 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/

#ifndef QEMU_IOAPIC_INTERNAL_H
#define QEMU_IOAPIC_INTERNAL_H
#ifndef HW_INTC_IOAPIC_INTERNAL_H
#define HW_INTC_IOAPIC_INTERNAL_H

#include "exec/memory.h"
#include "hw/i386/ioapic.h"
#include "hw/intc/ioapic.h"
#include "hw/sysbus.h"
#include "qemu/notify.h"
#include "qom/object.h"
Expand Down Expand Up @@ -115,4 +115,4 @@ void ioapic_reset_common(DeviceState *dev);

void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);

#endif /* QEMU_IOAPIC_INTERNAL_H */
#endif /* HW_INTC_IOAPIC_INTERNAL_H */
19 changes: 6 additions & 13 deletions hw/isa/i82378.c
View file
Expand Up @@ -32,8 +32,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(I82378State, I82378)
struct I82378State {
PCIDevice parent_obj;

qemu_irq out[2];
qemu_irq *i8259;
qemu_irq cpu_intr;
qemu_irq *isa_irqs_in;
MemoryRegion io;
};

Expand All @@ -47,18 +47,12 @@ static const VMStateDescription vmstate_i82378 = {
},
};

static void i82378_request_out0_irq(void *opaque, int irq, int level)
{
I82378State *s = opaque;
qemu_set_irq(s->out[0], level);
}

static void i82378_request_pic_irq(void *opaque, int irq, int level)
{
DeviceState *dev = opaque;
I82378State *s = I82378(dev);

qemu_set_irq(s->i8259[irq], level);
qemu_set_irq(s->isa_irqs_in[irq], level);
}

static void i82378_realize(PCIDevice *pci, Error **errp)
Expand Down Expand Up @@ -94,9 +88,8 @@ static void i82378_realize(PCIDevice *pci, Error **errp)
*/

/* 2 82C59 (irq) */
s->i8259 = i8259_init(isabus,
qemu_allocate_irq(i82378_request_out0_irq, s, 0));
isa_bus_irqs(isabus, s->i8259);
s->isa_irqs_in = i8259_init(isabus, s->cpu_intr);
isa_bus_register_input_irqs(isabus, s->isa_irqs_in);

/* 1 82C54 (pit) */
pit = i8254_pit_init(isabus, 0x40, 0, NULL);
Expand All @@ -113,7 +106,7 @@ static void i82378_init(Object *obj)
DeviceState *dev = DEVICE(obj);
I82378State *s = I82378(obj);

qdev_init_gpio_out(dev, s->out, 1);
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
}

Expand Down
32 changes: 21 additions & 11 deletions hw/isa/isa-bus.c
View file
Expand Up @@ -67,28 +67,34 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
return isabus;
}

void isa_bus_irqs(ISABus *bus, qemu_irq *irqs)
void isa_bus_register_input_irqs(ISABus *bus, qemu_irq *irqs_in)
{
bus->irqs = irqs;
bus->irqs_in = irqs_in;
}

qemu_irq isa_bus_get_irq(ISABus *bus, unsigned irqnum)
{
assert(irqnum < ISA_NUM_IRQS);
assert(bus->irqs_in);
return bus->irqs_in[irqnum];
}

/*
* isa_get_irq() returns the corresponding qemu_irq entry for the i8259.
* isa_get_irq() returns the corresponding input qemu_irq entry for the i8259.
*
* This function is only for special cases such as the 'ferr', and
* temporary use for normal devices until they are converted to qdev.
*/
qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq)
{
assert(!dev || ISA_BUS(qdev_get_parent_bus(DEVICE(dev))) == isabus);
assert(isairq < ISA_NUM_IRQS);
return isabus->irqs[isairq];
return isa_bus_get_irq(isabus, isairq);
}

void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq)
{
qemu_irq irq = isa_get_irq(isadev, isairq);
qdev_connect_gpio_out(DEVICE(isadev), gpioirq, irq);
qemu_irq input_irq = isa_get_irq(isadev, isairq);
qdev_connect_gpio_out(DEVICE(isadev), gpioirq, input_irq);
}

void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16)
Expand All @@ -99,7 +105,7 @@ void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16)
bus->dma[1] = dma16;
}

IsaDma *isa_get_dma(ISABus *bus, int nchan)
IsaDma *isa_bus_get_dma(ISABus *bus, int nchan)
{
assert(bus);
return bus->dma[nchan > 3 ? 1 : 0];
Expand All @@ -114,7 +120,7 @@ static inline void isa_init_ioport(ISADevice *dev, uint16_t ioport)

void isa_register_ioport(ISADevice *dev, MemoryRegion *io, uint16_t start)
{
memory_region_add_subregion(isabus->address_space_io, start, io);
memory_region_add_subregion(isa_address_space_io(dev), start, io);
isa_init_ioport(dev, start);
}

Expand All @@ -135,7 +141,7 @@ int isa_register_portio_list(ISADevice *dev,
isa_init_ioport(dev, start);

portio_list_init(piolist, OBJECT(dev), pio_start, opaque, name);
portio_list_add(piolist, isabus->address_space_io, start);
portio_list_add(piolist, isa_address_space_io(dev), start);

return 0;
}
Expand Down Expand Up @@ -164,6 +170,11 @@ bool isa_realize_and_unref(ISADevice *dev, ISABus *bus, Error **errp)
return qdev_realize_and_unref(&dev->parent_obj, &bus->parent_obj, errp);
}

ISABus *isa_bus_from_device(ISADevice *dev)
{
return ISA_BUS(qdev_get_parent_bus(DEVICE(dev)));
}

ISADevice *isa_vga_init(ISABus *bus)
{
vga_interface_created = true;
Expand Down Expand Up @@ -213,7 +224,6 @@ static const TypeInfo isa_device_type_info = {
.parent = TYPE_DEVICE,
.instance_size = sizeof(ISADevice),
.abstract = true,
.class_size = sizeof(ISADeviceClass),
.class_init = isa_device_class_init,
};

Expand Down
36 changes: 18 additions & 18 deletions hw/isa/lpc_ich9.c
View file
Expand Up @@ -40,8 +40,8 @@
#include "hw/irq.h"
#include "hw/isa/apm.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"
#include "hw/i386/pc.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"
Expand All @@ -57,8 +57,6 @@
/*****************************************************************************/
/* ICH9 LPC PCI to ISA bridge */

static void ich9_lpc_reset(DeviceState *qdev);

/* chipset configuration register
* to access chipset configuration registers, pci_[sg]et_{byte, word, long}
* are used.
Expand Down Expand Up @@ -259,7 +257,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
qemu_set_irq(lpc->gsi[gsi], level);
}

void ich9_lpc_set_irq(void *opaque, int pirq, int level)
static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
{
ICH9LPCState *lpc = opaque;
int pic_irq, pic_dis;
Expand All @@ -275,7 +273,7 @@ void ich9_lpc_set_irq(void *opaque, int pirq, int level)
/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
* a given device irq pin.
*/
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
{
BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
PCIBus *pci_bus = PCI_BUS(bus);
Expand All @@ -286,7 +284,7 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
}

PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
{
ICH9LPCState *lpc = opaque;
PCIINTxRoute route;
Expand Down Expand Up @@ -407,14 +405,13 @@ static void smi_features_ok_callback(void *opaque)
lpc->smi_features_ok = 1;
}

void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
static void ich9_lpc_pm_init(ICH9LPCState *lpc)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
qemu_irq sci_irq;
FWCfgState *fw_cfg = fw_cfg_find();

sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
ich9_pm_init(PCI_DEVICE(lpc), &lpc->pm, sci_irq);

if (lpc->smi_host_features && fw_cfg) {
uint64_t host_features_le;
Expand All @@ -440,8 +437,6 @@ void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
sizeof lpc->smi_features_ok,
true);
}

ich9_lpc_reset(DEVICE(lpc));
}

/* APM */
Expand Down Expand Up @@ -680,6 +675,7 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
{
ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
DeviceState *dev = DEVICE(d);
PCIBus *pci_bus = pci_get_bus(d);
ISABus *isa_bus;

if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) &&
Expand Down Expand Up @@ -709,8 +705,6 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
"lpc-rcrb-mmio", ICH9_CC_SIZE);

lpc->isa_bus = isa_bus;

ich9_cc_init(lpc);
apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);

Expand All @@ -723,11 +717,17 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
1);

qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, IOAPIC_NUM_PINS);

isa_bus_irqs(isa_bus, lpc->gsi);
isa_bus_register_input_irqs(isa_bus, lpc->gsi);

i8257_dma_init(isa_bus, 0);

pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS);
pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq);
pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq);

ich9_lpc_pm_init(lpc);
}

static bool ich9_rst_cnt_needed(void *opaque)
Expand Down Expand Up @@ -794,6 +794,7 @@ static const VMStateDescription vmstate_ich9_lpc = {
static Property ich9_lpc_properties[] = {
DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, false),
DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false),
DEFINE_PROP_BOOL("smm-enabled", ICH9LPCState, pm.smm_enabled, false),
DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
ICH9_LPC_SMI_F_BROADCAST_BIT, true),
DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features,
Expand All @@ -813,8 +814,7 @@ static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
{
Aml *field;
ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
BusState *bus = BUS(s->isa_bus);
BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
Aml *sb_scope = aml_scope("\\_SB");

/* ICH9 PCI to ISA irq remapping */
Expand Down
4 changes: 2 additions & 2 deletions hw/isa/piix4.c
View file
Expand Up @@ -47,7 +47,7 @@ struct PIIX4State {
qemu_irq cpu_intr;
qemu_irq *isa;

RTCState rtc;
MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci;
PIIX4PMState pm;
Expand Down Expand Up @@ -212,7 +212,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
s->isa = i8259_init(isa_bus, *i8259_out_irq);

/* initialize ISA irqs */
isa_bus_irqs(isa_bus, s->isa);
isa_bus_register_input_irqs(isa_bus, s->isa);

/* initialize pit */
i8254_pit_init(isa_bus, 0x40, 0, NULL);
Expand Down
18 changes: 5 additions & 13 deletions hw/isa/vt82c686.c
View file
Expand Up @@ -548,9 +548,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA)
struct ViaISAState {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa_irqs;
qemu_irq *isa_irqs_in;
ViaSuperIOState via_sio;
RTCState rtc;
MC146818RtcState rtc;
PCIIDEState ide;
UHCIState uhci[2];
ViaPMState pm;
Expand Down Expand Up @@ -595,35 +595,27 @@ static const TypeInfo via_isa_info = {
void via_isa_set_irq(PCIDevice *d, int n, int level)
{
ViaISAState *s = VIA_ISA(d);
qemu_set_irq(s->isa_irqs[n], level);
}

static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
ViaISAState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
qemu_set_irq(s->isa_irqs_in[n], level);
}

static void via_isa_realize(PCIDevice *d, Error **errp)
{
ViaISAState *s = VIA_ISA(d);
DeviceState *dev = DEVICE(d);
PCIBus *pci_bus = pci_get_bus(d);
qemu_irq *isa_irq;
ISABus *isa_bus;
int i;

qdev_init_gpio_out(dev, &s->cpu_intr, 1);
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d),
errp);

if (!isa_bus) {
return;
}

s->isa_irqs = i8259_init(isa_bus, *isa_irq);
isa_bus_irqs(isa_bus, s->isa_irqs);
s->isa_irqs_in = i8259_init(isa_bus, s->cpu_intr);
isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in);
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);

Expand Down
2 changes: 1 addition & 1 deletion hw/mips/jazz.c
View file
Expand Up @@ -249,7 +249,7 @@ static void mips_jazz_init(MachineState *machine,

/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
isa_bus_register_input_irqs(isa_bus, i8259);
i8257_dma_init(isa_bus, 0);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_new(TYPE_PC_SPEAKER), isa_bus, pit);
Expand Down
1 change: 1 addition & 0 deletions hw/misc/macio/gpio.c
View file
Expand Up @@ -28,6 +28,7 @@
#include "migration/vmstate.h"
#include "hw/misc/macio/macio.h"
#include "hw/misc/macio/gpio.h"
#include "hw/irq.h"
#include "hw/nmi.h"
#include "qemu/log.h"
#include "qemu/module.h"
Expand Down
1 change: 1 addition & 0 deletions hw/nubus/nubus-device.c
View file
Expand Up @@ -80,6 +80,7 @@ static void nubus_device_realize(DeviceState *dev, Error **errp)
&error_abort);
ret = load_image_mr(path, &nd->decl_rom);
g_free(path);
g_free(name);
if (ret < 0) {
error_setg(errp, "could not load romfile \"%s\"", nd->romfile);
return;
Expand Down
2 changes: 1 addition & 1 deletion hw/pci-bridge/i82801b11.c
View file
Expand Up @@ -45,7 +45,7 @@
#include "hw/pci/pci_bridge.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "hw/i386/ich9.h"
#include "hw/southbridge/ich9.h"

/*****************************************************************************/
/* ICH9 DMI-to-PCI bridge */
Expand Down
11 changes: 11 additions & 0 deletions hw/pci/msi.c
View file
Expand Up @@ -24,6 +24,8 @@
#include "qemu/range.h"
#include "qapi/error.h"

#include "hw/i386/kvm/xen_evtchn.h"

/* PCI_MSI_ADDRESS_LO */
#define PCI_MSI_ADDRESS_LO_MASK (~0x3)

Expand Down Expand Up @@ -414,6 +416,15 @@ void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
fprintf(stderr, "\n");
#endif

if (xen_mode == XEN_EMULATE) {
for (vector = 0; vector < msi_nr_vectors(flags); vector++) {
MSIMessage msg = msi_prepare_message(dev, vector);

xen_evtchn_snoop_msi(dev, false, vector, msg.address, msg.data,
msi_is_masked(dev, vector));
}
}

if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
return;
}
Expand Down
9 changes: 9 additions & 0 deletions hw/pci/msix.c
View file
Expand Up @@ -26,6 +26,8 @@
#include "qapi/error.h"
#include "trace.h"

#include "hw/i386/kvm/xen_evtchn.h"

/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
Expand Down Expand Up @@ -124,6 +126,13 @@ static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
{
bool is_masked = msix_is_masked(dev, vector);

if (xen_mode == XEN_EMULATE) {
MSIMessage msg = msix_prepare_message(dev, vector);

xen_evtchn_snoop_msi(dev, true, vector, msg.address, msg.data,
is_masked);
}

if (is_masked == was_masked) {
return;
}
Expand Down
19 changes: 18 additions & 1 deletion hw/pci/pci.c
View file
Expand Up @@ -49,6 +49,9 @@
#include "qemu/cutils.h"
#include "pci-internal.h"

#include "hw/xen/xen.h"
#include "hw/i386/kvm/xen_evtchn.h"

//#define DEBUG_PCI
#ifdef DEBUG_PCI
# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
Expand Down Expand Up @@ -319,6 +322,17 @@ static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg)
{
MemTxAttrs attrs = {};

/*
* Xen uses the high bits of the address to contain some of the bits
* of the PIRQ#. Therefore we can't just send the write cycle and
* trust that it's caught by the APIC at 0xfee00000 because the
* target of the write might be e.g. 0x0x1000fee46000 for PIRQ#4166.
* So we intercept the delivery here instead of in kvm_send_msi().
*/
if (xen_mode == XEN_EMULATE &&
xen_evtchn_deliver_pirq_msi(msg.address, msg.data)) {
return;
}
attrs.requester_id = pci_requester_id(dev);
address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,
attrs, NULL);
Expand Down Expand Up @@ -988,6 +1002,9 @@ static void do_pci_unregister_device(PCIDevice *pci_dev)
pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL;
pci_config_free(pci_dev);

if (xen_mode == XEN_EMULATE) {
xen_evtchn_remove_pci_device(pci_dev);
}
if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) {
memory_region_del_subregion(&pci_dev->bus_master_container_region,
&pci_dev->bus_master_enable_region);
Expand Down Expand Up @@ -1648,7 +1665,7 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev,
* 9.1: Interrupt routing. Table 9-1
*
* the PCI Express Base Specification, Revision 2.1
* 2.2.8.1: INTx interrutp signaling - Rules
* 2.2.8.1: INTx interrupt signaling - Rules
* the Implementation Note
* Table 2-20
*/
Expand Down
2 changes: 1 addition & 1 deletion hw/ppc/pnv_lpc.c
View file
Expand Up @@ -837,7 +837,7 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)

irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);

isa_bus_irqs(isa_bus, irqs);
isa_bus_register_input_irqs(isa_bus, irqs);

return isa_bus;
}
11 changes: 5 additions & 6 deletions hw/ppc/prep.c
View file
Expand Up @@ -212,14 +212,13 @@ static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
{
uint16_t checksum = *(uint16_t *)opaque;
ISADevice *rtc;

if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
rtc = ISA_DEVICE(dev);
rtc_set_memory(rtc, 0x2e, checksum & 0xff);
rtc_set_memory(rtc, 0x3e, checksum & 0xff);
rtc_set_memory(rtc, 0x2f, checksum >> 8);
rtc_set_memory(rtc, 0x3f, checksum >> 8);
MC146818RtcState *rtc = MC146818_RTC(dev);
mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff);
mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff);
mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8);
mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8);

object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
"date");
Expand Down
4 changes: 2 additions & 2 deletions hw/ppc/sam460ex.c
View file
Expand Up @@ -389,8 +389,8 @@ static void sam460ex_init(MachineState *machine)

/* MAL */
dev = qdev_new(TYPE_PPC4xx_MAL);
qdev_prop_set_uint32(dev, "txc-num", 4);
qdev_prop_set_uint32(dev, "rxc-num", 16);
qdev_prop_set_uint8(dev, "txc-num", 4);
qdev_prop_set_uint8(dev, "rxc-num", 16);
ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
object_unref(OBJECT(dev));
sbdev = SYS_BUS_DEVICE(dev);
Expand Down
2 changes: 1 addition & 1 deletion hw/rtc/m48t59-isa.c
View file
Expand Up @@ -47,7 +47,7 @@ struct M48txxISAState {
};

struct M48txxISADeviceClass {
ISADeviceClass parent_class;
DeviceClass parent_class;
M48txxInfo info;
};

Expand Down
128 changes: 64 additions & 64 deletions hw/rtc/mc146818rtc.c
View file

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions hw/sh4/r2d.c
View file
Expand Up @@ -38,7 +38,7 @@
#include "hw/qdev-properties.h"
#include "net/net.h"
#include "sh7750_regs.h"
#include "hw/ide.h"
#include "hw/ide/mmio.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/usb.h"
Expand Down Expand Up @@ -274,7 +274,7 @@ static void r2d_init(MachineState *machine)
dev = qdev_new("sysbus-sm501");
busdev = SYS_BUS_DEVICE(dev);
qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
qdev_prop_set_uint32(dev, "base", 0x10000000);
qdev_prop_set_uint64(dev, "dma-offset", 0x10000000);
qdev_prop_set_chr(dev, "chardev", serial_hd(2));
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0x10000000);
Expand Down
13 changes: 7 additions & 6 deletions hw/sparc64/sun4u.c
View file
Expand Up @@ -28,6 +28,7 @@
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
Expand Down Expand Up @@ -84,7 +85,8 @@ struct EbusState {
PCIDevice parent_obj;

ISABus *isa_bus;
qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
qemu_irq *isa_irqs_in;
qemu_irq isa_irqs_out[ISA_NUM_IRQS];
uint64_t console_serial_base;
MemoryRegion bar0;
MemoryRegion bar1;
Expand Down Expand Up @@ -287,7 +289,7 @@ static const TypeInfo power_info = {
static void ebus_isa_irq_handler(void *opaque, int n, int level)
{
EbusState *s = EBUS(opaque);
qemu_irq irq = s->isa_bus_irqs[n];
qemu_irq irq = s->isa_irqs_out[n];

/* Pass ISA bus IRQs onto their gpio equivalent */
trace_ebus_isa_irq_handler(n, level);
Expand All @@ -303,7 +305,6 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
ISADevice *isa_dev;
SysBusDevice *sbd;
DeviceState *dev;
qemu_irq *isa_irq;
DriveInfo *fd[MAX_FD];
int i;

Expand All @@ -315,9 +316,9 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp)
}

/* ISA bus */
isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
isa_bus_irqs(s->isa_bus, isa_irq);
qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in);
qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq",
ISA_NUM_IRQS);

/* Serial ports */
Expand Down
1 change: 1 addition & 0 deletions hw/timer/hpet.c
View file
Expand Up @@ -30,6 +30,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "hw/qdev-properties.h"
#include "hw/timer/hpet.h"
#include "hw/sysbus.h"
#include "hw/rtc/mc146818rtc.h"
Expand Down
7 changes: 3 additions & 4 deletions hw/usb/dev-smartcard-reader.c
View file
Expand Up @@ -278,7 +278,9 @@ typedef struct BulkIn {
struct CCIDBus {
BusState qbus;
};
typedef struct CCIDBus CCIDBus;

#define TYPE_CCID_BUS "ccid-bus"
OBJECT_DECLARE_SIMPLE_TYPE(CCIDBus, CCID_BUS)

/*
* powered - defaults to true, changed by PowerOn/PowerOff messages
Expand Down Expand Up @@ -1174,9 +1176,6 @@ static Property ccid_props[] = {
DEFINE_PROP_END_OF_LIST(),
};

#define TYPE_CCID_BUS "ccid-bus"
OBJECT_DECLARE_SIMPLE_TYPE(CCIDBus, CCID_BUS)

static const TypeInfo ccid_bus_info = {
.name = TYPE_CCID_BUS,
.parent = TYPE_BUS,
Expand Down
442 changes: 240 additions & 202 deletions hw/usb/hcd-ohci.c
View file

Large diffs are not rendered by default.

11 changes: 7 additions & 4 deletions hw/usb/hcd-ohci.h
View file
Expand Up @@ -21,6 +21,7 @@
#ifndef HCD_OHCI_H
#define HCD_OHCI_H

#include "hw/sysbus.h"
#include "sysemu/dma.h"
#include "hw/usb.h"
#include "qom/object.h"
Expand All @@ -33,7 +34,9 @@ typedef struct OHCIPort {
uint32_t ctrl;
} OHCIPort;

typedef struct OHCIState {
typedef struct OHCIState OHCIState;

struct OHCIState {
USBBus bus;
qemu_irq irq;
MemoryRegion mem;
Expand Down Expand Up @@ -89,8 +92,8 @@ typedef struct OHCIState {
uint32_t async_td;
bool async_complete;

void (*ohci_die)(struct OHCIState *ohci);
} OHCIState;
void (*ohci_die)(OHCIState *ohci);
};

#define TYPE_SYSBUS_OHCI "sysbus-ohci"
OBJECT_DECLARE_SIMPLE_TYPE(OHCISysBusState, SYSBUS_OHCI)
Expand All @@ -112,7 +115,7 @@ extern const VMStateDescription vmstate_ohci_state;
void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
dma_addr_t localmem_base, char *masterbus,
uint32_t firstport, AddressSpace *as,
void (*ohci_die_fn)(struct OHCIState *), Error **errp);
void (*ohci_die_fn)(OHCIState *), Error **errp);
void ohci_bus_stop(OHCIState *ohci);
void ohci_stop_endpoints(OHCIState *ohci);
void ohci_hard_reset(OHCIState *ohci);
Expand Down
7 changes: 2 additions & 5 deletions hw/usb/hcd-uhci.c
View file
Expand Up @@ -60,9 +60,7 @@ enum {
TD_RESULT_ASYNC_CONT,
};

typedef struct UHCIState UHCIState;
typedef struct UHCIAsync UHCIAsync;
typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;

struct UHCIPCIDeviceClass {
PCIDeviceClass parent_class;
Expand Down Expand Up @@ -1161,8 +1159,7 @@ static USBBusOps uhci_bus_ops = {
void usb_uhci_common_realize(PCIDevice *dev, Error **errp)
{
Error *err = NULL;
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class);
UHCIPCIDeviceClass *u = UHCI_GET_CLASS(dev);
UHCIState *s = UHCI(dev);
uint8_t *pci_conf = s->dev.config;
int i;
Expand Down Expand Up @@ -1269,7 +1266,7 @@ void uhci_data_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class);
UHCIPCIDeviceClass *u = UHCI_CLASS(klass);
UHCIInfo *info = data;

k->realize = info->realize ? info->realize : usb_uhci_common_realize;
Expand Down
2 changes: 1 addition & 1 deletion hw/usb/hcd-uhci.h
View file
Expand Up @@ -75,7 +75,7 @@ typedef struct UHCIState {
} UHCIState;

#define TYPE_UHCI "pci-uhci-usb"
DECLARE_INSTANCE_CHECKER(UHCIState, UHCI, TYPE_UHCI)
OBJECT_DECLARE_TYPE(UHCIState, UHCIPCIDeviceClass, UHCI)

typedef struct UHCIInfo {
const char *name;
Expand Down
8 changes: 5 additions & 3 deletions hw/usb/hcd-xhci-nec.c
View file
Expand Up @@ -27,14 +27,16 @@

#include "hcd-xhci-pci.h"

typedef struct XHCINecState {
OBJECT_DECLARE_SIMPLE_TYPE(XHCINecState, NEC_XHCI)

struct XHCINecState {
/*< private >*/
XHCIPciState parent_obj;
/*< public >*/
uint32_t flags;
uint32_t intrs;
uint32_t slots;
} XHCINecState;
};

static Property nec_xhci_properties[] = {
DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO),
Expand All @@ -51,7 +53,7 @@ static Property nec_xhci_properties[] = {
static void nec_xhci_instance_init(Object *obj)
{
XHCIPciState *pci = XHCI_PCI(obj);
XHCINecState *nec = container_of(pci, XHCINecState, parent_obj);
XHCINecState *nec = NEC_XHCI(obj);

pci->xhci.flags = nec->flags;
pci->xhci.numintrs = nec->intrs;
Expand Down
4 changes: 4 additions & 0 deletions hw/usb/trace-events
View file
Expand Up @@ -57,8 +57,12 @@ usb_ohci_ed_read_error(uint32_t addr) "ED read error at 0x%x"
usb_ohci_ed_pkt(uint32_t cur, int h, int c, uint32_t head, uint32_t tail, uint32_t next) "ED @ 0x%.8x h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x"
usb_ohci_ed_pkt_flags(uint32_t fa, uint32_t en, uint32_t d, int s, int k, int f, uint32_t mps) "fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u"
usb_ohci_hcca_read_error(uint32_t addr) "HCCA read error at 0x%x"
usb_ohci_mem_read(uint32_t size, const char *name, uint32_t addr, uint32_t offs, uint32_t val) "%d %s 0x%x %d -> 0x%x"
usb_ohci_mem_port_read(uint32_t size, const char *name, uint32_t port, uint32_t addr, uint32_t offs, uint32_t val) "%d %s[%d] 0x%x %d -> 0x%x"
usb_ohci_mem_read_unaligned(uint32_t addr) "at 0x%x"
usb_ohci_mem_read_bad_offset(uint32_t addr) "0x%x"
usb_ohci_mem_write(uint32_t size, const char *name, uint32_t addr, uint32_t offs, uint32_t val) "%d %s 0x%x %d <- 0x%x"
usb_ohci_mem_port_write(uint32_t size, const char *name, uint32_t port, uint32_t addr, uint32_t offs, uint32_t val) "%d %s[%d] 0x%x %d <- 0x%x"
usb_ohci_mem_write_unaligned(uint32_t addr) "at 0x%x"
usb_ohci_mem_write_bad_offset(uint32_t addr) "0x%x"
usb_ohci_process_lists(uint32_t head, uint32_t cur) "head 0x%x, cur 0x%x"
Expand Down
16 changes: 5 additions & 11 deletions hw/usb/u2f.h
View file
Expand Up @@ -31,22 +31,16 @@
#define U2FHID_PACKET_SIZE 64
#define U2FHID_PENDING_IN_NUM 32

typedef struct U2FKeyState U2FKeyState;
typedef struct U2FKeyInfo U2FKeyInfo;

#define TYPE_U2F_KEY "u2f-key"
#define U2F_KEY(obj) \
OBJECT_CHECK(U2FKeyState, (obj), TYPE_U2F_KEY)
#define U2F_KEY_CLASS(klass) \
OBJECT_CLASS_CHECK(U2FKeyClass, (klass), TYPE_U2F_KEY)
#define U2F_KEY_GET_CLASS(obj) \
OBJECT_GET_CLASS(U2FKeyClass, (obj), TYPE_U2F_KEY)
OBJECT_DECLARE_TYPE(U2FKeyState, U2FKeyClass, U2F_KEY)

/*
* Callbacks to be used by the U2F key base device (i.e. hw/u2f.c)
* to interact with its variants (i.e. hw/u2f-*.c)
*/
typedef struct U2FKeyClass {
struct U2FKeyClass {
/*< private >*/
USBDeviceClass parent_class;

Expand All @@ -55,12 +49,12 @@ typedef struct U2FKeyClass {
const uint8_t packet[U2FHID_PACKET_SIZE]);
void (*realize)(U2FKeyState *key, Error **errp);
void (*unrealize)(U2FKeyState *key);
} U2FKeyClass;
};

/*
* State of the U2F key base device (i.e. hw/u2f.c)
*/
typedef struct U2FKeyState {
struct U2FKeyState {
USBDevice dev;
USBEndpoint *ep;
uint8_t idle;
Expand All @@ -70,7 +64,7 @@ typedef struct U2FKeyState {
uint8_t pending_in_start;
uint8_t pending_in_end;
uint8_t pending_in_num;
} U2FKeyState;
};

/*
* API to be used by the U2F key device variants (i.e. hw/u2f-*.c)
Expand Down
3 changes: 3 additions & 0 deletions hw/xen/Kconfig
View file
@@ -0,0 +1,3 @@
config XEN_BUS
bool
default y if (XEN || XEN_EMU)
56 changes: 22 additions & 34 deletions hw/xen/xen-legacy-backend.c
View file
Expand Up @@ -676,21 +676,30 @@ void xenstore_update_fe(char *watch, struct XenLegacyDevice *xendev)
}
/* -------------------------------------------------------------------- */

int xen_be_init(void)
static void xen_set_dynamic_sysbus(void)
{
Object *machine = qdev_get_machine();
ObjectClass *oc = object_get_class(machine);
MachineClass *mc = MACHINE_CLASS(oc);

machine_class_allow_dynamic_sysbus_dev(mc, TYPE_XENSYSDEV);
}

void xen_be_init(void)
{
xengnttab_handle *gnttabdev;

xenstore = xs_daemon_open();
if (!xenstore) {
xen_pv_printf(NULL, 0, "can't connect to xenstored\n");
return -1;
exit(1);
}

qemu_set_fd_handler(xs_fileno(xenstore), xenstore_update, NULL, NULL);

if (xen_xc == NULL || xen_fmem == NULL) {
/* Check if xen_init() have been called */
goto err;
xen_pv_printf(NULL, 0, "Xen operations not set up\n");
exit(1);
}

gnttabdev = xengnttab_open(NULL, 0);
Expand All @@ -706,23 +715,16 @@ int xen_be_init(void)
xen_sysbus = qbus_new(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
qbus_set_bus_hotplug_handler(xen_sysbus);

return 0;

err:
qemu_set_fd_handler(xs_fileno(xenstore), NULL, NULL, NULL);
xs_daemon_close(xenstore);
xenstore = NULL;

return -1;
}

static void xen_set_dynamic_sysbus(void)
{
Object *machine = qdev_get_machine();
ObjectClass *oc = object_get_class(machine);
MachineClass *mc = MACHINE_CLASS(oc);
xen_set_dynamic_sysbus();

machine_class_allow_dynamic_sysbus_dev(mc, TYPE_XENSYSDEV);
xen_be_register("console", &xen_console_ops);
xen_be_register("vkbd", &xen_kbdmouse_ops);
#ifdef CONFIG_VIRTFS
xen_be_register("9pfs", &xen_9pfs_ops);
#endif
#ifdef CONFIG_USB_LIBUSB
xen_be_register("qusb", &xen_usb_ops);
#endif
}

int xen_be_register(const char *type, struct XenDevOps *ops)
Expand All @@ -744,20 +746,6 @@ int xen_be_register(const char *type, struct XenDevOps *ops)
return xenstore_scan(type, xen_domid, ops);
}

void xen_be_register_common(void)
{
xen_set_dynamic_sysbus();

xen_be_register("console", &xen_console_ops);
xen_be_register("vkbd", &xen_kbdmouse_ops);
#ifdef CONFIG_VIRTFS
xen_be_register("9pfs", &xen_9pfs_ops);
#endif
#ifdef CONFIG_USB_LIBUSB
xen_be_register("qusb", &xen_usb_ops);
#endif
}

int xen_be_bind_evtchn(struct XenLegacyDevice *xendev)
{
if (xendev->local_port != -1) {
Expand Down
6 changes: 1 addition & 5 deletions hw/xenpv/xen_machine_pv.c
View file
Expand Up @@ -36,10 +36,7 @@ static void xen_init_pv(MachineState *machine)
int i;

/* Initialize backend core & drivers */
if (xen_be_init() != 0) {
error_report("%s: xen backend core setup failed", __func__);
exit(1);
}
xen_be_init();

switch (xen_mode) {
case XEN_ATTACH:
Expand All @@ -55,7 +52,6 @@ static void xen_init_pv(MachineState *machine)
break;
}

xen_be_register_common();
xen_be_register("vfb", &xen_framebuffer_ops);
xen_be_register("qnic", &xen_netdev_ops);

Expand Down
1 change: 0 additions & 1 deletion include/exec/gen-icount.h
View file
Expand Up @@ -2,7 +2,6 @@
#define GEN_ICOUNT_H

#include "exec/exec-all.h"
#include "qemu/timer.h"

/* Helpers for instruction counting code generation. */

Expand Down
80 changes: 80 additions & 0 deletions include/exec/replay-core.h
View file
@@ -0,0 +1,80 @@
/*
* QEMU replay core API
*
* Copyright (c) 2010-2015 Institute for System Programming
* of the Russian Academy of Sciences.
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/

#ifndef EXEC_REPLAY_H
#define EXEC_REPLAY_H

#include "qapi/qapi-types-replay.h"

extern ReplayMode replay_mode;

/* Replay process control functions */

/* Enables recording or saving event log with specified parameters */
void replay_configure(struct QemuOpts *opts);
/* Initializes timers used for snapshotting and enables events recording */
void replay_start(void);
/* Closes replay log file and frees other resources. */
void replay_finish(void);
/* Adds replay blocker with the specified error description */
void replay_add_blocker(const char *feature);
/* Returns name of the replay log file */
const char *replay_get_filename(void);

/*
* Start making one step in backward direction.
* Used by gdbstub for backwards debugging.
* Returns true on success.
*/
bool replay_reverse_step(void);
/*
* Start searching the last breakpoint/watchpoint.
* Used by gdbstub for backwards debugging.
* Returns true if the process successfully started.
*/
bool replay_reverse_continue(void);
/*
* Returns true if replay module is processing
* reverse_continue or reverse_step request
*/
bool replay_running_debug(void);
/* Called in reverse debugging mode to collect breakpoint information */
void replay_breakpoint(void);
/* Called when gdb is attached to gdbstub */
void replay_gdb_attached(void);

/* Interrupts and exceptions */

/* Called by exception handler to write or read exception processing events */
bool replay_exception(void);
/*
* Used to determine that exception is pending.
* Does not proceed to the next event in the log.
*/
bool replay_has_exception(void);
/*
* Called by interrupt handlers to write or read interrupt processing events.
* Returns true if interrupt should be processed.
*/
bool replay_interrupt(void);
/*
* Tries to read interrupt event from the file.
* Returns true, when interrupt request is pending.
*/
bool replay_has_interrupt(void);

/* Processing data from random generators */

/* Saves the values from the random number generator */
void replay_save_random(int ret, void *buf, size_t len);
/* Loads the saved values for the random number generator */
int replay_read_random(void *buf, size_t len);

#endif
6 changes: 2 additions & 4 deletions include/hw/acpi/ich9.h
View file
Expand Up @@ -64,17 +64,15 @@ typedef struct ICH9LPCPMRegs {
uint8_t disable_s3;
uint8_t disable_s4;
uint8_t s4_val;
uint8_t smm_enabled;
bool smm_enabled;
bool smm_compat;
bool enable_tco;
TCOIORegs tco_regs;
} ICH9LPCPMRegs;

#define ACPI_PM_PROP_TCO_ENABLED "enable_tco"

void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
bool smm_enabled,
qemu_irq sci_irq);
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq);

void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
extern const VMStateDescription vmstate_ich9_pm;
Expand Down
4 changes: 3 additions & 1 deletion include/hw/core/cpu.h
View file
Expand Up @@ -272,6 +272,8 @@ struct qemu_work_item;
* to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
* be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
* QOM parent.
* Under TCG this value is propagated to @tcg_cflags.
* See TranslationBlock::TCG CF_CLUSTER_MASK.
* @tcg_cflags: Pre-computed cflags for this cpu.
* @nr_cores: Number of cores within this CPU package.
* @nr_threads: Number of threads within this CPU.
Expand Down Expand Up @@ -946,7 +948,7 @@ static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
return false;
}

#ifdef CONFIG_USER_ONLY
#if !defined(CONFIG_TCG) || defined(CONFIG_USER_ONLY)
static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint)
{
Expand Down
3 changes: 3 additions & 0 deletions include/hw/i386/pc.h
View file
Expand Up @@ -291,12 +291,15 @@ extern const size_t pc_compat_1_5_len;
extern GlobalProperty pc_compat_1_4[];
extern const size_t pc_compat_1_4_len;

int pc_machine_kvm_type(MachineState *machine, const char *vm_type);

#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
{ \
MachineClass *mc = MACHINE_CLASS(oc); \
optsfn(mc); \
mc->init = initfn; \
mc->kvm_type = pc_machine_kvm_type; \
} \
static const TypeInfo pc_machine_type_##suffix = { \
.name = namestr TYPE_MACHINE_SUFFIX, \
Expand Down
6 changes: 1 addition & 5 deletions include/hw/i386/x86.h
View file
Expand Up @@ -20,11 +20,10 @@
#include "exec/hwaddr.h"
#include "qemu/notify.h"

#include "hw/i386/topology.h"
#include "hw/boards.h"
#include "hw/nmi.h"
#include "hw/intc/ioapic.h"
#include "hw/isa/isa.h"
#include "hw/i386/ioapic.h"
#include "qom/object.h"

struct X86MachineClass {
Expand Down Expand Up @@ -98,8 +97,6 @@ struct X86MachineState {
#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)

void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);

uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
unsigned int cpu_index);

Expand Down Expand Up @@ -134,7 +131,6 @@ bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);

/* Global System Interrupts */

#define GSI_NUM_PINS IOAPIC_NUM_PINS
#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))

typedef struct GSIState {
Expand Down
12 changes: 0 additions & 12 deletions include/hw/ide.h
View file
@@ -1,20 +1,8 @@
#ifndef HW_IDE_H
#define HW_IDE_H

#include "hw/isa/isa.h"
#include "exec/memory.h"

/* ide-isa.c */
ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
DriveInfo *hd0, DriveInfo *hd1);

/* ide-mmio.c */
void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1);

int ide_get_geometry(BusState *bus, int unit,
int16_t *cyls, int8_t *heads, int8_t *secs);
int ide_get_bios_chs_trans(BusState *bus, int unit);

/* ide/core.c */
void ide_drive_get(DriveInfo **hd, int max_bus);

Expand Down
29 changes: 12 additions & 17 deletions include/hw/ide/internal.h
View file
Expand Up @@ -7,13 +7,10 @@
* non-internal declarations are in hw/ide.h
*/

#include "qapi/qapi-types-run-state.h"
#include "hw/ide.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "sysemu/dma.h"
#include "hw/block/block.h"
#include "scsi/constants.h"
#include "exec/ioport.h"

/* debug IDE devices */
#define USE_DMA_CDROM
Expand Down Expand Up @@ -491,7 +488,7 @@ struct IDEBus {
IDEDMA *dma;
uint8_t unit;
uint8_t cmd;
qemu_irq irq;
qemu_irq irq; /* bus output */

int error_status;
uint8_t retry_unit;
Expand Down Expand Up @@ -569,18 +566,11 @@ static inline uint8_t ide_dma_cmd_to_retry(uint8_t dma_cmd)
return 0;
}

static inline IDEState *idebus_active_if(IDEBus *bus)
static inline IDEState *ide_bus_active_if(IDEBus *bus)
{
return bus->ifs + bus->unit;
}

static inline void ide_set_irq(IDEBus *bus)
{
if (!(bus->cmd & IDE_CTRL_DISABLE_IRQ)) {
qemu_irq_raise(bus->irq);
}
}

/* hw/ide/core.c */
extern const VMStateDescription vmstate_ide_bus;

Expand Down Expand Up @@ -626,12 +616,13 @@ int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
uint64_t wwn,
uint32_t cylinders, uint32_t heads, uint32_t secs,
int chs_trans, Error **errp);
void ide_init2(IDEBus *bus, qemu_irq irq);
void ide_exit(IDEState *s);
void ide_bus_init_output_irq(IDEBus *bus, qemu_irq irq_out);
int ide_init_ioport(IDEBus *bus, ISADevice *isa, int iobase, int iobase2);
void ide_register_restart_cb(IDEBus *bus);
void ide_bus_set_irq(IDEBus *bus);
void ide_bus_register_restart_cb(IDEBus *bus);

void ide_exec_cmd(IDEBus *bus, uint32_t val);
void ide_bus_exec_cmd(IDEBus *bus, uint32_t val);

void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
EndTransferFunc *end_transfer_func);
Expand All @@ -654,7 +645,11 @@ void ide_atapi_cmd_reply_end(IDEState *s);
/* hw/ide/qdev.c */
void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
int bus_id, int max_units);
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
IDEDevice *ide_bus_create_drive(IDEBus *bus, int unit, DriveInfo *drive);

int ide_get_geometry(BusState *bus, int unit,
int16_t *cyls, int8_t *heads, int8_t *secs);
int ide_get_bios_chs_trans(BusState *bus, int unit);

int ide_handle_rw_error(IDEState *s, int error, int op);

Expand Down
20 changes: 20 additions & 0 deletions include/hw/ide/isa.h
View file
@@ -0,0 +1,20 @@
/*
* QEMU IDE Emulation: ISA Bus support.
*
* Copyright (c) 2003 Fabrice Bellard
* Copyright (c) 2006 Openedhand Ltd.
*
* SPDX-License-Identifier: MIT
*/
#ifndef HW_IDE_ISA_H
#define HW_IDE_ISA_H

#include "qom/object.h"

#define TYPE_ISA_IDE "isa-ide"
OBJECT_DECLARE_SIMPLE_TYPE(ISAIDEState, ISA_IDE)

ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int irqnum,
DriveInfo *hd0, DriveInfo *hd1);

#endif
26 changes: 26 additions & 0 deletions include/hw/ide/mmio.h
View file
@@ -0,0 +1,26 @@
/*
* QEMU IDE Emulation: mmio support (for embedded).
*
* Copyright (c) 2003 Fabrice Bellard
* Copyright (c) 2006 Openedhand Ltd.
*
* SPDX-License-Identifier: MIT
*/

#ifndef HW_IDE_MMIO_H
#define HW_IDE_MMIO_H

#include "qom/object.h"

/*
* QEMU interface:
* + sysbus IRQ 0: asserted by the IDE channel
* + sysbus MMIO region 0: data registers
* + sysbus MMIO region 1: status & control registers
*/
#define TYPE_MMIO_IDE "mmio-ide"
OBJECT_DECLARE_SIMPLE_TYPE(MMIOIDEState, MMIO_IDE)

void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1);

#endif
7 changes: 1 addition & 6 deletions include/hw/ide/pci.h
View file
Expand Up @@ -49,18 +49,13 @@ struct PCIIDEState {

IDEBus bus[2];
BMDMAState bmdma[2];
qemu_irq isa_irq[2];
uint32_t secondary; /* used only for cmd646 */
MemoryRegion bmdma_bar;
MemoryRegion cmd_bar[2];
MemoryRegion data_bar[2];
};

static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
{
assert(bmdma->bus->retry_unit != (uint8_t)-1);
return bmdma->bus->ifs + bmdma->bus->retry_unit;
}

void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);
void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val);
extern MemoryRegionOps bmdma_addr_ioport_ops;
Expand Down
10 changes: 9 additions & 1 deletion include/hw/intc/i8259.h
View file
Expand Up @@ -4,7 +4,15 @@
/* i8259.c */

extern PICCommonState *isa_pic;
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);

/*
* i8259_init()
*
* Create a i8259 device on an ISA @bus,
* connect its output to @parent_irq_in,
* return an (allocated) array of 16 input IRQs.
*/
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq_in);
qemu_irq *kvm_i8259_init(ISABus *bus);
int pic_get_output(PICCommonState *s);
int pic_read_irq(PICCommonState *s);
Expand Down
6 changes: 3 additions & 3 deletions include/hw/i386/ioapic.h → include/hw/intc/ioapic.h
View file
Expand Up @@ -17,8 +17,8 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/

#ifndef HW_IOAPIC_H
#define HW_IOAPIC_H
#ifndef HW_INTC_IOAPIC_H
#define HW_INTC_IOAPIC_H

#define IOAPIC_NUM_PINS 24
#define IO_APIC_DEFAULT_ADDRESS 0xfec00000
Expand All @@ -30,4 +30,4 @@

void ioapic_eoi_broadcast(int vector);

#endif /* HW_IOAPIC_H */
#endif /* HW_INTC_IOAPIC_H */
2 changes: 1 addition & 1 deletion include/hw/isa/i8259_internal.h
View file
Expand Up @@ -35,7 +35,7 @@
OBJECT_DECLARE_TYPE(PICCommonState, PICCommonClass, PIC_COMMON)

struct PICCommonClass {
ISADeviceClass parent_class;
DeviceClass parent_class;

void (*pre_save)(PICCommonState *s);
void (*post_load)(PICCommonState *s);
Expand Down
35 changes: 18 additions & 17 deletions include/hw/isa/isa.h
View file
Expand Up @@ -11,7 +11,7 @@
#define ISA_NUM_IRQS 16

#define TYPE_ISA_DEVICE "isa-device"
OBJECT_DECLARE_TYPE(ISADevice, ISADeviceClass, ISA_DEVICE)
OBJECT_DECLARE_SIMPLE_TYPE(ISADevice, ISA_DEVICE)

#define TYPE_ISA_BUS "ISA"
OBJECT_DECLARE_SIMPLE_TYPE(ISABus, ISA_BUS)
Expand Down Expand Up @@ -48,18 +48,14 @@ struct IsaDmaClass {
void *opaque);
};

struct ISADeviceClass {
DeviceClass parent_class;
};

struct ISABus {
/*< private >*/
BusState parent_obj;
/*< public >*/

MemoryRegion *address_space;
MemoryRegion *address_space_io;
qemu_irq *irqs;
qemu_irq *irqs_in;
IsaDma *dma[2];
};

Expand All @@ -73,20 +69,30 @@ struct ISADevice {

ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space,
MemoryRegion *address_space_io, Error **errp);
void isa_bus_irqs(ISABus *bus, qemu_irq *irqs);
qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq);
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq);
void isa_bus_register_input_irqs(ISABus *bus, qemu_irq *irqs_in);
void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16);
IsaDma *isa_get_dma(ISABus *bus, int nchan);
MemoryRegion *isa_address_space(ISADevice *dev);
MemoryRegion *isa_address_space_io(ISADevice *dev);
IsaDma *isa_bus_get_dma(ISABus *bus, int nchan);
/**
* isa_bus_get_irq: Return input IRQ on ISA bus.
* @bus: the #ISABus to plug ISA devices on.
* @irqnum: the ISA IRQ number.
*
* Return IRQ @irqnum from the PIC associated on ISA @bus.
*/
qemu_irq isa_bus_get_irq(ISABus *bus, unsigned irqnum);
ISADevice *isa_new(const char *name);
ISADevice *isa_try_new(const char *name);
bool isa_realize_and_unref(ISADevice *dev, ISABus *bus, Error **errp);
ISADevice *isa_create_simple(ISABus *bus, const char *name);

ISADevice *isa_vga_init(ISABus *bus);

qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq);
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq);
MemoryRegion *isa_address_space(ISADevice *dev);
MemoryRegion *isa_address_space_io(ISADevice *dev);
ISABus *isa_bus_from_device(ISADevice *dev);

/**
* isa_register_ioport: Install an I/O port region on the ISA bus.
*
Expand Down Expand Up @@ -123,9 +129,4 @@ int isa_register_portio_list(ISADevice *dev,
const MemoryRegionPortio *portio,
void *opaque, const char *name);

static inline ISABus *isa_bus_from_device(ISADevice *d)
{
return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
}

#endif
2 changes: 1 addition & 1 deletion include/hw/isa/superio.h
View file
Expand Up @@ -44,7 +44,7 @@ typedef struct ISASuperIOFuncs {

struct ISASuperIOClass {
/*< private >*/
ISADeviceClass parent_class;
DeviceClass parent_class;
/*< public >*/
DeviceRealize parent_realize;

Expand Down
1 change: 1 addition & 0 deletions include/hw/pci/msi.h
View file
Expand Up @@ -33,6 +33,7 @@ extern bool msi_nonbroken;
void msi_set_message(PCIDevice *dev, MSIMessage msg);
MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector);
bool msi_enabled(const PCIDevice *dev);
void msi_set_enabled(PCIDevice *dev);
int msi_init(struct PCIDevice *dev, uint8_t offset,
unsigned int nr_vectors, bool msi64bit,
bool msi_per_vector_mask, Error **errp);
Expand Down
2 changes: 1 addition & 1 deletion include/hw/qdev-core.h
View file
Expand Up @@ -715,7 +715,7 @@ static inline void qdev_init_gpio_in_named(DeviceState *dev,
void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
const char *name);

BusState *qdev_get_parent_bus(DeviceState *dev);
BusState *qdev_get_parent_bus(const DeviceState *dev);

/*** BUS API. ***/

Expand Down
14 changes: 7 additions & 7 deletions include/hw/rtc/mc146818rtc.h
View file
Expand Up @@ -16,9 +16,9 @@
#include "qom/object.h"

#define TYPE_MC146818_RTC "mc146818rtc"
OBJECT_DECLARE_SIMPLE_TYPE(RTCState, MC146818_RTC)
OBJECT_DECLARE_SIMPLE_TYPE(MC146818RtcState, MC146818_RTC)

struct RTCState {
struct MC146818RtcState {
ISADevice parent_obj;

MemoryRegion io;
Expand Down Expand Up @@ -46,15 +46,15 @@ struct RTCState {
Notifier clock_reset_notifier;
LostTickPolicy lost_tick_policy;
Notifier suspend_notifier;
QLIST_ENTRY(RTCState) link;
QLIST_ENTRY(MC146818RtcState) link;
};

#define RTC_ISA_IRQ 8

ISADevice *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq);
void rtc_set_memory(ISADevice *dev, int addr, int val);
int rtc_get_memory(ISADevice *dev, int addr);
MC146818RtcState *mc146818_rtc_init(ISABus *bus, int base_year,
qemu_irq intercept_irq);
void mc146818rtc_set_cmos_data(MC146818RtcState *s, int addr, int val);
int mc146818rtc_get_cmos_data(MC146818RtcState *s, int addr);
void qmp_rtc_reset_reinjection(Error **errp);

#endif /* HW_RTC_MC146818RTC_H */
35 changes: 14 additions & 21 deletions include/hw/i386/ich9.h → include/hw/southbridge/ich9.h
View file
@@ -1,20 +1,15 @@
#ifndef HW_ICH9_H
#define HW_ICH9_H
#ifndef HW_SOUTHBRIDGE_ICH9_H
#define HW_SOUTHBRIDGE_ICH9_H

#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/i386/pc.h"
#include "hw/isa/apm.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/intc/ioapic.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_device.h"
#include "exec/memory.h"
#include "qemu/notify.h"
#include "qom/object.h"

void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);

void ich9_generate_smi(void);

#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
Expand Down Expand Up @@ -67,15 +62,13 @@ struct ICH9LPCState {
* triggers feature lockdown */
uint64_t smi_negotiated_features; /* guest-invisible, host endian */

/* isa bus */
ISABus *isa_bus;
MemoryRegion rcrb_mem; /* root complex register block */
Notifier machine_ready;

qemu_irq gsi[GSI_NUM_PINS];
qemu_irq gsi[IOAPIC_NUM_PINS];
};

#define Q35_MASK(bit, ms_bit, ls_bit) \
#define ICH9_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))

/* ICH9: Chipset Configuration Registers */
Expand Down Expand Up @@ -137,13 +130,13 @@ struct ICH9LPCState {
#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */

#define ICH9_LPC_PMBASE 0x40
#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ICH9_MASK(32, 15, 7)
#define ICH9_LPC_PMBASE_RTE 0x1
#define ICH9_LPC_PMBASE_DEFAULT 0x1

#define ICH9_LPC_ACPI_CTRL 0x44
#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ICH9_MASK(8, 2, 0)
#define ICH9_LPC_ACPI_CTRL_9 0x0
#define ICH9_LPC_ACPI_CTRL_10 0x1
#define ICH9_LPC_ACPI_CTRL_11 0x2
Expand All @@ -162,7 +155,7 @@ struct ICH9LPCState {
#define ICH9_LPC_PIRQH_ROUT 0x6b

#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
#define ICH9_LPC_PIRQ_ROUT_MASK ICH9_MASK(8, 3, 0)
#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80

#define ICH9_LPC_GEN_PMCON_1 0xa0
Expand All @@ -172,7 +165,7 @@ struct ICH9LPCState {
#define ICH9_LPC_GEN_PMCON_LOCK 0xa6

#define ICH9_LPC_RCBA 0xf0
#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
#define ICH9_LPC_RCBA_BA_MASK ICH9_MASK(32, 31, 14)
#define ICH9_LPC_RCBA_EN 0x1
#define ICH9_LPC_RCBA_DEFAULT 0x0

Expand Down Expand Up @@ -249,4 +242,4 @@ struct ICH9LPCState {
#define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1
#define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2

#endif /* HW_ICH9_H */
#endif /* HW_SOUTHBRIDGE_ICH9_H */
3 changes: 2 additions & 1 deletion include/hw/timer/i8254.h
View file
Expand Up @@ -56,7 +56,8 @@ static inline ISADevice *i8254_pit_init(ISABus *bus, int base, int isa_irq,
qdev_prop_set_uint32(dev, "iobase", base);
isa_realize_and_unref(d, bus, &error_fatal);
qdev_connect_gpio_out(dev, 0,
isa_irq >= 0 ? isa_get_irq(d, isa_irq) : alt_irq);
isa_irq >= 0 ? isa_bus_get_irq(bus, isa_irq)
: alt_irq);

return d;
}
Expand Down
2 changes: 1 addition & 1 deletion include/hw/timer/i8254_internal.h
View file
Expand Up @@ -58,7 +58,7 @@ struct PITCommonState {
};

struct PITCommonClass {
ISADeviceClass parent_class;
DeviceClass parent_class;

void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val);
void (*get_channel_info)(PITCommonState *s, PITChannelState *sc,
Expand Down
510 changes: 510 additions & 0 deletions include/hw/xen/interface/arch-arm.h
View file

Large diffs are not rendered by default.

118 changes: 118 additions & 0 deletions include/hw/xen/interface/arch-x86/cpuid.h
View file
@@ -0,0 +1,118 @@
/******************************************************************************
* arch-x86/cpuid.h
*
* CPUID interface to Xen.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Copyright (c) 2007 Citrix Systems, Inc.
*
* Authors:
* Keir Fraser <keir@xen.org>
*/

#ifndef __XEN_PUBLIC_ARCH_X86_CPUID_H__
#define __XEN_PUBLIC_ARCH_X86_CPUID_H__

/*
* For compatibility with other hypervisor interfaces, the Xen cpuid leaves
* can be found at the first otherwise unused 0x100 aligned boundary starting
* from 0x40000000.
*
* e.g If viridian extensions are enabled for an HVM domain, the Xen cpuid
* leaves will start at 0x40000100
*/

#define XEN_CPUID_FIRST_LEAF 0x40000000
#define XEN_CPUID_LEAF(i) (XEN_CPUID_FIRST_LEAF + (i))

/*
* Leaf 1 (0x40000x00)
* EAX: Largest Xen-information leaf. All leaves up to an including @EAX
* are supported by the Xen host.
* EBX-EDX: "XenVMMXenVMM" signature, allowing positive identification
* of a Xen host.
*/
#define XEN_CPUID_SIGNATURE_EBX 0x566e6558 /* "XenV" */
#define XEN_CPUID_SIGNATURE_ECX 0x65584d4d /* "MMXe" */
#define XEN_CPUID_SIGNATURE_EDX 0x4d4d566e /* "nVMM" */

/*
* Leaf 2 (0x40000x01)
* EAX[31:16]: Xen major version.
* EAX[15: 0]: Xen minor version.
* EBX-EDX: Reserved (currently all zeroes).
*/

/*
* Leaf 3 (0x40000x02)
* EAX: Number of hypercall transfer pages. This register is always guaranteed
* to specify one hypercall page.
* EBX: Base address of Xen-specific MSRs.
* ECX: Features 1. Unused bits are set to zero.
* EDX: Features 2. Unused bits are set to zero.
*/

/* Does the host support MMU_PT_UPDATE_PRESERVE_AD for this guest? */
#define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
#define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD (1u<<0)

/*
* Leaf 4 (0x40000x03)
* Sub-leaf 0: EAX: bit 0: emulated tsc
* bit 1: host tsc is known to be reliable
* bit 2: RDTSCP instruction available
* EBX: tsc_mode: 0=default (emulate if necessary), 1=emulate,
* 2=no emulation, 3=no emulation + TSC_AUX support
* ECX: guest tsc frequency in kHz
* EDX: guest tsc incarnation (migration count)
* Sub-leaf 1: EAX: tsc offset low part
* EBX: tsc offset high part
* ECX: multiplicator for tsc->ns conversion
* EDX: shift amount for tsc->ns conversion
* Sub-leaf 2: EAX: host tsc frequency in kHz
*/

/*
* Leaf 5 (0x40000x04)
* HVM-specific features
* Sub-leaf 0: EAX: Features
* Sub-leaf 0: EBX: vcpu id (iff EAX has XEN_HVM_CPUID_VCPU_ID_PRESENT flag)
* Sub-leaf 0: ECX: domain id (iff EAX has XEN_HVM_CPUID_DOMID_PRESENT flag)
*/
#define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0) /* Virtualized APIC registers */
#define XEN_HVM_CPUID_X2APIC_VIRT (1u << 1) /* Virtualized x2APIC accesses */
/* Memory mapped from other domains has valid IOMMU entries */
#define XEN_HVM_CPUID_IOMMU_MAPPINGS (1u << 2)
#define XEN_HVM_CPUID_VCPU_ID_PRESENT (1u << 3) /* vcpu id is present in EBX */
#define XEN_HVM_CPUID_DOMID_PRESENT (1u << 4) /* domid is present in ECX */

/*
* Leaf 6 (0x40000x05)
* PV-specific parameters
* Sub-leaf 0: EAX: max available sub-leaf
* Sub-leaf 0: EBX: bits 0-7: max machine address width
*/

/* Max. address width in bits taking memory hotplug into account. */
#define XEN_CPUID_MACHINE_ADDRESS_WIDTH_MASK (0xffu << 0)

#define XEN_CPUID_MAX_NUM_LEAVES 5

#endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
194 changes: 194 additions & 0 deletions include/hw/xen/interface/arch-x86/xen-x86_32.h
View file
@@ -0,0 +1,194 @@
/******************************************************************************
* xen-x86_32.h
*
* Guest OS interface to x86 32-bit Xen.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to
* deal in the Software without restriction, including without limitation the
* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Copyright (c) 2004-2007, K A Fraser
*/

#ifndef __XEN_PUBLIC_ARCH_X86_XEN_X86_32_H__
#define __XEN_PUBLIC_ARCH_X86_XEN_X86_32_H__

/*
* Hypercall interface:
* Input: %ebx, %ecx, %edx, %esi, %edi, %ebp (arguments 1-6)
* Output: %eax
* Access is via hypercall page (set up by guest loader or via a Xen MSR):
* call hypercall_page + hypercall-number * 32
* Clobbered: Argument registers (e.g., 2-arg hypercall clobbers %ebx,%ecx)
*/

/*
* These flat segments are in the Xen-private section of every GDT. Since these
* are also present in the initial GDT, many OSes will be able to avoid
* installing their own GDT.
*/
#define FLAT_RING1_CS 0xe019 /* GDT index 259 */
#define FLAT_RING1_DS 0xe021 /* GDT index 260 */
#define FLAT_RING1_SS 0xe021 /* GDT index 260 */
#define FLAT_RING3_CS 0xe02b /* GDT index 261 */
#define FLAT_RING3_DS 0xe033 /* GDT index 262 */
#define FLAT_RING3_SS 0xe033 /* GDT index 262 */

#define FLAT_KERNEL_CS FLAT_RING1_CS
#define FLAT_KERNEL_DS FLAT_RING1_DS
#define FLAT_KERNEL_SS FLAT_RING1_SS
#define FLAT_USER_CS FLAT_RING3_CS
#define FLAT_USER_DS FLAT_RING3_DS
#define FLAT_USER_SS FLAT_RING3_SS

#define __HYPERVISOR_VIRT_START_PAE 0xF5800000
#define __MACH2PHYS_VIRT_START_PAE 0xF5800000
#define __MACH2PHYS_VIRT_END_PAE 0xF6800000
#define HYPERVISOR_VIRT_START_PAE xen_mk_ulong(__HYPERVISOR_VIRT_START_PAE)
#define MACH2PHYS_VIRT_START_PAE xen_mk_ulong(__MACH2PHYS_VIRT_START_PAE)
#define MACH2PHYS_VIRT_END_PAE xen_mk_ulong(__MACH2PHYS_VIRT_END_PAE)

/* Non-PAE bounds are obsolete. */
#define __HYPERVISOR_VIRT_START_NONPAE 0xFC000000
#define __MACH2PHYS_VIRT_START_NONPAE 0xFC000000
#define __MACH2PHYS_VIRT_END_NONPAE 0xFC400000
#define HYPERVISOR_VIRT_START_NONPAE \
xen_mk_ulong(__HYPERVISOR_VIRT_START_NONPAE)
#define MACH2PHYS_VIRT_START_NONPAE \
xen_mk_ulong(__MACH2PHYS_VIRT_START_NONPAE)
#define MACH2PHYS_VIRT_END_NONPAE \
xen_mk_ulong(__MACH2PHYS_VIRT_END_NONPAE)

#define __HYPERVISOR_VIRT_START __HYPERVISOR_VIRT_START_PAE
#define __MACH2PHYS_VIRT_START __MACH2PHYS_VIRT_START_PAE
#define __MACH2PHYS_VIRT_END __MACH2PHYS_VIRT_END_PAE

#ifndef HYPERVISOR_VIRT_START
#define HYPERVISOR_VIRT_START xen_mk_ulong(__HYPERVISOR_VIRT_START)
#endif

#define MACH2PHYS_VIRT_START xen_mk_ulong(__MACH2PHYS_VIRT_START)
#define MACH2PHYS_VIRT_END xen_mk_ulong(__MACH2PHYS_VIRT_END)
#define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>2)
#ifndef machine_to_phys_mapping
#define machine_to_phys_mapping ((unsigned long *)MACH2PHYS_VIRT_START)
#endif

/* 32-/64-bit invariability for control interfaces (domctl/sysctl). */
#if defined(__XEN__) || defined(__XEN_TOOLS__)
#undef ___DEFINE_XEN_GUEST_HANDLE
#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \
typedef struct { type *p; } \
__guest_handle_ ## name; \
typedef struct { union { type *p; uint64_aligned_t q; }; } \
__guest_handle_64_ ## name
#undef set_xen_guest_handle_raw
#define set_xen_guest_handle_raw(hnd, val) \
do { if ( sizeof(hnd) == 8 ) *(uint64_t *)&(hnd) = 0; \
(hnd).p = val; \
} while ( 0 )
#define int64_aligned_t int64_t __attribute__((aligned(8)))
#define uint64_aligned_t uint64_t __attribute__((aligned(8)))
#define __XEN_GUEST_HANDLE_64(name) __guest_handle_64_ ## name
#define XEN_GUEST_HANDLE_64(name) __XEN_GUEST_HANDLE_64(name)
#endif

#ifndef __ASSEMBLY__

#if defined(XEN_GENERATING_COMPAT_HEADERS)
/* nothing */
#elif defined(__XEN__) || defined(__XEN_TOOLS__)
/* Anonymous unions include all permissible names (e.g., al/ah/ax/eax). */
#define __DECL_REG_LO8(which) union { \
uint32_t e ## which ## x; \
uint16_t which ## x; \
struct { \
uint8_t which ## l; \
uint8_t which ## h; \
}; \
}
#define __DECL_REG_LO16(name) union { \
uint32_t e ## name, _e ## name; \
uint16_t name; \
}
#else
/* Other sources must always use the proper 32-bit name (e.g., eax). */
#define __DECL_REG_LO8(which) uint32_t e ## which ## x
#define __DECL_REG_LO16(name) uint32_t e ## name
#endif

struct cpu_user_regs {
__DECL_REG_LO8(b);
__DECL_REG_LO8(c);
__DECL_REG_LO8(d);
__DECL_REG_LO16(si);
__DECL_REG_LO16(di);
__DECL_REG_LO16(bp);
__DECL_REG_LO8(a);
uint16_t error_code; /* private */
uint16_t entry_vector; /* private */
__DECL_REG_LO16(ip);
uint16_t cs;
uint8_t saved_upcall_mask;
uint8_t _pad0;
__DECL_REG_LO16(flags); /* eflags.IF == !saved_upcall_mask */
__DECL_REG_LO16(sp);
uint16_t ss, _pad1;
uint16_t es, _pad2;
uint16_t ds, _pad3;
uint16_t fs, _pad4;
uint16_t gs, _pad5;
};
typedef struct cpu_user_regs cpu_user_regs_t;
DEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t);

#undef __DECL_REG_LO8
#undef __DECL_REG_LO16

/*
* Page-directory addresses above 4GB do not fit into architectural %cr3.
* When accessing %cr3, or equivalent field in vcpu_guest_context, guests
* must use the following accessor macros to pack/unpack valid MFNs.
*/
#define xen_pfn_to_cr3(pfn) (((unsigned)(pfn) << 12) | ((unsigned)(pfn) >> 20))
#define xen_cr3_to_pfn(cr3) (((unsigned)(cr3) >> 12) | ((unsigned)(cr3) << 20))

struct arch_vcpu_info {
unsigned long cr2;
unsigned long pad[5]; /* sizeof(vcpu_info_t) == 64 */
};
typedef struct arch_vcpu_info arch_vcpu_info_t;

struct xen_callback {
unsigned long cs;
unsigned long eip;
};
typedef struct xen_callback xen_callback_t;

#endif /* !__ASSEMBLY__ */

#endif /* __XEN_PUBLIC_ARCH_X86_XEN_X86_32_H__ */

/*
* Local variables:
* mode: C
* c-file-style: "BSD"
* c-basic-offset: 4
* tab-width: 4
* indent-tabs-mode: nil
* End:
*/