276 changes: 13 additions & 263 deletions target/m68k/translate.c
View file

Large diffs are not rendered by default.

89 changes: 15 additions & 74 deletions target/microblaze/translate.c
View file
Expand Up @@ -101,10 +101,7 @@ static void t_sync_flags(DisasContext *dc)

static void gen_raise_exception(DisasContext *dc, uint32_t index)
{
TCGv_i32 tmp = tcg_const_i32(index);

gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN;
}

Expand All @@ -117,9 +114,8 @@ static void gen_raise_exception_sync(DisasContext *dc, uint32_t index)

static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
{
TCGv_i32 tmp = tcg_const_i32(esr_ec);
TCGv_i32 tmp = tcg_constant_i32(esr_ec);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr));
tcg_temp_free_i32(tmp);

gen_raise_exception_sync(dc, EXCP_HW_EXCP);
}
Expand Down Expand Up @@ -262,11 +258,9 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,

rd = reg_for_write(dc, arg->rd);
ra = reg_for_read(dc, arg->ra);
imm = tcg_const_i32(arg->imm);
imm = tcg_constant_i32(arg->imm);

fn(rd, ra, imm);

tcg_temp_free_i32(imm);
return true;
}

Expand Down Expand Up @@ -309,24 +303,19 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,
/* No input carry, but output carry. */
static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);

tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero);

tcg_temp_free_i32(zero);
}

/* Input and output carry. */
static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();

tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero);
tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);

tcg_temp_free_i32(tmp);
tcg_temp_free_i32(zero);
}

/* Input carry, but no output carry. */
Expand Down Expand Up @@ -361,23 +350,20 @@ static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_sar_i32(out, ina, tmp);
tcg_temp_free_i32(tmp);
}

static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_shr_i32(out, ina, tmp);
tcg_temp_free_i32(tmp);
}

static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_shl_i32(out, ina, tmp);
tcg_temp_free_i32(tmp);
}

static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm)
Expand Down Expand Up @@ -436,7 +422,6 @@ static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina);
tcg_gen_sub_i32(out, inb, ina);
tcg_gen_deposit_i32(out, out, lt, 31, 1);
tcg_temp_free_i32(lt);
}

static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
Expand All @@ -446,7 +431,6 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina);
tcg_gen_sub_i32(out, inb, ina);
tcg_gen_deposit_i32(out, out, lt, 31, 1);
tcg_temp_free_i32(lt);
}

DO_TYPEA(cmp, false, gen_cmp)
Expand Down Expand Up @@ -513,21 +497,18 @@ static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_muls2_i32(tmp, out, ina, inb);
tcg_temp_free_i32(tmp);
}

static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_mulu2_i32(tmp, out, ina, inb);
tcg_temp_free_i32(tmp);
}

static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_mulsu2_i32(tmp, out, ina, inb);
tcg_temp_free_i32(tmp);
}

DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32)
Expand Down Expand Up @@ -563,15 +544,12 @@ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
/* Input and output carry. */
static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 zero = tcg_const_i32(0);
TCGv_i32 zero = tcg_constant_i32(0);
TCGv_i32 tmp = tcg_temp_new_i32();

tcg_gen_not_i32(tmp, ina);
tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero);
tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);

tcg_temp_free_i32(zero);
tcg_temp_free_i32(tmp);
}

/* No input or output carry. */
Expand All @@ -588,8 +566,6 @@ static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
tcg_gen_not_i32(nota, ina);
tcg_gen_add_i32(out, inb, nota);
tcg_gen_add_i32(out, out, cpu_msr_c);

tcg_temp_free_i32(nota);
}

DO_TYPEA(rsub, true, gen_rsub)
Expand Down Expand Up @@ -618,8 +594,6 @@ static void gen_src(TCGv_i32 out, TCGv_i32 ina)
tcg_gen_mov_i32(tmp, cpu_msr_c);
tcg_gen_andi_i32(cpu_msr_c, ina, 1);
tcg_gen_extract2_i32(out, ina, tmp, 1);

tcg_temp_free_i32(tmp);
}

static void gen_srl(TCGv_i32 out, TCGv_i32 ina)
Expand Down Expand Up @@ -659,7 +633,6 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]);
tcg_gen_extu_i32_tl(ret, tmp);
tcg_temp_free_i32(tmp);
} else if (ra) {
tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
} else if (rb) {
Expand All @@ -683,7 +656,6 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_addi_i32(tmp, cpu_R[ra], imm);
tcg_gen_extu_i32_tl(ret, tmp);
tcg_temp_free_i32(tmp);
} else {
tcg_gen_movi_tl(ret, (uint32_t)imm);
}
Expand Down Expand Up @@ -772,8 +744,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
#endif

tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop);

tcg_temp_free(addr);
return true;
}

Expand Down Expand Up @@ -879,7 +849,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)

tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
tcg_gen_mov_tl(cpu_res_addr, addr);
tcg_temp_free(addr);

if (arg->rd) {
tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
Expand Down Expand Up @@ -925,8 +894,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
#endif

tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop);

tcg_temp_free(addr);
return true;
}

Expand Down Expand Up @@ -1040,7 +1007,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
* In either case, addr is no longer needed.
*/
tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
tcg_temp_free(addr);

/*
* Compare the value loaded during lwx with current contents of
Expand All @@ -1053,7 +1019,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
dc->mem_index, MO_TEUL);

tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
tcg_temp_free_i32(tval);

/* Success */
tcg_gen_movi_i32(cpu_msr_c, 0);
Expand Down Expand Up @@ -1150,13 +1115,11 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm,
}

/* Compute the final destination into btarget. */
zero = tcg_const_i32(0);
next = tcg_const_i32(dc->base.pc_next + (delay + 1) * 4);
zero = tcg_constant_i32(0);
next = tcg_constant_i32(dc->base.pc_next + (delay + 1) * 4);
tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget,
reg_for_read(dc, ra), zero,
cpu_btarget, next);
tcg_temp_free_i32(zero);
tcg_temp_free_i32(next);

return true;
}
Expand Down Expand Up @@ -1261,20 +1224,16 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg)

/* Sleep. */
if (mbar_imm & 16) {
TCGv_i32 tmp_1;

if (trap_userspace(dc, true)) {
/* Sleep is a privileged instruction. */
return true;
}

t_sync_flags(dc);

tmp_1 = tcg_const_i32(1);
tcg_gen_st_i32(tmp_1, cpu_env,
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
-offsetof(MicroBlazeCPU, env)
+offsetof(CPUState, halted));
tcg_temp_free_i32(tmp_1);

tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);

Expand Down Expand Up @@ -1345,7 +1304,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d)
t = tcg_temp_new_i32();
tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC);
tcg_gen_or_i32(d, cpu_msr, t);
tcg_temp_free_i32(t);
}

static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
Expand Down Expand Up @@ -1438,12 +1396,10 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
case 0x1004: /* TLBHI */
case 0x1005: /* TLBSX */
{
TCGv_i32 tmp_ext = tcg_const_i32(arg->e);
TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7);
TCGv_i32 tmp_ext = tcg_constant_i32(arg->e);
TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7);

gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src);
tcg_temp_free_i32(tmp_reg);
tcg_temp_free_i32(tmp_ext);
}
break;

Expand All @@ -1467,7 +1423,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
tcg_gen_extrh_i64_i32(dest, t64);
tcg_temp_free_i64(t64);
}
return true;
#ifndef CONFIG_USER_ONLY
Expand Down Expand Up @@ -1498,7 +1453,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
TCGv_i64 t64 = tcg_temp_new_i64();
tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
tcg_gen_extrl_i64_i32(dest, t64);
tcg_temp_free_i64(t64);
}
break;
case SR_ESR:
Expand Down Expand Up @@ -1528,12 +1482,10 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
case 0x1004: /* TLBHI */
case 0x1005: /* TLBSX */
{
TCGv_i32 tmp_ext = tcg_const_i32(arg->e);
TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7);
TCGv_i32 tmp_ext = tcg_constant_i32(arg->e);
TCGv_i32 tmp_reg = tcg_constant_i32(arg->rs & 7);

gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg);
tcg_temp_free_i32(tmp_reg);
tcg_temp_free_i32(tmp_ext);
}
break;
#endif
Expand All @@ -1559,8 +1511,6 @@ static void do_rti(DisasContext *dc)
tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM);
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);

tcg_temp_free_i32(tmp);
}

static void do_rtb(DisasContext *dc)
Expand All @@ -1571,8 +1521,6 @@ static void do_rtb(DisasContext *dc)
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP));
tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);

tcg_temp_free_i32(tmp);
}

static void do_rte(DisasContext *dc)
Expand All @@ -1584,8 +1532,6 @@ static void do_rte(DisasContext *dc)
tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM));
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);

tcg_temp_free_i32(tmp);
}

/* Insns connected to FSL or AXI stream attached devices. */
Expand All @@ -1604,10 +1550,8 @@ static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl)
tcg_gen_movi_i32(t_id, imm);
}

t_ctrl = tcg_const_i32(ctrl);
t_ctrl = tcg_constant_i32(ctrl);
gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl);
tcg_temp_free_i32(t_id);
tcg_temp_free_i32(t_ctrl);
return true;
}

Expand Down Expand Up @@ -1636,10 +1580,8 @@ static bool do_put(DisasContext *dc, int ra, int rb, int imm, int ctrl)
tcg_gen_movi_i32(t_id, imm);
}

t_ctrl = tcg_const_i32(ctrl);
t_ctrl = tcg_constant_i32(ctrl);
gen_helper_put(t_id, t_ctrl, reg_for_read(dc, ra));
tcg_temp_free_i32(t_id);
tcg_temp_free_i32(t_ctrl);
return true;
}

Expand Down Expand Up @@ -1704,7 +1646,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
}

if (dc->r0) {
tcg_temp_free_i32(dc->r0);
dc->r0 = NULL;
dc->r0_set = false;
}
Expand Down
6 changes: 0 additions & 6 deletions target/mips/tcg/mips16e_translate.c.inc
View file
Expand Up @@ -280,9 +280,6 @@ static void gen_mips16_save(DisasContext *ctx,

tcg_gen_movi_tl(t2, -framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}

static void gen_mips16_restore(DisasContext *ctx,
Expand Down Expand Up @@ -386,9 +383,6 @@ static void gen_mips16_restore(DisasContext *ctx,

tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}

#if defined(TARGET_MIPS64)
Expand Down
2 changes: 1 addition & 1 deletion target/mips/tcg/vr54xx_translate.c
View file
Expand Up @@ -53,7 +53,7 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
tcg_temp_free(t0);
tcg_temp_free(t1);

return false;
return true;
}

TRANS(MACC, trans_mult_acc, gen_helper_macc);
Expand Down
15 changes: 0 additions & 15 deletions target/nios2/translate.c
View file
Expand Up @@ -233,7 +233,6 @@ static void gen_jumpr(DisasContext *dc, int regno, bool is_call)

tcg_gen_andi_tl(test, dest, 3);
tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l);
tcg_temp_free(test);

tcg_gen_mov_tl(cpu_pc, dest);
if (is_call) {
Expand Down Expand Up @@ -300,7 +299,6 @@ static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags)

tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);
tcg_temp_free(addr);
}

/* Store instructions */
Expand All @@ -312,7 +310,6 @@ static void gen_stx(DisasContext *dc, uint32_t code, uint32_t flags)
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_st_tl(val, addr, dc->mem_idx, flags);
tcg_temp_free(addr);
}

/* Branch instructions */
Expand Down Expand Up @@ -500,7 +497,6 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t flags)
TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
tcg_temp_free(tmp);
} else {
gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA));
}
Expand Down Expand Up @@ -530,7 +526,6 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t flags)
TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA));
tcg_temp_free(tmp);

dc->base.is_jmp = DISAS_NORETURN;
#endif
Expand Down Expand Up @@ -597,8 +592,6 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING]));
tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE]));
tcg_gen_and_tl(dest, t1, t2);
tcg_temp_free(t1);
tcg_temp_free(t2);
break;
default:
tcg_gen_ld_tl(dest, cpu_env,
Expand Down Expand Up @@ -662,11 +655,9 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
tcg_gen_ld_tl(o, cpu_env, ofs);
tcg_gen_andi_tl(o, o, ro);
tcg_gen_or_tl(n, n, o);
tcg_temp_free(o);
}

tcg_gen_st_tl(n, cpu_env, ofs);
tcg_temp_free(n);
}
break;
}
Expand Down Expand Up @@ -753,7 +744,6 @@ static void do_rr_mul_high(DisasContext *dc, uint32_t insn, GenFn4 *fn)

fn(discard, dest_gpr(dc, instr.c),
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
tcg_temp_free(discard);
}

#define gen_rr_mul_high(fname, insn) \
Expand All @@ -771,7 +761,6 @@ static void do_rr_shift(DisasContext *dc, uint32_t insn, GenFn3 *fn)

tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31);
fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), sh);
tcg_temp_free(sh);
}

#define gen_rr_shift(fname, insn) \
Expand Down Expand Up @@ -990,10 +979,6 @@ static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)

instr = &i_type_instructions[op];
instr->handler(dc, code, instr->flags);

if (dc->sink) {
tcg_temp_free(dc->sink);
}
}

static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
Expand Down
39 changes: 0 additions & 39 deletions target/openrisc/translate.c
View file
Expand Up @@ -206,10 +206,8 @@ static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
tcg_gen_xor_tl(t0, res, srcb);
tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
tcg_temp_free(t0);

tcg_gen_mov_tl(dest, res);
tcg_temp_free(res);

gen_ove_cyov(dc);
}
Expand All @@ -224,10 +222,8 @@ static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
tcg_gen_xor_tl(t0, res, srcb);
tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
tcg_temp_free(t0);

tcg_gen_mov_tl(dest, res);
tcg_temp_free(res);

gen_ove_cyov(dc);
}
Expand All @@ -243,7 +239,6 @@ static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb);

tcg_gen_mov_tl(dest, res);
tcg_temp_free(res);

gen_ove_cyov(dc);
}
Expand All @@ -255,7 +250,6 @@ static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb);
tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1);
tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0);
tcg_temp_free(t0);

tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
gen_ove_ov(dc);
Expand All @@ -278,7 +272,6 @@ static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
Supress the host-side exception by dividing by 1. */
tcg_gen_or_tl(t0, srcb, cpu_sr_ov);
tcg_gen_div_tl(dest, srca, t0);
tcg_temp_free(t0);

tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
gen_ove_ov(dc);
Expand All @@ -293,7 +286,6 @@ static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
Supress the host-side exception by dividing by 1. */
tcg_gen_or_tl(t0, srcb, cpu_sr_cy);
tcg_gen_divu_tl(dest, srca, t0);
tcg_temp_free(t0);

gen_ove_cy(dc);
}
Expand All @@ -314,14 +306,11 @@ static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb)
tcg_gen_muls2_i64(cpu_mac, high, t1, t2);
tcg_gen_sari_i64(t1, cpu_mac, 63);
tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high);
tcg_temp_free_i64(high);
tcg_gen_trunc_i64_tl(cpu_sr_ov, t1);
tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);

gen_ove_ov(dc);
}
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}

static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb)
Expand All @@ -340,12 +329,9 @@ static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb)
tcg_gen_mulu2_i64(cpu_mac, high, t1, t2);
tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0);
tcg_gen_trunc_i64_tl(cpu_sr_cy, high);
tcg_temp_free_i64(high);

gen_ove_cy(dc);
}
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
}

static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb)
Expand All @@ -362,14 +348,12 @@ static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb)
tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
tcg_gen_xor_i64(t1, t1, cpu_mac);
tcg_gen_andc_i64(t1, t1, t2);
tcg_temp_free_i64(t2);

#if TARGET_LONG_BITS == 32
tcg_gen_extrh_i64_i32(cpu_sr_ov, t1);
#else
tcg_gen_mov_i64(cpu_sr_ov, t1);
#endif
tcg_temp_free_i64(t1);

gen_ove_ov(dc);
}
Expand All @@ -382,13 +366,11 @@ static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb)
tcg_gen_extu_tl_i64(t1, srca);
tcg_gen_extu_tl_i64(t2, srcb);
tcg_gen_mul_i64(t1, t1, t2);
tcg_temp_free_i64(t2);

/* Note that overflow is only computed during addition stage. */
tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1);
tcg_gen_trunc_i64_tl(cpu_sr_cy, t1);
tcg_temp_free_i64(t1);

gen_ove_cy(dc);
}
Expand All @@ -407,14 +389,12 @@ static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb)
tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
tcg_gen_xor_i64(t1, t1, cpu_mac);
tcg_gen_and_i64(t1, t1, t2);
tcg_temp_free_i64(t2);

#if TARGET_LONG_BITS == 32
tcg_gen_extrh_i64_i32(cpu_sr_ov, t1);
#else
tcg_gen_mov_i64(cpu_sr_ov, t1);
#endif
tcg_temp_free_i64(t1);

gen_ove_ov(dc);
}
Expand All @@ -432,8 +412,6 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb)
tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1);
tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
tcg_gen_trunc_i64_tl(cpu_sr_cy, t2);
tcg_temp_free_i64(t2);
tcg_temp_free_i64(t1);

gen_ove_cy(dc);
}
Expand Down Expand Up @@ -672,7 +650,6 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a)
tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL);
tcg_gen_mov_tl(cpu_lock_addr, ea);
tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d));
tcg_temp_free(ea);
return true;
}

Expand All @@ -684,7 +661,6 @@ static void do_load(DisasContext *dc, arg_load *a, MemOp mop)
ea = tcg_temp_new();
tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i);
tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop);
tcg_temp_free(ea);
}

static bool trans_l_lwz(DisasContext *dc, arg_load *a)
Expand Down Expand Up @@ -734,13 +710,11 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)
lab_fail = gen_new_label();
lab_done = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail);
tcg_temp_free(ea);

val = tcg_temp_new();
tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value,
cpu_R(dc, a->b), dc->mem_idx, MO_TEUL);
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value);
tcg_temp_free(val);

tcg_gen_br(lab_done);

Expand All @@ -757,7 +731,6 @@ static void do_store(DisasContext *dc, arg_store *a, MemOp mop)
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i);
tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop);
tcg_temp_free(t0);
}

static bool trans_l_sw(DisasContext *dc, arg_store *a)
Expand Down Expand Up @@ -866,7 +839,6 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a)

tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr);
tcg_temp_free(spr);
}
return true;
}
Expand Down Expand Up @@ -897,7 +869,6 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a)
spr = tcg_temp_new();
tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k);
gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b));
tcg_temp_free(spr);
}
return true;
}
Expand Down Expand Up @@ -1349,8 +1320,6 @@ static bool do_dp3(DisasContext *dc, arg_dab_pair *a,
load_pair(dc, t1, a->b, a->bp);
fn(t0, cpu_env, t0, t1);
save_pair(dc, t0, a->d, a->dp);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);

gen_helper_update_fpcsr(cpu_env);
return true;
Expand All @@ -1372,7 +1341,6 @@ static bool do_dp2(DisasContext *dc, arg_da_pair *a,
load_pair(dc, t0, a->a, a->ap);
fn(t0, cpu_env, t0);
save_pair(dc, t0, a->d, a->dp);
tcg_temp_free_i64(t0);

gen_helper_update_fpcsr(cpu_env);
return true;
Expand All @@ -1399,8 +1367,6 @@ static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a,
} else {
fn(cpu_sr_f, cpu_env, t0, t1);
}
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);

if (inv) {
tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
Expand Down Expand Up @@ -1457,7 +1423,6 @@ static bool trans_lf_stod_d(DisasContext *dc, arg_lf_stod_d *a)
t0 = tcg_temp_new_i64();
gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a));
save_pair(dc, t0, a->d, a->dp);
tcg_temp_free_i64(t0);

gen_helper_update_fpcsr(cpu_env);
return true;
Expand All @@ -1476,7 +1441,6 @@ static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_dtos_d *a)
t0 = tcg_temp_new_i64();
load_pair(dc, t0, a->a, a->ap);
gen_helper_dtos(cpu_R(dc, a->d), cpu_env, t0);
tcg_temp_free_i64(t0);

gen_helper_update_fpcsr(cpu_env);
return true;
Expand All @@ -1502,9 +1466,6 @@ static bool trans_lf_madd_d(DisasContext *dc, arg_dab_pair *a)
load_pair(dc, t2, a->b, a->bp);
gen_helper_float_madd_d(t0, cpu_env, t0, t1, t2);
save_pair(dc, t0, a->d, a->dp);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);

gen_helper_update_fpcsr(cpu_env);
return true;
Expand Down
16 changes: 0 additions & 16 deletions target/ppc/power8-pmu-regs.c.inc
View file
Expand Up @@ -58,8 +58,6 @@ static bool spr_groupA_write_allowed(DisasContext *ctx)
/*
* Helper function to avoid code repetition between MMCR0 and
* MMCR2 problem state write functions.
*
* 'ret' must be tcg_temp_freed() by the caller.
*/
static TCGv masked_gprn_for_spr_write(int gprn, int sprn,
uint64_t spr_mask)
Expand All @@ -77,8 +75,6 @@ static TCGv masked_gprn_for_spr_write(int gprn, int sprn,
/* Add the masked gprn bits into 'ret' */
tcg_gen_or_tl(ret, ret, t0);

tcg_temp_free(t0);

return ret;
}

Expand All @@ -100,8 +96,6 @@ void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn)
gen_load_spr(t0, SPR_POWER_MMCR0);
tcg_gen_andi_tl(t0, t0, MMCR0_UREG_MASK);
tcg_gen_mov_tl(cpu_gpr[gprn], t0);

tcg_temp_free(t0);
}

static void write_MMCR0_common(DisasContext *ctx, TCGv val)
Expand Down Expand Up @@ -137,8 +131,6 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn)
masked_gprn = masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR0,
MMCR0_UREG_MASK);
write_MMCR0_common(ctx, masked_gprn);

tcg_temp_free(masked_gprn);
}

void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn)
Expand All @@ -164,8 +156,6 @@ void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn)
gen_load_spr(t0, SPR_POWER_MMCR2);
tcg_gen_andi_tl(t0, t0, MMCR2_UREG_MASK);
tcg_gen_mov_tl(cpu_gpr[gprn], t0);

tcg_temp_free(t0);
}

void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
Expand All @@ -183,8 +173,6 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
masked_gprn = masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR2,
MMCR2_UREG_MASK);
gen_store_spr(SPR_POWER_MMCR2, masked_gprn);

tcg_temp_free(masked_gprn);
}

void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
Expand All @@ -193,8 +181,6 @@ void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)

gen_icount_io_start(ctx);
gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);

tcg_temp_free_i32(t_sprn);
}

void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn)
Expand Down Expand Up @@ -228,8 +214,6 @@ void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)

gen_icount_io_start(ctx);
gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);

tcg_temp_free_i32(t_sprn);
}

void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn)
Expand Down
285 changes: 0 additions & 285 deletions target/ppc/translate.c
View file

Large diffs are not rendered by default.

20 changes: 0 additions & 20 deletions target/ppc/translate/dfp-impl.c.inc
View file
Expand Up @@ -20,9 +20,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
tcg_temp_free_ptr(rt); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
return true; \
}

Expand All @@ -36,8 +33,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_crf[a->bf], \
cpu_env, ra, rb); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
return true; \
}

Expand All @@ -50,7 +45,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
rb = gen_fprp_ptr(a->rb); \
gen_helper_##NAME(cpu_crf[a->bf], \
cpu_env, tcg_constant_i32(a->uim), rb);\
tcg_temp_free_ptr(rb); \
return true; \
}

Expand All @@ -63,7 +57,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
ra = gen_fprp_ptr(a->fra); \
gen_helper_##NAME(cpu_crf[a->bf], \
cpu_env, ra, tcg_constant_i32(a->dm)); \
tcg_temp_free_ptr(ra); \
return true; \
}

Expand All @@ -81,8 +74,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
tcg_temp_free_ptr(rt); \
tcg_temp_free_ptr(rb); \
return true; \
}

Expand All @@ -100,9 +91,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
tcg_temp_free_ptr(rt); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
return true; \
}

Expand All @@ -118,8 +106,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
tcg_temp_free_ptr(rt); \
tcg_temp_free_ptr(rb); \
return true; \
}

Expand All @@ -136,8 +122,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
if (unlikely(a->rc)) { \
gen_set_cr1_from_fpscr(ctx); \
} \
tcg_temp_free_ptr(rt); \
tcg_temp_free_ptr(rx); \
return true; \
}

Expand Down Expand Up @@ -205,8 +189,6 @@ static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
rt = gen_fprp_ptr(a->frtp);
rb = gen_avr_ptr(a->vrb);
gen_helper_DCFFIXQQ(cpu_env, rt, rb);
tcg_temp_free_ptr(rt);
tcg_temp_free_ptr(rb);

return true;
}
Expand All @@ -222,8 +204,6 @@ static bool trans_DCTFIXQQ(DisasContext *ctx, arg_DCTFIXQQ *a)
rt = gen_avr_ptr(a->vrt);
rb = gen_fprp_ptr(a->frbp);
gen_helper_DCTFIXQQ(cpu_env, rt, rb);
tcg_temp_free_ptr(rt);
tcg_temp_free_ptr(rb);

return true;
}
16 changes: 0 additions & 16 deletions target/ppc/translate/fixedpoint-impl.c.inc
View file
Expand Up @@ -42,8 +42,6 @@ static bool do_ldst(DisasContext *ctx, int rt, int ra, TCGv displ, bool update,
if (update) {
tcg_gen_mov_tl(cpu_gpr[ra], ea);
}
tcg_temp_free(ea);

return true;
}

Expand Down Expand Up @@ -149,7 +147,6 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
tcg_gen_qemu_ld_i64(high_addr_gpr, ea, ctx->mem_idx, mop);
}
}
tcg_temp_free(ea);
#else
qemu_build_not_reached();
#endif
Expand Down Expand Up @@ -389,8 +386,6 @@ static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev)
if (neg) {
tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]);
}
tcg_temp_free(temp);

return true;
}

Expand Down Expand Up @@ -437,9 +432,6 @@ static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, int64_t trail)
}

tcg_gen_ctpop_i64(dst, t0);

tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}

static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
Expand Down Expand Up @@ -519,11 +511,6 @@ static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)

tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);

tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(carry);

return true;
}

Expand Down Expand Up @@ -564,9 +551,6 @@ static bool do_hash(DisasContext *ctx, arg_X *a, bool priv,

ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt));
helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]);

tcg_temp_free(ea);

return true;
}

Expand Down
122 changes: 2 additions & 120 deletions target/ppc/translate/fp-impl.c.inc
View file

Large diffs are not rendered by default.

59 changes: 0 additions & 59 deletions target/ppc/translate/spe-impl.c.inc
View file
Expand Up @@ -23,7 +23,6 @@ static inline void gen_evmra(DisasContext *ctx)

/* spe_acc := tmp */
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
tcg_temp_free_i64(tmp);

/* rD := rA */
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
Expand Down Expand Up @@ -96,8 +95,6 @@ static inline void gen_##name(DisasContext *ctx) \
tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
tcg_opi(t0, t0, rB(ctx->opcode)); \
tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
\
tcg_temp_free_i32(t0); \
}
GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
Expand All @@ -122,8 +119,6 @@ static inline void gen_##name(DisasContext *ctx) \
tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
tcg_op(t0, t0); \
tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
\
tcg_temp_free_i32(t0); \
}

GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32);
Expand Down Expand Up @@ -159,9 +154,6 @@ static inline void gen_##name(DisasContext *ctx) \
tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
tcg_op(t0, t0, t1); \
tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
\
tcg_temp_free_i32(t0); \
tcg_temp_free_i32(t1); \
}

static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
Expand All @@ -178,7 +170,6 @@ static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
gen_set_label(l1);
tcg_gen_movi_i32(ret, 0);
gen_set_label(l2);
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
Expand All @@ -195,7 +186,6 @@ static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
gen_set_label(l1);
tcg_gen_movi_i32(ret, 0);
gen_set_label(l2);
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
Expand All @@ -212,15 +202,13 @@ static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
gen_set_label(l1);
tcg_gen_movi_i32(ret, 0);
gen_set_label(l2);
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_andi_i32(t0, arg2, 0x1F);
tcg_gen_rotl_i32(ret, arg1, t0);
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
static inline void gen_evmergehi(DisasContext *ctx)
Expand Down Expand Up @@ -257,8 +245,6 @@ static inline void gen_##name(DisasContext *ctx) \
tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
tcg_op(t0, t0, rA(ctx->opcode)); \
tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
\
tcg_temp_free_i32(t0); \
}
GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
Expand Down Expand Up @@ -341,7 +327,6 @@ static inline void gen_evmergelohi(DisasContext *ctx)
tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
tcg_temp_free(tmp);
} else {
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
Expand Down Expand Up @@ -394,7 +379,6 @@ static inline void gen_evsel(DisasContext *ctx)
gen_set_label(l3);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
gen_set_label(l4);
tcg_temp_free_i32(t0);
}

static void gen_evsel0(DisasContext *ctx)
Expand Down Expand Up @@ -456,9 +440,6 @@ static inline void gen_evmwumi(DisasContext *ctx)
tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */

gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */

tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}

static inline void gen_evmwumia(DisasContext *ctx)
Expand All @@ -477,7 +458,6 @@ static inline void gen_evmwumia(DisasContext *ctx)
/* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode));
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
tcg_temp_free_i64(tmp);
}

static inline void gen_evmwumiaa(DisasContext *ctx)
Expand Down Expand Up @@ -509,9 +489,6 @@ static inline void gen_evmwumiaa(DisasContext *ctx)

/* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc);

tcg_temp_free_i64(acc);
tcg_temp_free_i64(tmp);
}

static inline void gen_evmwsmi(DisasContext *ctx)
Expand All @@ -535,9 +512,6 @@ static inline void gen_evmwsmi(DisasContext *ctx)
tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */

gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */

tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}

static inline void gen_evmwsmia(DisasContext *ctx)
Expand All @@ -556,8 +530,6 @@ static inline void gen_evmwsmia(DisasContext *ctx)
/* acc := rD */
gen_load_gpr64(tmp, rD(ctx->opcode));
tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));

tcg_temp_free_i64(tmp);
}

static inline void gen_evmwsmiaa(DisasContext *ctx)
Expand Down Expand Up @@ -589,9 +561,6 @@ static inline void gen_evmwsmiaa(DisasContext *ctx)

/* rD := acc */
gen_store_gpr64(rD(ctx->opcode), acc);

tcg_temp_free_i64(acc);
tcg_temp_free_i64(tmp);
}

GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
Expand Down Expand Up @@ -644,7 +613,6 @@ static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
TCGv_i64 t0 = tcg_temp_new_i64();
gen_qemu_ld64_i64(ctx, t0, addr);
gen_store_gpr64(rD(ctx->opcode), t0);
tcg_temp_free_i64(t0);
}

static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
Expand All @@ -668,7 +636,6 @@ static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
gen_addr_add(ctx, addr, addr, 2);
gen_qemu_ld16u(ctx, t0, addr);
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
tcg_temp_free(t0);
}

static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
Expand All @@ -678,7 +645,6 @@ static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
tcg_gen_shli_tl(t0, t0, 16);
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
tcg_temp_free(t0);
}

static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
Expand All @@ -687,7 +653,6 @@ static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
gen_qemu_ld16u(ctx, t0, addr);
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
tcg_temp_free(t0);
}

static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
Expand All @@ -696,7 +661,6 @@ static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
gen_qemu_ld16s(ctx, t0, addr);
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
tcg_temp_free(t0);
}

static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
Expand All @@ -707,7 +671,6 @@ static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
gen_addr_add(ctx, addr, addr, 2);
gen_qemu_ld16u(ctx, t0, addr);
tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
tcg_temp_free(t0);
}

static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
Expand All @@ -730,7 +693,6 @@ static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
gen_qemu_ld32u(ctx, t0, addr);
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
tcg_temp_free(t0);
}

static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
Expand All @@ -743,15 +705,13 @@ static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
gen_qemu_ld16u(ctx, t0, addr);
tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
tcg_temp_free(t0);
}

static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
{
TCGv_i64 t0 = tcg_temp_new_i64();
gen_load_gpr64(t0, rS(ctx->opcode));
gen_qemu_st64_i64(ctx, t0, addr);
tcg_temp_free_i64(t0);
}

static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
Expand All @@ -771,7 +731,6 @@ static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
gen_addr_add(ctx, addr, addr, 2);
tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
gen_qemu_st16(ctx, t0, addr);
tcg_temp_free(t0);
gen_addr_add(ctx, addr, addr, 2);
gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
Expand All @@ -784,7 +743,6 @@ static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
gen_addr_add(ctx, addr, addr, 2);
tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
gen_qemu_st16(ctx, t0, addr);
tcg_temp_free(t0);
}

static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
Expand Down Expand Up @@ -820,7 +778,6 @@ static void glue(gen_, name)(DisasContext *ctx) \
gen_addr_reg_index(ctx, t0); \
} \
gen_op_##name(ctx, t0); \
tcg_temp_free(t0); \
}

GEN_SPEOP_LDST(evldd, 0x00, 3);
Expand Down Expand Up @@ -923,7 +880,6 @@ static inline void gen_##name(DisasContext *ctx) \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
gen_helper_##name(t0, cpu_env, t0); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
tcg_temp_free_i32(t0); \
}
#define GEN_SPEFPUOP_CONV_32_64(name) \
static inline void gen_##name(DisasContext *ctx) \
Expand All @@ -939,8 +895,6 @@ static inline void gen_##name(DisasContext *ctx) \
gen_load_gpr64(t0, rB(ctx->opcode)); \
gen_helper_##name(t1, cpu_env, t0); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
tcg_temp_free_i64(t0); \
tcg_temp_free_i32(t1); \
}
#define GEN_SPEFPUOP_CONV_64_32(name) \
static inline void gen_##name(DisasContext *ctx) \
Expand All @@ -956,8 +910,6 @@ static inline void gen_##name(DisasContext *ctx) \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
gen_helper_##name(t0, cpu_env, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \
tcg_temp_free_i64(t0); \
tcg_temp_free_i32(t1); \
}
#define GEN_SPEFPUOP_CONV_64_64(name) \
static inline void gen_##name(DisasContext *ctx) \
Expand All @@ -971,7 +923,6 @@ static inline void gen_##name(DisasContext *ctx) \
gen_load_gpr64(t0, rB(ctx->opcode)); \
gen_helper_##name(t0, cpu_env, t0); \
gen_store_gpr64(rD(ctx->opcode), t0); \
tcg_temp_free_i64(t0); \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name) \
static inline void gen_##name(DisasContext *ctx) \
Expand All @@ -982,9 +933,6 @@ static inline void gen_##name(DisasContext *ctx) \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
gen_helper_##name(t0, cpu_env, t0, t1); \
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
\
tcg_temp_free_i32(t0); \
tcg_temp_free_i32(t1); \
}
#define GEN_SPEFPUOP_ARITH2_64_64(name) \
static inline void gen_##name(DisasContext *ctx) \
Expand All @@ -1000,8 +948,6 @@ static inline void gen_##name(DisasContext *ctx) \
gen_load_gpr64(t1, rB(ctx->opcode)); \
gen_helper_##name(t0, cpu_env, t0, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \
tcg_temp_free_i64(t0); \
tcg_temp_free_i64(t1); \
}
#define GEN_SPEFPUOP_COMP_32(name) \
static inline void gen_##name(DisasContext *ctx) \
Expand All @@ -1012,9 +958,6 @@ static inline void gen_##name(DisasContext *ctx) \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
\
tcg_temp_free_i32(t0); \
tcg_temp_free_i32(t1); \
}
#define GEN_SPEFPUOP_COMP_64(name) \
static inline void gen_##name(DisasContext *ctx) \
Expand All @@ -1029,8 +972,6 @@ static inline void gen_##name(DisasContext *ctx) \
gen_load_gpr64(t0, rA(ctx->opcode)); \
gen_load_gpr64(t1, rB(ctx->opcode)); \
gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
tcg_temp_free_i64(t0); \
tcg_temp_free_i64(t1); \
}

/* Single precision floating-point vectors operations */
Expand Down
2 changes: 0 additions & 2 deletions target/ppc/translate/storage-ctrl-impl.c.inc
View file
Expand Up @@ -212,7 +212,6 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
TCGv t0 = tcg_temp_new();
tcg_gen_ext32u_tl(t0, cpu_gpr[rb]);
gen_helper_tlbie(cpu_env, t0);
tcg_temp_free(t0);

#if defined(TARGET_PPC64)
/*
Expand Down Expand Up @@ -240,7 +239,6 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
tcg_temp_free_i32(t1);

return true;
#endif
Expand Down
296 changes: 4 additions & 292 deletions target/ppc/translate/vmx-impl.c.inc
View file

Large diffs are not rendered by default.

287 changes: 1 addition & 286 deletions target/ppc/translate/vsx-impl.c.inc
View file

Large diffs are not rendered by default.

24 changes: 0 additions & 24 deletions target/riscv/insn_trans/trans_rvb.c.inc
View file
Expand Up @@ -64,7 +64,6 @@ static void gen_clzw(TCGv ret, TCGv arg1)
TCGv t = tcg_temp_new();
tcg_gen_shli_tl(t, arg1, 32);
tcg_gen_clzi_tl(ret, t, 32);
tcg_temp_free(t);
}

static bool trans_clz(DisasContext *ctx, arg_clz *a)
Expand Down Expand Up @@ -161,8 +160,6 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)

gen_sbop_mask(t, shamt);
tcg_gen_or_tl(ret, arg1, t);

tcg_temp_free(t);
}

static bool trans_bset(DisasContext *ctx, arg_bset *a)
Expand All @@ -183,8 +180,6 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)

gen_sbop_mask(t, shamt);
tcg_gen_andc_tl(ret, arg1, t);

tcg_temp_free(t);
}

static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
Expand All @@ -205,8 +200,6 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)

gen_sbop_mask(t, shamt);
tcg_gen_xor_tl(ret, arg1, t);

tcg_temp_free(t);
}

static bool trans_binv(DisasContext *ctx, arg_binv *a)
Expand Down Expand Up @@ -252,9 +245,6 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)

/* sign-extend 64-bits */
tcg_gen_ext_i32_tl(ret, t1);

tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
}

static bool trans_ror(DisasContext *ctx, arg_ror *a)
Expand All @@ -270,8 +260,6 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
tcg_gen_trunc_tl_i32(t1, arg1);
tcg_gen_rotri_i32(t1, t1, shamt);
tcg_gen_ext_i32_tl(ret, t1);

tcg_temp_free_i32(t1);
}

static bool trans_rori(DisasContext *ctx, arg_rori *a)
Expand All @@ -294,9 +282,6 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)

/* sign-extend 64-bits */
tcg_gen_ext_i32_tl(ret, t1);

tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
}

static bool trans_rol(DisasContext *ctx, arg_rol *a)
Expand Down Expand Up @@ -340,8 +325,6 @@ static void gen_orc_b(TCGv ret, TCGv source1)

/* Replicate the lsb of each byte across the byte. */
tcg_gen_muli_tl(ret, tmp, 0xff);

tcg_temp_free(tmp);
}

static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
Expand All @@ -357,8 +340,6 @@ static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
\
tcg_gen_shli_tl(t, arg1, SHAMT); \
tcg_gen_add_tl(ret, t, arg2); \
\
tcg_temp_free(t); \
}

GEN_SHADD(1)
Expand Down Expand Up @@ -446,8 +427,6 @@ static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
\
tcg_gen_shli_tl(t, t, SHAMT); \
tcg_gen_add_tl(ret, t, arg2); \
\
tcg_temp_free(t); \
}

GEN_SHADD_UW(1)
Expand All @@ -472,7 +451,6 @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
TCGv t = tcg_temp_new();
tcg_gen_ext32u_tl(t, arg1);
tcg_gen_add_tl(ret, t, arg2);
tcg_temp_free(t);
}

static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
Expand Down Expand Up @@ -531,7 +509,6 @@ static void gen_packh(TCGv ret, TCGv src1, TCGv src2)

tcg_gen_ext8u_tl(t, src2);
tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
tcg_temp_free(t);
}

static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
Expand All @@ -540,7 +517,6 @@ static void gen_packw(TCGv ret, TCGv src1, TCGv src2)

tcg_gen_ext16s_tl(t, src2);
tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
tcg_temp_free(t);
}

static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
Expand Down
2 changes: 0 additions & 2 deletions target/riscv/insn_trans/trans_rvd.c.inc
View file
Expand Up @@ -250,7 +250,6 @@ static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a)
TCGv_i64 t0 = tcg_temp_new_i64();
tcg_gen_not_i64(t0, src2);
tcg_gen_deposit_i64(dest, t0, src1, 0, 63);
tcg_temp_free_i64(t0);
}
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
Expand All @@ -273,7 +272,6 @@ static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a)
TCGv_i64 t0 = tcg_temp_new_i64();
tcg_gen_andi_i64(t0, src2, INT64_MIN);
tcg_gen_xor_i64(dest, src1, t0);
tcg_temp_free_i64(t0);
}
gen_set_fpr_d(ctx, a->rd, dest);
mark_fs_dirty(ctx);
Expand Down
9 changes: 0 additions & 9 deletions target/riscv/insn_trans/trans_rvf.c.inc
View file
Expand Up @@ -233,9 +233,6 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a)

/* This formulation retains the nanboxing of rs2 in normal 'F'. */
tcg_gen_deposit_i64(dest, rs2, rs1, 0, 31);

tcg_temp_free_i64(rs1);
tcg_temp_free_i64(rs2);
} else {
tcg_gen_deposit_i64(dest, src2, src1, 0, 31);
tcg_gen_ext32s_i64(dest, dest);
Expand Down Expand Up @@ -281,15 +278,12 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
tcg_gen_nor_i64(rs2, rs2, mask);
tcg_gen_and_i64(dest, mask, rs1);
tcg_gen_or_i64(dest, dest, rs2);

tcg_temp_free_i64(rs2);
}
/* signed-extended intead of nanboxing for result if enable zfinx */
if (ctx->cfg_ptr->ext_zfinx) {
tcg_gen_ext32s_i64(dest, dest);
}
gen_set_fpr_hs(ctx, a->rd, dest);
tcg_temp_free_i64(rs1);
mark_fs_dirty(ctx);
return true;
}
Expand Down Expand Up @@ -329,14 +323,11 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsgnjx_s *a)
*/
tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(31, 1));
tcg_gen_xor_i64(dest, rs1, dest);

tcg_temp_free_i64(rs2);
}
/* signed-extended intead of nanboxing for result if enable zfinx */
if (ctx->cfg_ptr->ext_zfinx) {
tcg_gen_ext32s_i64(dest, dest);
}
tcg_temp_free_i64(rs1);
gen_set_fpr_hs(ctx, a->rd, dest);
mark_fs_dirty(ctx);
return true;
Expand Down
37 changes: 0 additions & 37 deletions target/riscv/insn_trans/trans_rvi.c.inc
View file
Expand Up @@ -62,7 +62,6 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
misaligned = gen_new_label();
tcg_gen_andi_tl(t0, cpu_pc, 0x2);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
tcg_temp_free(t0);
}

gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
Expand Down Expand Up @@ -108,8 +107,6 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl,
tcg_gen_xor_tl(tmp, ah, bh);
tcg_gen_and_tl(rl, rl, tmp);
tcg_gen_xor_tl(rl, rh, rl);

tcg_temp_free(tmp);
}
break;

Expand All @@ -128,8 +125,6 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl,
/* seed third word with 1, which will be result */
tcg_gen_sub2_tl(tmp, rh, ah, one, tmp, zero);
tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero);

tcg_temp_free(tmp);
}
break;

Expand All @@ -140,8 +135,6 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl,
if (invert) {
cond = tcg_invert_cond(cond);
}

tcg_temp_free(rh);
return cond;
}

Expand Down Expand Up @@ -169,8 +162,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
cond = gen_compare_i128(a->rs2 == 0,
tmp, src1, src1h, src2, src2h, cond);
tcg_gen_brcondi_tl(cond, tmp, 0, l);

tcg_temp_free(tmp);
} else {
tcg_gen_brcond_tl(cond, src1, src2, l);
}
Expand Down Expand Up @@ -254,8 +245,6 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
}

gen_set_gpr128(ctx, a->rd, destl, desth);

tcg_temp_free(addrl);
return true;
}

Expand Down Expand Up @@ -344,8 +333,6 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
tcg_gen_addi_tl(addrl, addrl, 8);
tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ);
}

tcg_temp_free(addrl);
return true;
}

Expand Down Expand Up @@ -568,14 +555,6 @@ static void gen_sll_i128(TCGv destl, TCGv desth,

tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, zero, ll);
tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, ll, h1);

tcg_temp_free(ls);
tcg_temp_free(rs);
tcg_temp_free(hs);
tcg_temp_free(ll);
tcg_temp_free(lr);
tcg_temp_free(h0);
tcg_temp_free(h1);
}

static bool trans_sll(DisasContext *ctx, arg_sll *a)
Expand Down Expand Up @@ -618,14 +597,6 @@ static void gen_srl_i128(TCGv destl, TCGv desth,

tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, zero, h1);

tcg_temp_free(ls);
tcg_temp_free(rs);
tcg_temp_free(hs);
tcg_temp_free(ll);
tcg_temp_free(lr);
tcg_temp_free(h0);
tcg_temp_free(h1);
}

static bool trans_srl(DisasContext *ctx, arg_srl *a)
Expand Down Expand Up @@ -659,14 +630,6 @@ static void gen_sra_i128(TCGv destl, TCGv desth,

tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0);
tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, lr, h1);

tcg_temp_free(ls);
tcg_temp_free(rs);
tcg_temp_free(hs);
tcg_temp_free(ll);
tcg_temp_free(lr);
tcg_temp_free(h0);
tcg_temp_free(h1);
}

static bool trans_sra(DisasContext *ctx, arg_sra *a)
Expand Down
15 changes: 0 additions & 15 deletions target/riscv/insn_trans/trans_rvk.c.inc
View file
Expand Up @@ -161,9 +161,6 @@ static bool gen_sha256(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
tcg_gen_ext_i32_tl(dest, t1);

gen_set_gpr(ctx, a->rd, dest);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
return true;
}

Expand Down Expand Up @@ -212,9 +209,6 @@ static bool gen_sha512_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
tcg_gen_trunc_i64_tl(dest, t1);

gen_set_gpr(ctx, a->rd, dest);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
return true;
}

Expand Down Expand Up @@ -271,9 +265,6 @@ static bool gen_sha512h_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
tcg_gen_trunc_i64_tl(dest, t1);

gen_set_gpr(ctx, a->rd, dest);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
return true;
}

Expand Down Expand Up @@ -310,9 +301,6 @@ static bool gen_sha512_rv64(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
tcg_gen_trunc_i64_tl(dest, t1);

gen_set_gpr(ctx, a->rd, dest);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
return true;
}

Expand Down Expand Up @@ -359,9 +347,6 @@ static bool gen_sm3(DisasContext *ctx, arg_r2 *a, int32_t b, int32_t c)
tcg_gen_xor_i32(t1, t1, t0);
tcg_gen_ext_i32_tl(dest, t1);
gen_set_gpr(ctx, a->rd, dest);

tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
return true;
}

Expand Down
33 changes: 0 additions & 33 deletions target/riscv/insn_trans/trans_rvm.c.inc
View file
Expand Up @@ -45,9 +45,6 @@ static void gen_mulhu_i128(TCGv r2, TCGv r3, TCGv al, TCGv ah, TCGv bl, TCGv bh)

tcg_gen_mulu2_tl(tmpl, tmph, ah, bh);
tcg_gen_add2_tl(r2, r3, r2, r3, tmpl, tmph);

tcg_temp_free(tmpl);
tcg_temp_free(tmph);
}

static void gen_mul_i128(TCGv rl, TCGv rh,
Expand All @@ -63,10 +60,6 @@ static void gen_mul_i128(TCGv rl, TCGv rh,
tcg_gen_add2_tl(rh, tmpx, rh, zero, tmpl, tmph);
tcg_gen_mulu2_tl(tmpl, tmph, rs1h, rs2l);
tcg_gen_add2_tl(rh, tmph, rh, tmpx, tmpl, tmph);

tcg_temp_free(tmpl);
tcg_temp_free(tmph);
tcg_temp_free(tmpx);
}

static bool trans_mul(DisasContext *ctx, arg_mul *a)
Expand All @@ -92,19 +85,13 @@ static void gen_mulh_i128(TCGv rl, TCGv rh,
tcg_gen_and_tl(t1h, t1h, rs1h);
tcg_gen_sub2_tl(t0l, t0h, rl, rh, t0l, t0h);
tcg_gen_sub2_tl(rl, rh, t0l, t0h, t1l, t1h);

tcg_temp_free(t0l);
tcg_temp_free(t0h);
tcg_temp_free(t1l);
tcg_temp_free(t1h);
}

static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
{
TCGv discard = tcg_temp_new();

tcg_gen_muls2_tl(discard, ret, s1, s2);
tcg_temp_free(discard);
}

static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
Expand Down Expand Up @@ -132,9 +119,6 @@ static void gen_mulhsu_i128(TCGv rl, TCGv rh,
tcg_gen_and_tl(t0l, t0h, rs2l);
tcg_gen_and_tl(t0h, t0h, rs2h);
tcg_gen_sub2_tl(rl, rh, rl, rh, t0l, t0h);

tcg_temp_free(t0l);
tcg_temp_free(t0h);
}

static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
Expand All @@ -147,9 +131,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
tcg_gen_and_tl(rl, rl, arg2);
tcg_gen_sub_tl(ret, rh, rl);

tcg_temp_free(rl);
tcg_temp_free(rh);
}

static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
Expand All @@ -160,8 +141,6 @@ static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_ext32s_tl(t1, arg1);
tcg_gen_ext32u_tl(t2, arg2);
tcg_gen_mul_tl(ret, t1, t2);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_gen_sari_tl(ret, ret, 32);
}

Expand All @@ -177,7 +156,6 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
TCGv discard = tcg_temp_new();

tcg_gen_mulu2_tl(discard, ret, s1, s2);
tcg_temp_free(discard);
}

static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
Expand Down Expand Up @@ -223,9 +201,6 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);

tcg_gen_div_tl(ret, temp1, temp2);

tcg_temp_free(temp1);
tcg_temp_free(temp2);
}

static bool trans_div(DisasContext *ctx, arg_div *a)
Expand Down Expand Up @@ -258,9 +233,6 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
tcg_gen_divu_tl(ret, temp1, temp2);

tcg_temp_free(temp1);
tcg_temp_free(temp2);
}

static bool trans_divu(DisasContext *ctx, arg_divu *a)
Expand Down Expand Up @@ -306,9 +278,6 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)

/* If div by zero, the required result is the original dividend. */
tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);

tcg_temp_free(temp1);
tcg_temp_free(temp2);
}

static bool trans_rem(DisasContext *ctx, arg_rem *a)
Expand Down Expand Up @@ -342,8 +311,6 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)

/* If div by zero, the required result is the original dividend. */
tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);

tcg_temp_free(temp);
}

static bool trans_remu(DisasContext *ctx, arg_remu *a)
Expand Down
59 changes: 2 additions & 57 deletions target/riscv/insn_trans/trans_rvv.c.inc
View file
Expand Up @@ -172,11 +172,6 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
gen_set_pc_imm(s, s->pc_succ_insn);
lookup_and_goto_ptr(s);
s->base.is_jmp = DISAS_NORETURN;

if (rd == 0 && rs1 == 0) {
tcg_temp_free(s1);
}

return true;
}

Expand Down Expand Up @@ -214,8 +209,8 @@ static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)

static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
{
TCGv s1 = tcg_const_tl(a->rs1);
TCGv s2 = tcg_const_tl(a->zimm);
TCGv s1 = tcg_constant_tl(a->rs1);
TCGv s2 = tcg_constant_tl(a->zimm);
return do_vsetivli(s, a->rd, s1, s2);
}

Expand Down Expand Up @@ -644,9 +639,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,

fn(dest, mask, base, cpu_env, desc);

tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);

if (!is_store) {
mark_vs_dirty(s);
}
Expand Down Expand Up @@ -809,9 +801,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,

fn(dest, mask, base, stride, cpu_env, desc);

tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);

if (!is_store) {
mark_vs_dirty(s);
}
Expand Down Expand Up @@ -920,10 +909,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,

fn(dest, mask, base, index, cpu_env, desc);

tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(index);

if (!is_store) {
mark_vs_dirty(s);
}
Expand Down Expand Up @@ -1063,8 +1048,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,

fn(dest, mask, base, cpu_env, desc);

tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
mark_vs_dirty(s);
gen_set_label(over);
return true;
Expand Down Expand Up @@ -1125,8 +1108,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,

fn(dest, base, cpu_env, desc);

tcg_temp_free_ptr(dest);

if (!is_store) {
mark_vs_dirty(s);
}
Expand Down Expand Up @@ -1282,9 +1263,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,

fn(dest, mask, src1, src2, cpu_env, desc);

tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
mark_vs_dirty(s);
gen_set_label(over);
return true;
Expand Down Expand Up @@ -1315,7 +1293,6 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
src1, MAXSZ(s), MAXSZ(s));

tcg_temp_free_i64(src1);
mark_vs_dirty(s);
return true;
}
Expand Down Expand Up @@ -1450,9 +1427,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,

fn(dest, mask, src1, src2, cpu_env, desc);

tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
mark_vs_dirty(s);
gen_set_label(over);
return true;
Expand Down Expand Up @@ -1821,7 +1795,6 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
src1, MAXSZ(s), MAXSZ(s));

tcg_temp_free_i32(src1);
mark_vs_dirty(s);
return true;
}
Expand Down Expand Up @@ -2114,7 +2087,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
tcg_gen_ext_tl_i64(s1_i64, s1);
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), s1_i64);
tcg_temp_free_i64(s1_i64);
} else {
tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), s1);
Expand All @@ -2135,9 +2107,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
s->cfg_ptr->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1_i64, cpu_env, desc);

tcg_temp_free_ptr(dest);
tcg_temp_free_i64(s1_i64);
}

mark_vs_dirty(s);
Expand Down Expand Up @@ -2179,7 +2148,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, cpu_env, desc);

tcg_temp_free_ptr(dest);
mark_vs_dirty(s);
gen_set_label(over);
}
Expand Down Expand Up @@ -2372,10 +2340,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,

fn(dest, mask, t1, src2, cpu_env, desc);

tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
tcg_temp_free_i64(t1);
mark_vs_dirty(s);
gen_set_label(over);
return true;
Expand Down Expand Up @@ -2761,11 +2725,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)

fns[s->sew - 1](dest, t1, cpu_env, desc);

tcg_temp_free_ptr(dest);
mark_vs_dirty(s);
gen_set_label(over);
}
tcg_temp_free_i64(t1);
return true;
}
return false;
Expand Down Expand Up @@ -3140,10 +3102,6 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a)

gen_helper_vcpop_m(dst, mask, src2, cpu_env, desc);
gen_set_gpr(s, a->rd, dst);

tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);

return true;
}
return false;
Expand Down Expand Up @@ -3173,9 +3131,6 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)

gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc);
gen_set_gpr(s, a->rd, dst);

tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
return true;
}
return false;
Expand Down Expand Up @@ -3370,8 +3325,6 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
/* Perform the load. */
load_element(dest, base,
vreg_ofs(s, vreg), s->sew, false);
tcg_temp_free_ptr(base);
tcg_temp_free_i32(ofs);

/* Flush out-of-range indexing to zero. */
t_vlmax = tcg_constant_i64(vlmax);
Expand All @@ -3380,8 +3333,6 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,

tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
t_vlmax, dest, t_zero);

tcg_temp_free_i64(t_idx);
}

static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
Expand Down Expand Up @@ -3441,9 +3392,6 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
vec_element_loadi(s, t1, a->rs2, 0, true);
tcg_gen_trunc_i64_tl(dest, t1);
gen_set_gpr(s, a->rd, dest);
tcg_temp_free_i64(t1);
tcg_temp_free(dest);

return true;
}
return false;
Expand Down Expand Up @@ -3471,7 +3419,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
s1 = get_gpr(s, a->rs1, EXT_NONE);
tcg_gen_ext_tl_i64(t1, s1);
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
mark_vs_dirty(s);
gen_set_label(over);
return true;
Expand Down Expand Up @@ -3526,7 +3473,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
do_nanbox(s, t1, cpu_fpr[a->rs1]);

vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
mark_vs_dirty(s);
gen_set_label(over);
return true;
Expand Down Expand Up @@ -3635,7 +3581,6 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)

tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), dest);
tcg_temp_free_i64(dest);
mark_vs_dirty(s);
} else {
static gen_helper_opivx * const fns[4] = {
Expand Down
14 changes: 2 additions & 12 deletions target/riscv/insn_trans/trans_rvzfh.c.inc
View file
Expand Up @@ -51,7 +51,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
decode_save_opc(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
TCGv temp = temp_new(ctx);
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, t0, a->imm);
t0 = temp;
}
Expand Down Expand Up @@ -256,9 +256,6 @@ static bool trans_fsgnj_h(DisasContext *ctx, arg_fsgnj_h *a)

/* This formulation retains the nanboxing of rs2 in normal 'Zfh'. */
tcg_gen_deposit_i64(dest, rs2, rs1, 0, 15);

tcg_temp_free_i64(rs1);
tcg_temp_free_i64(rs2);
} else {
tcg_gen_deposit_i64(dest, src2, src1, 0, 15);
tcg_gen_ext16s_i64(dest, dest);
Expand Down Expand Up @@ -302,20 +299,16 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h *a)
* Replace bit 15 in rs1 with inverse in rs2.
* This formulation retains the nanboxing of rs1.
*/
mask = tcg_const_i64(~MAKE_64BIT_MASK(15, 1));
mask = tcg_constant_i64(~MAKE_64BIT_MASK(15, 1));
tcg_gen_not_i64(rs2, rs2);
tcg_gen_andc_i64(rs2, rs2, mask);
tcg_gen_and_i64(dest, mask, rs1);
tcg_gen_or_i64(dest, dest, rs2);

tcg_temp_free_i64(mask);
tcg_temp_free_i64(rs2);
}
/* signed-extended intead of nanboxing for result if enable zfinx */
if (ctx->cfg_ptr->ext_zfinx) {
tcg_gen_ext16s_i64(dest, dest);
}
tcg_temp_free_i64(rs1);
mark_fs_dirty(ctx);
return true;
}
Expand Down Expand Up @@ -355,14 +348,11 @@ static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsgnjx_h *a)
*/
tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(15, 1));
tcg_gen_xor_i64(dest, rs1, dest);

tcg_temp_free_i64(rs2);
}
/* signed-extended intead of nanboxing for result if enable zfinx */
if (ctx->cfg_ptr->ext_zfinx) {
tcg_gen_ext16s_i64(dest, dest);
}
tcg_temp_free_i64(rs1);
mark_fs_dirty(ctx);
return true;
}
Expand Down
24 changes: 1 addition & 23 deletions target/riscv/insn_trans/trans_xthead.c.inc
View file
Expand Up @@ -100,10 +100,7 @@ static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2,
tcg_gen_shli_tl(offs, src2, imm2);
}

TCGv addr = get_address_indexed(ctx, rs1, offs);

tcg_temp_free(offs);
return addr;
return get_address_indexed(ctx, rs1, offs);
}

/* XTheadBa */
Expand All @@ -120,7 +117,6 @@ static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
TCGv t = tcg_temp_new(); \
tcg_gen_shli_tl(t, arg2, SHAMT); \
tcg_gen_add_tl(ret, t, arg1); \
tcg_temp_free(t); \
}

GEN_TH_ADDSL(1)
Expand Down Expand Up @@ -204,7 +200,6 @@ static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext)
gen_clz(dest, t);
}

tcg_temp_free(t);
gen_set_gpr(ctx, a->rd, dest);

return true;
Expand Down Expand Up @@ -469,7 +464,6 @@ static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a)

tcg_gen_extu_tl_i64(t1, src1);
tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32);
tcg_temp_free_i64(t1);
mark_fs_dirty(ctx);
return true;
}
Expand All @@ -489,7 +483,6 @@ static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a)
tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32);
tcg_gen_trunc_i64_tl(dst, t1);
gen_set_gpr(ctx, a->rd, dst);
tcg_temp_free_i64(t1);
mark_fs_dirty(ctx);
return true;
}
Expand All @@ -511,15 +504,12 @@ static bool gen_th_mac(DisasContext *ctx, arg_r *a,
extend_operand_func(tmp, src1);
extend_operand_func(tmp2, src2);
tcg_gen_mul_tl(tmp, tmp, tmp2);
tcg_temp_free(tmp2);
} else {
tcg_gen_mul_tl(tmp, src1, src2);
}

accumulate_func(dest, src0, tmp);
gen_set_gpr(ctx, a->rd, dest);
tcg_temp_free(tmp);

return true;
}

Expand Down Expand Up @@ -594,8 +584,6 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
tcg_gen_addi_tl(rs1, rs1, imm);
gen_set_gpr(ctx, a->rd, rd);
gen_set_gpr(ctx, a->rs1, rs1);

tcg_temp_free(addr);
return true;
}

Expand All @@ -615,8 +603,6 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
tcg_gen_addi_tl(rs1, rs1, imm);
gen_set_gpr(ctx, a->rs1, rs1);

tcg_temp_free(addr);
return true;
}

Expand Down Expand Up @@ -950,11 +936,6 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd1, t1);
gen_set_gpr(ctx, a->rd2, t2);

tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(addr1);
tcg_temp_free(addr2);
return true;
}

Expand Down Expand Up @@ -991,9 +972,6 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,

tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop);
tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop);

tcg_temp_free(addr1);
tcg_temp_free(addr2);
return true;
}

Expand Down
65 changes: 12 additions & 53 deletions target/riscv/translate.c
View file
Expand Up @@ -101,14 +101,8 @@ typedef struct DisasContext {
bool cfg_vta_all_1s;
target_ulong vstart;
bool vl_eq_vlmax;
uint8_t ntemp;
CPUState *cs;
TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
/* Space for 4 operands(1 dest and <=3 src) for float point computation */
TCGv_i64 ftemp[4];
uint8_t nftemp;
/* PointerMasking extension */
bool pm_mask_enabled;
bool pm_base_enabled;
Expand Down Expand Up @@ -207,12 +201,10 @@ static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
*/
static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
{
TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);
TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull);

tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
tcg_temp_free_i64(t_max);
tcg_temp_free_i64(t_nan);
}

static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
Expand Down Expand Up @@ -315,12 +307,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
*
* Further, we may provide an extension for word operations.
*/
static TCGv temp_new(DisasContext *ctx)
{
assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
return ctx->temp[ctx->ntemp++] = tcg_temp_new();
}

static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
{
TCGv t;
Expand All @@ -335,11 +321,11 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
case EXT_NONE:
break;
case EXT_SIGN:
t = temp_new(ctx);
t = tcg_temp_new();
tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
return t;
case EXT_ZERO:
t = temp_new(ctx);
t = tcg_temp_new();
tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
return t;
default:
Expand Down Expand Up @@ -367,15 +353,15 @@ static TCGv get_gprh(DisasContext *ctx, int reg_num)
static TCGv dest_gpr(DisasContext *ctx, int reg_num)
{
if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
return temp_new(ctx);
return tcg_temp_new();
}
return cpu_gpr[reg_num];
}

static TCGv dest_gprh(DisasContext *ctx, int reg_num)
{
if (reg_num == 0) {
return temp_new(ctx);
return tcg_temp_new();
}
return cpu_gprh[reg_num];
}
Expand Down Expand Up @@ -431,12 +417,6 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
}
}

static TCGv_i64 ftemp_new(DisasContext *ctx)
{
assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp));
return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64();
}

static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
{
if (!ctx->cfg_ptr->ext_zfinx) {
Expand All @@ -450,7 +430,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
case MXL_RV32:
#ifdef TARGET_RISCV32
{
TCGv_i64 t = ftemp_new(ctx);
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]);
return t;
}
Expand All @@ -476,7 +456,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num)
switch (get_xl(ctx)) {
case MXL_RV32:
{
TCGv_i64 t = ftemp_new(ctx);
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
return t;
}
Expand All @@ -496,12 +476,12 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
}

if (reg_num == 0) {
return ftemp_new(ctx);
return tcg_temp_new_i64();
}

switch (get_xl(ctx)) {
case MXL_RV32:
return ftemp_new(ctx);
return tcg_temp_new_i64();
#ifdef TARGET_RISCV64
case MXL_RV64:
return cpu_gpr[reg_num];
Expand Down Expand Up @@ -584,7 +564,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
/* Compute a canonical address from a register plus offset. */
static TCGv get_address(DisasContext *ctx, int rs1, int imm)
{
TCGv addr = temp_new(ctx);
TCGv addr = tcg_temp_new();
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);

tcg_gen_addi_tl(addr, src1, imm);
Expand All @@ -602,7 +582,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
/* Compute a canonical address from a register plus reg offset. */
static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
{
TCGv addr = temp_new(ctx);
TCGv addr = tcg_temp_new();
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);

tcg_gen_add_tl(addr, src1, offs);
Expand Down Expand Up @@ -639,7 +619,6 @@ static void mark_fs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_temp_free(tmp);
}

if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
Expand All @@ -650,7 +629,6 @@ static void mark_fs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_temp_free(tmp);
}
}
#else
Expand All @@ -675,7 +653,6 @@ static void mark_vs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
tcg_temp_free(tmp);
}

if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
Expand All @@ -686,7 +663,6 @@ static void mark_vs_dirty(DisasContext *ctx)
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
tcg_temp_free(tmp);
}
}
#else
Expand Down Expand Up @@ -1037,7 +1013,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
f128(dest, desth, src1, src1h, ext2);
gen_set_gpr128(ctx, a->rd, dest, desth);
}
tcg_temp_free(ext2);
return true;
}

Expand Down Expand Up @@ -1206,10 +1181,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->misa_mxl_max = env->misa_mxl_max;
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->cs = cs;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
ctx->nftemp = 0;
memset(ctx->ftemp, 0, sizeof(ctx->ftemp));
ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
Expand All @@ -1234,23 +1205,11 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu->env_ptr;
uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
int i;

ctx->ol = ctx->xl;
decode_opc(env, ctx, opcode16);
ctx->base.pc_next = ctx->pc_succ_insn;

for (i = ctx->ntemp - 1; i >= 0; --i) {
tcg_temp_free(ctx->temp[i]);
ctx->temp[i] = NULL;
}
ctx->ntemp = 0;
for (i = ctx->nftemp - 1; i >= 0; --i) {
tcg_temp_free_i64(ctx->ftemp[i]);
ctx->ftemp[i] = NULL;
}
ctx->nftemp = 0;

/* Only the first insn within a TB is allowed to cross a page boundary. */
if (ctx->base.is_jmp == DISAS_NEXT) {
if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
Expand Down
84 changes: 0 additions & 84 deletions target/rx/translate.c
View file

Large diffs are not rendered by default.

23 changes: 14 additions & 9 deletions target/s390x/tcg/translate.c
View file
Expand Up @@ -5886,9 +5886,14 @@ static void in2_a2(DisasContext *s, DisasOps *o)
}
#define SPEC_in2_a2 0

static TCGv gen_ri2(DisasContext *s)
{
return tcg_constant_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2);
}

static void in2_ri2(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2);
o->in2 = gen_ri2(s);
}
#define SPEC_in2_ri2 0

Expand Down Expand Up @@ -5976,29 +5981,29 @@ static void in2_m2_64a(DisasContext *s, DisasOps *o)

static void in2_mri2_16u(DisasContext *s, DisasOps *o)
{
in2_ri2(s, o);
tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
o->in2 = tcg_temp_new_i64();
tcg_gen_qemu_ld16u(o->in2, gen_ri2(s), get_mem_index(s));
}
#define SPEC_in2_mri2_16u 0

static void in2_mri2_32s(DisasContext *s, DisasOps *o)
{
in2_ri2(s, o);
tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
o->in2 = tcg_temp_new_i64();
tcg_gen_qemu_ld32s(o->in2, gen_ri2(s), get_mem_index(s));
}
#define SPEC_in2_mri2_32s 0

static void in2_mri2_32u(DisasContext *s, DisasOps *o)
{
in2_ri2(s, o);
tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
o->in2 = tcg_temp_new_i64();
tcg_gen_qemu_ld32u(o->in2, gen_ri2(s), get_mem_index(s));
}
#define SPEC_in2_mri2_32u 0

static void in2_mri2_64(DisasContext *s, DisasOps *o)
{
in2_ri2(s, o);
tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
o->in2 = tcg_temp_new_i64();
tcg_gen_qemu_ld64(o->in2, gen_ri2(s), get_mem_index(s));
}
#define SPEC_in2_mri2_64 0

Expand Down
110 changes: 0 additions & 110 deletions target/sh4/translate.c
View file

Large diffs are not rendered by default.

121 changes: 54 additions & 67 deletions target/sparc/mmu_helper.c
View file
Expand Up @@ -64,10 +64,9 @@ static const int perm_table[2][8] = {
}
};

static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
int *prot, int *access_index, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
int *access_index, target_ulong address,
int rw, int mmu_idx)
{
int access_perms = 0;
hwaddr pde_ptr;
Expand All @@ -80,20 +79,20 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
is_user = mmu_idx == MMU_USER_IDX;

if (mmu_idx == MMU_PHYS_IDX) {
*page_size = TARGET_PAGE_SIZE;
full->lg_page_size = TARGET_PAGE_BITS;
/* Boot mode: instruction fetches are taken from PROM */
if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) {
*physical = env->prom_addr | (address & 0x7ffffULL);
*prot = PAGE_READ | PAGE_EXEC;
full->phys_addr = env->prom_addr | (address & 0x7ffffULL);
full->prot = PAGE_READ | PAGE_EXEC;
return 0;
}
*physical = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
full->phys_addr = address;
full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return 0;
}

*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
*physical = 0xffffffffffff0000ULL;
full->phys_addr = 0xffffffffffff0000ULL;

/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */
Expand Down Expand Up @@ -157,16 +156,17 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
case 2: /* L3 PTE */
page_offset = 0;
}
*page_size = TARGET_PAGE_SIZE;
full->lg_page_size = TARGET_PAGE_BITS;
break;
case 2: /* L2 PTE */
page_offset = address & 0x3f000;
*page_size = 0x40000;
full->lg_page_size = 18;
}
break;
case 2: /* L1 PTE */
page_offset = address & 0xfff000;
*page_size = 0x1000000;
full->lg_page_size = 24;
break;
}
}

Expand All @@ -188,16 +188,16 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
}

/* the page can be put in the TLB */
*prot = perm_table[is_user][access_perms];
full->prot = perm_table[is_user][access_perms];
if (!(pde & PG_MODIFIED_MASK)) {
/* only set write access if already dirty... otherwise wait
for dirty access */
*prot &= ~PAGE_WRITE;
full->prot &= ~PAGE_WRITE;
}

/* Even if large ptes, we map only one 4KB page in the cache to
avoid filling it too fast */
*physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
full->phys_addr = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
return error_code;
}

Expand All @@ -208,11 +208,9 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
hwaddr paddr;
CPUTLBEntryFull full = {};
target_ulong vaddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
MemTxAttrs attrs = {};
int error_code = 0, access_index;

/*
* TODO: If we ever need tlb_vaddr_to_host for this target,
Expand All @@ -223,16 +221,15 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
assert(!probe);

address &= TARGET_PAGE_MASK;
error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
address, access_type,
mmu_idx, &page_size);
error_code = get_physical_address(env, &full, &access_index,
address, access_type, mmu_idx);
vaddr = address;
if (likely(error_code == 0)) {
qemu_log_mask(CPU_LOG_MMU,
"Translate at %" VADDR_PRIx " -> "
HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n",
address, paddr, vaddr);
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
address, full.phys_addr, vaddr);
tlb_set_page_full(cs, mmu_idx, vaddr, &full);
return true;
}

Expand All @@ -247,8 +244,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
permissions. If no mapping is available, redirect accesses to
neverland. Fake/overridden mappings will be flushed when
switching to normal mode. */
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
full.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
tlb_set_page_full(cs, mmu_idx, vaddr, &full);
return true;
} else {
if (access_type == MMU_INST_FETCH) {
Expand Down Expand Up @@ -545,8 +542,7 @@ static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw)
return sfsr;
}

static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
int *prot, MemTxAttrs *attrs,
static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full,
target_ulong address, int rw, int mmu_idx)
{
CPUState *cs = env_cpu(env);
Expand Down Expand Up @@ -579,11 +575,12 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,

for (i = 0; i < 64; i++) {
/* ctx match, vaddr match, valid? */
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
if (ultrasparc_tag_match(&env->dtlb[i], address, context,
&full->phys_addr)) {
int do_fault = 0;

if (TTE_IS_IE(env->dtlb[i].tte)) {
attrs->byte_swap = true;
full->attrs.byte_swap = true;
}

/* access ok? */
Expand Down Expand Up @@ -616,9 +613,9 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
}

if (!do_fault) {
*prot = PAGE_READ;
full->prot = PAGE_READ;
if (TTE_IS_W_OK(env->dtlb[i].tte)) {
*prot |= PAGE_WRITE;
full->prot |= PAGE_WRITE;
}

TTE_SET_USED(env->dtlb[i].tte);
Expand All @@ -645,8 +642,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
return 1;
}

static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
int *prot, MemTxAttrs *attrs,
static int get_physical_address_code(CPUSPARCState *env, CPUTLBEntryFull *full,
target_ulong address, int mmu_idx)
{
CPUState *cs = env_cpu(env);
Expand Down Expand Up @@ -681,7 +677,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
for (i = 0; i < 64; i++) {
/* ctx match, vaddr match, valid? */
if (ultrasparc_tag_match(&env->itlb[i],
address, context, physical)) {
address, context, &full->phys_addr)) {
/* access ok? */
if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
/* Fault status register */
Expand All @@ -708,7 +704,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,

return 1;
}
*prot = PAGE_EXEC;
full->prot = PAGE_EXEC;
TTE_SET_USED(env->itlb[i].tte);
return 0;
}
Expand All @@ -722,14 +718,13 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical,
return 1;
}

static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
int *prot, int *access_index, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
static int get_physical_address(CPUSPARCState *env, CPUTLBEntryFull *full,
int *access_index, target_ulong address,
int rw, int mmu_idx)
{
/* ??? We treat everything as a small page, then explicitly flush
everything when an entry is evicted. */
*page_size = TARGET_PAGE_SIZE;
full->lg_page_size = TARGET_PAGE_BITS;

/* safety net to catch wrong softmmu index use from dynamic code */
if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
Expand All @@ -747,17 +742,15 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
}

if (mmu_idx == MMU_PHYS_IDX) {
*physical = ultrasparc_truncate_physical(address);
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
full->phys_addr = ultrasparc_truncate_physical(address);
full->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return 0;
}

if (rw == 2) {
return get_physical_address_code(env, physical, prot, attrs, address,
mmu_idx);
return get_physical_address_code(env, full, address, mmu_idx);
} else {
return get_physical_address_data(env, physical, prot, attrs, address,
rw, mmu_idx);
return get_physical_address_data(env, full, address, rw, mmu_idx);
}
}

Expand All @@ -768,25 +761,17 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
target_ulong vaddr;
hwaddr paddr;
target_ulong page_size;
MemTxAttrs attrs = {};
int error_code = 0, prot, access_index;
CPUTLBEntryFull full = {};
int error_code = 0, access_index;

address &= TARGET_PAGE_MASK;
error_code = get_physical_address(env, &paddr, &prot, &access_index, &attrs,
address, access_type,
mmu_idx, &page_size);
error_code = get_physical_address(env, &full, &access_index,
address, access_type, mmu_idx);
if (likely(error_code == 0)) {
vaddr = address;

trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->tl,
env->dmmu.mmu_primary_context,
env->dmmu.mmu_secondary_context);

tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx,
page_size);
tlb_set_page_full(cs, mmu_idx, address, &full);
return true;
}
if (probe) {
Expand Down Expand Up @@ -888,12 +873,14 @@ void dump_mmu(CPUSPARCState *env)
static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
target_ulong addr, int rw, int mmu_idx)
{
target_ulong page_size;
int prot, access_index;
MemTxAttrs attrs = {};
CPUTLBEntryFull full = {};
int access_index, ret;

return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
rw, mmu_idx, &page_size);
ret = get_physical_address(env, &full, &access_index, addr, rw, mmu_idx);
if (ret == 0) {
*phys = full.phys_addr;
}
return ret;
}

#if defined(TARGET_SPARC64)
Expand Down