168 changes: 0 additions & 168 deletions scripts/tracetool/transform.py
View file

This file was deleted.

1 change: 1 addition & 0 deletions softmmu/runstate.c
View file
Expand Up @@ -46,6 +46,7 @@
#include "qemu/module.h"
#include "qemu/plugin.h"
#include "qemu/sockets.h"
#include "qemu/timer.h"
#include "qemu/thread.h"
#include "qom/object.h"
#include "qom/object_interfaces.h"
Expand Down
19 changes: 10 additions & 9 deletions softmmu/watchpoint.c
View file
Expand Up @@ -162,9 +162,12 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
/* this is currently used only by ARM BE32 */
addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
}

assert((flags & ~BP_MEM_ACCESS) == 0);
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (watchpoint_address_matches(wp, addr, len)
&& (wp->flags & flags)) {
int hit_flags = wp->flags & flags;

if (hit_flags && watchpoint_address_matches(wp, addr, len)) {
if (replay_running_debug()) {
/*
* replay_breakpoint reads icount.
Expand All @@ -184,16 +187,14 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
replay_breakpoint();
return;
}
if (flags == BP_MEM_READ) {
wp->flags |= BP_WATCHPOINT_HIT_READ;
} else {
wp->flags |= BP_WATCHPOINT_HIT_WRITE;
}

wp->flags |= hit_flags << BP_HIT_SHIFT;
wp->hitaddr = MAX(addr, wp->vaddr);
wp->hitattrs = attrs;

if (wp->flags & BP_CPU && cc->tcg_ops->debug_check_watchpoint &&
!cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
if (wp->flags & BP_CPU
&& cc->tcg_ops->debug_check_watchpoint
&& !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
wp->flags &= ~BP_WATCHPOINT_HIT;
continue;
}
Expand Down
71 changes: 0 additions & 71 deletions target/alpha/translate.c
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594 changes: 52 additions & 542 deletions target/arm/tcg/translate-a64.c
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Large diffs are not rendered by default.

2 changes: 0 additions & 2 deletions target/arm/tcg/translate-a64.h
View file
Expand Up @@ -18,8 +18,6 @@
#ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H

TCGv_i64 new_tmp_a64(DisasContext *s);
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
TCGv_i64 cpu_reg(DisasContext *s, int reg);
TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
Expand Down
20 changes: 0 additions & 20 deletions target/arm/tcg/translate-m-nocp.c
View file
Expand Up @@ -91,7 +91,6 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
} else {
gen_helper_v7m_vlstm(cpu_env, fptr);
}
tcg_temp_free_i32(fptr);

clear_eci_state(s);

Expand Down Expand Up @@ -303,8 +302,6 @@ static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,
tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK);
tcg_gen_or_i32(fpca, fpca, aspen);
tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label);
tcg_temp_free_i32(aspen);
tcg_temp_free_i32(fpca);
}

static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
Expand All @@ -328,7 +325,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
case ARM_VFP_FPSCR:
tmp = loadfn(s, opaque, true);
gen_helper_vfp_set_fpscr(cpu_env, tmp);
tcg_temp_free_i32(tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPSCR_NZCVQC:
Expand All @@ -351,7 +347,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
tcg_gen_or_i32(fpscr, fpscr, tmp);
store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
tcg_temp_free_i32(tmp);
break;
}
case ARM_VFP_FPCXT_NS:
Expand Down Expand Up @@ -400,8 +395,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
gen_helper_vfp_set_fpscr(cpu_env, tmp);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(sfpa);
break;
}
case ARM_VFP_VPR:
Expand All @@ -423,7 +416,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
store_cpu_field(vpr, v7m.vpr);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
tcg_temp_free_i32(tmp);
break;
}
default:
Expand Down Expand Up @@ -491,7 +483,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
tcg_gen_or_i32(tmp, tmp, sfpa);
tcg_temp_free_i32(sfpa);
/*
* Store result before updating FPSCR etc, in case
* it is a memory write which causes an exception.
Expand All @@ -505,7 +496,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
store_cpu_field(control, v7m.control[M_REG_S]);
fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
tcg_temp_free_i32(fpscr);
lookup_tb = true;
break;
}
Expand Down Expand Up @@ -546,17 +536,13 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
tcg_gen_or_i32(tmp, tmp, sfpa);
tcg_temp_free_i32(control);
/* Store result before updating FPSCR, in case it faults */
storefn(s, opaque, tmp, true);
/* If SFPA is zero then set FPSCR from FPDSCR_NS */
fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0),
fpdscr, fpscr);
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
tcg_temp_free_i32(sfpa);
tcg_temp_free_i32(fpdscr);
tcg_temp_free_i32(fpscr);
break;
}
case ARM_VFP_VPR:
Expand Down Expand Up @@ -598,7 +584,6 @@ static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value,
if (a->rt == 15) {
/* Set the 4 flag bits in the CPSR */
gen_set_nzcv(value);
tcg_temp_free_i32(value);
} else {
store_reg(s, a->rt, value);
}
Expand Down Expand Up @@ -666,7 +651,6 @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value,
if (do_access) {
gen_aa32_st_i32(s, value, addr, get_mem_index(s),
MO_UL | MO_ALIGN | s->be_data);
tcg_temp_free_i32(value);
}

if (a->w) {
Expand All @@ -675,8 +659,6 @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value,
tcg_gen_addi_i32(addr, addr, offset);
}
store_reg(s, a->rn, addr);
} else {
tcg_temp_free_i32(addr);
}
}

Expand Down Expand Up @@ -717,8 +699,6 @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque,
tcg_gen_addi_i32(addr, addr, offset);
}
store_reg(s, a->rn, addr);
} else {
tcg_temp_free_i32(addr);
}
return value;
}
Expand Down
52 changes: 0 additions & 52 deletions target/arm/tcg/translate-mve.c
View file
Expand Up @@ -178,7 +178,6 @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,

qreg = mve_qreg_ptr(a->qd);
fn(cpu_env, qreg, addr);
tcg_temp_free_ptr(qreg);

/*
* Writeback always happens after the last beat of the insn,
Expand All @@ -189,8 +188,6 @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
tcg_gen_addi_i32(addr, addr, offset);
}
store_reg(s, a->rn, addr);
} else {
tcg_temp_free_i32(addr);
}
mve_update_eci(s);
return true;
Expand Down Expand Up @@ -242,9 +239,6 @@ static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a, MVEGenLdStSGFn fn)
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, addr);
tcg_temp_free_ptr(qd);
tcg_temp_free_ptr(qm);
tcg_temp_free_i32(addr);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -341,8 +335,6 @@ static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_sg_imm *a,
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(offset));
tcg_temp_free_ptr(qd);
tcg_temp_free_ptr(qm);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -414,8 +406,6 @@ static bool do_vldst_il(DisasContext *s, arg_vldst_il *a, MVEGenLdStIlFn *fn,
if (a->w) {
tcg_gen_addi_i32(rn, rn, addrinc);
store_reg(s, a->rn, rn);
} else {
tcg_temp_free_i32(rn);
}
mve_update_and_store_eci(s);
return true;
Expand Down Expand Up @@ -506,9 +496,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
qd = mve_qreg_ptr(a->qd);
tcg_gen_dup_i32(a->size, rt, rt);
gen_helper_mve_vdup(cpu_env, qd, rt);
tcg_temp_free_ptr(qd);
}
tcg_temp_free_i32(rt);
mve_update_eci(s);
return true;
}
Expand All @@ -534,8 +522,6 @@ static bool do_1op_vec(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn,
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm);
tcg_temp_free_ptr(qd);
tcg_temp_free_ptr(qm);
}
mve_update_eci(s);
return true;
Expand Down Expand Up @@ -631,8 +617,6 @@ static bool do_vcvt_rmode(DisasContext *s, arg_1op *a,
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode)));
tcg_temp_free_ptr(qd);
tcg_temp_free_ptr(qm);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -821,9 +805,6 @@ static bool do_2op_vec(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn,
qn = mve_qreg_ptr(a->qn);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qn, qm);
tcg_temp_free_ptr(qd);
tcg_temp_free_ptr(qn);
tcg_temp_free_ptr(qm);
}
mve_update_eci(s);
return true;
Expand Down Expand Up @@ -1076,9 +1057,6 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
qn = mve_qreg_ptr(a->qn);
rm = load_reg(s, a->rm);
fn(cpu_env, qd, qn, rm);
tcg_temp_free_i32(rm);
tcg_temp_free_ptr(qd);
tcg_temp_free_ptr(qn);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -1204,23 +1182,18 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
tcg_temp_free_i32(rdalo);
tcg_temp_free_i32(rdahi);
} else {
rda = tcg_const_i64(0);
}

fn(rda, cpu_env, qn, qm, rda);
tcg_temp_free_ptr(qn);
tcg_temp_free_ptr(qm);

rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
tcg_temp_free_i64(rda);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -1312,8 +1285,6 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)

fn(rda, cpu_env, qn, qm, rda);
store_reg(s, a->rda, rda);
tcg_temp_free_ptr(qn);
tcg_temp_free_ptr(qm);

mve_update_eci(s);
return true;
Expand Down Expand Up @@ -1451,7 +1422,6 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
qm = mve_qreg_ptr(a->qm);
fns[a->size][a->u](rda, cpu_env, qm, rda);
store_reg(s, a->rda, rda);
tcg_temp_free_ptr(qm);

mve_update_eci(s);
return true;
Expand Down Expand Up @@ -1494,8 +1464,6 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
tcg_temp_free_i32(rdalo);
tcg_temp_free_i32(rdahi);
} else {
/* Accumulate starting at zero */
rda = tcg_const_i64(0);
Expand All @@ -1507,15 +1475,13 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
} else {
gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
}
tcg_temp_free_ptr(qm);

rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
tcg_temp_free_i64(rda);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -1543,7 +1509,6 @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn,
} else {
qd = mve_qreg_ptr(a->qd);
fn(cpu_env, qd, tcg_constant_i64(imm));
tcg_temp_free_ptr(qd);
}
mve_update_eci(s);
return true;
Expand Down Expand Up @@ -1616,8 +1581,6 @@ static bool do_2shift_vec(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
qd = mve_qreg_ptr(a->qd);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qd, qm, tcg_constant_i32(shift));
tcg_temp_free_ptr(qd);
tcg_temp_free_ptr(qm);
}
mve_update_eci(s);
return true;
Expand Down Expand Up @@ -1723,8 +1686,6 @@ static bool do_2shift_scalar(DisasContext *s, arg_shl_scalar *a,
qda = mve_qreg_ptr(a->qda);
rm = load_reg(s, a->rm);
fn(cpu_env, qda, qda, rm);
tcg_temp_free_ptr(qda);
tcg_temp_free_i32(rm);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -1868,7 +1829,6 @@ static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
rdm = load_reg(s, a->rdm);
gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
store_reg(s, a->rdm, rdm);
tcg_temp_free_ptr(qd);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -1898,7 +1858,6 @@ static bool do_vidup(DisasContext *s, arg_vidup *a, MVEGenVIDUPFn *fn)
rn = load_reg(s, a->rn);
fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm));
store_reg(s, a->rn, rn);
tcg_temp_free_ptr(qd);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -1934,8 +1893,6 @@ static bool do_viwdup(DisasContext *s, arg_viwdup *a, MVEGenVIWDUPFn *fn)
rm = load_reg(s, a->rm);
fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm));
store_reg(s, a->rn, rn);
tcg_temp_free_ptr(qd);
tcg_temp_free_i32(rm);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -2001,8 +1958,6 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVEGenCmpFn *fn)
qn = mve_qreg_ptr(a->qn);
qm = mve_qreg_ptr(a->qm);
fn(cpu_env, qn, qm);
tcg_temp_free_ptr(qn);
tcg_temp_free_ptr(qm);
if (a->mask) {
/* VPT */
gen_vpst(s, a->mask);
Expand Down Expand Up @@ -2034,8 +1989,6 @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_scalar *a,
rm = load_reg(s, a->rm);
}
fn(cpu_env, qn, rm);
tcg_temp_free_ptr(qn);
tcg_temp_free_i32(rm);
if (a->mask) {
/* VPT */
gen_vpst(s, a->mask);
Expand Down Expand Up @@ -2138,7 +2091,6 @@ static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, MVEGenVADDVFn fn)
rda = load_reg(s, a->rda);
fn(rda, cpu_env, qm, rda);
store_reg(s, a->rda, rda);
tcg_temp_free_ptr(qm);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -2203,8 +2155,6 @@ static bool do_vabav(DisasContext *s, arg_vabav *a, MVEGenVABAVFn *fn)
rda = load_reg(s, a->rda);
fn(rda, cpu_env, qn, qm, rda);
store_reg(s, a->rda, rda);
tcg_temp_free_ptr(qm);
tcg_temp_free_ptr(qn);
mve_update_eci(s);
return true;
}
Expand Down Expand Up @@ -2297,12 +2247,10 @@ static bool trans_VMOV_from_2gp(DisasContext *s, arg_VMOV_to_2gp *a)
if (!mve_skip_vmov(s, vd, a->idx, MO_32)) {
tmp = load_reg(s, a->rt);
write_neon_element32(tmp, vd, a->idx, MO_32);
tcg_temp_free_i32(tmp);
}
if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) {
tmp = load_reg(s, a->rt2);
write_neon_element32(tmp, vd + 1, a->idx, MO_32);
tcg_temp_free_i32(tmp);
}

mve_update_and_store_eci(s);
Expand Down
131 changes: 1 addition & 130 deletions target/arm/tcg/translate-neon.c
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28 changes: 0 additions & 28 deletions target/arm/tcg/translate-sme.c
View file
Expand Up @@ -97,7 +97,6 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
/* Add the byte offset to env to produce the final pointer. */
addr = tcg_temp_new_ptr();
tcg_gen_ext_i32_ptr(addr, tmp);
tcg_temp_free_i32(tmp);
tcg_gen_add_ptr(addr, addr, cpu_env);

return addr;
Expand Down Expand Up @@ -166,11 +165,6 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a)
h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc);
}
}

tcg_temp_free_ptr(t_za);
tcg_temp_free_ptr(t_zr);
tcg_temp_free_ptr(t_pg);

return true;
}

Expand Down Expand Up @@ -237,10 +231,6 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)

fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr,
tcg_constant_i32(desc));

tcg_temp_free_ptr(t_za);
tcg_temp_free_ptr(t_pg);
tcg_temp_free_i64(addr);
return true;
}

Expand All @@ -260,8 +250,6 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn)
base = get_tile_rowcol(s, MO_8, a->rv, imm, false);

fn(s, base, 0, svl, a->rn, imm * svl);

tcg_temp_free_ptr(base);
return true;
}

Expand All @@ -286,11 +274,6 @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz,
pm = pred_full_reg_ptr(s, a->pm);

fn(za, zn, pn, pm, tcg_constant_i32(desc));

tcg_temp_free_ptr(za);
tcg_temp_free_ptr(zn);
tcg_temp_free_ptr(pn);
tcg_temp_free_ptr(pm);
return true;
}

Expand Down Expand Up @@ -318,11 +301,6 @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz,
pm = pred_full_reg_ptr(s, a->pm);

fn(za, zn, zm, pn, pm, tcg_constant_i32(desc));

tcg_temp_free_ptr(za);
tcg_temp_free_ptr(zn);
tcg_temp_free_ptr(pn);
tcg_temp_free_ptr(pm);
return true;
}

Expand All @@ -346,12 +324,6 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
fpst = fpstatus_ptr(FPST_FPCR);

fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc));

tcg_temp_free_ptr(za);
tcg_temp_free_ptr(zn);
tcg_temp_free_ptr(pn);
tcg_temp_free_ptr(pm);
tcg_temp_free_ptr(fpst);
return true;
}

Expand Down
206 changes: 12 additions & 194 deletions target/arm/tcg/translate-sve.c
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193 changes: 0 additions & 193 deletions target/arm/tcg/translate-vfp.c
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281 changes: 5 additions & 276 deletions target/arm/tcg/translate.c
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7 changes: 0 additions & 7 deletions target/arm/tcg/translate.h
View file
Expand Up @@ -149,15 +149,11 @@ typedef struct DisasContext {
int c15_cpar;
/* TCG op of the current insn_start. */
TCGOp *insn_start;
#define TMP_A64_MAX 16
int tmp_a64_count;
TCGv_i64 tmp_a64[TMP_A64_MAX];
} DisasContext;

typedef struct DisasCompare {
TCGCond cond;
TCGv_i32 value;
bool value_global;
} DisasCompare;

/* Share the TCG temporaries common between 32 and 64 bit modes. */
Expand Down Expand Up @@ -304,7 +300,6 @@ static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
#endif

void arm_test_cc(DisasCompare *cmp, int cc);
void arm_free_cc(DisasCompare *cmp);
void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
void arm_gen_test_cc(int cc, TCGLabel *label);
MemOp pow2_align(unsigned i);
Expand Down Expand Up @@ -336,7 +331,6 @@ static inline void set_pstate_bits(uint32_t bits)
tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_ori_i32(p, p, bits);
tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_temp_free_i32(p);
}

/* Clear bits within PSTATE. */
Expand All @@ -349,7 +343,6 @@ static inline void clear_pstate_bits(uint32_t bits)
tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_gen_andi_i32(p, p, ~bits);
tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
tcg_temp_free_i32(p);
}

/* If the singlestep state is Active-not-pending, advance to Active-pending. */
Expand Down
251 changes: 0 additions & 251 deletions target/avr/translate.c
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113 changes: 0 additions & 113 deletions target/cris/translate.c
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49 changes: 1 addition & 48 deletions target/cris/translate_v10.c.inc
View file
Expand Up @@ -90,9 +90,6 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
gen_set_label(l1);
tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */
tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=F*/
tcg_temp_free(t1);
tcg_temp_free(tval);
tcg_temp_free(taddr);
}

static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
Expand Down Expand Up @@ -215,7 +212,6 @@ static int dec10_prep_move_m(CPUCRISState *env, DisasContext *dc,
else
t_gen_zext(dst, dst, memsize);
insn_len += crisv10_post_memaddr(dc, memsize);
tcg_temp_free(addr);
}

if (dc->mode == CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG)) {
Expand Down Expand Up @@ -258,7 +254,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
c = tcg_const_tl(simm);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
tcg_temp_free(c);
break;
case CRISV10_QIMM_CMPQ:
LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);
Expand All @@ -267,7 +262,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
c = tcg_const_tl(simm);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
tcg_temp_free(c);
break;
case CRISV10_QIMM_ADDQ:
LOG_DIS("addq %d, $r%d\n", imm, dc->dst);
Expand All @@ -276,7 +270,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
c = tcg_const_tl(imm);
cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
tcg_temp_free(c);
break;
case CRISV10_QIMM_ANDQ:
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
Expand All @@ -285,7 +278,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
c = tcg_const_tl(simm);
cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
tcg_temp_free(c);
break;
case CRISV10_QIMM_ASHQ:
LOG_DIS("ashq %d, $r%d\n", simm, dc->dst);
Expand All @@ -303,7 +295,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst],
c, cpu_PR[PR_CCS]);
}
tcg_temp_free(c);
break;
case CRISV10_QIMM_LSHQ:
LOG_DIS("lshq %d, $r%d\n", simm, dc->dst);
Expand All @@ -317,7 +308,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
c = tcg_const_tl(imm);
cris_alu(dc, op, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
tcg_temp_free(c);
break;
case CRISV10_QIMM_SUBQ:
LOG_DIS("subq %d, $r%d\n", imm, dc->dst);
Expand All @@ -326,7 +316,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
c = tcg_const_tl(imm);
cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
tcg_temp_free(c);
break;
case CRISV10_QIMM_ORQ:
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);
Expand All @@ -335,7 +324,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
c = tcg_const_tl(simm);
cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
tcg_temp_free(c);
break;

case CRISV10_QIMM_BCC_R0:
Expand Down Expand Up @@ -426,8 +414,6 @@ static void dec10_reg_alu(DisasContext *dc, int op, int size, int sext)

assert(dc->dst != 15);
cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size);
tcg_temp_free(t[0]);
tcg_temp_free(t[1]);
}

static void dec10_reg_bound(DisasContext *dc, int size)
Expand All @@ -437,7 +423,6 @@ static void dec10_reg_bound(DisasContext *dc, int size)
t = tcg_temp_new();
t_gen_zext(t, cpu_R[dc->src], size);
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
tcg_temp_free(t);
}

static void dec10_reg_mul(DisasContext *dc, int size, int sext)
Expand All @@ -451,9 +436,6 @@ static void dec10_reg_mul(DisasContext *dc, int size, int sext)
t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]);

cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4);

tcg_temp_free(t[0]);
tcg_temp_free(t[1]);
}


Expand All @@ -472,7 +454,6 @@ static void dec10_reg_movs(DisasContext *dc)
t_gen_zext(t, cpu_R[dc->src], size);

cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
tcg_temp_free(t);
}

static void dec10_reg_alux(DisasContext *dc, int op)
Expand All @@ -490,7 +471,6 @@ static void dec10_reg_alux(DisasContext *dc, int op)
t_gen_zext(t, cpu_R[dc->src], size);

cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
tcg_temp_free(t);
}

static void dec10_reg_mov_pr(DisasContext *dc)
Expand Down Expand Up @@ -522,7 +502,6 @@ static void dec10_reg_abs(DisasContext *dc)
tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0);

cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4);
tcg_temp_free(t0);
}

static void dec10_reg_swap(DisasContext *dc)
Expand All @@ -543,7 +522,6 @@ static void dec10_reg_swap(DisasContext *dc)
if (dc->dst & 1)
t_gen_swapr(t0, t0);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4);
tcg_temp_free(t0);
}

static void dec10_reg_scc(DisasContext *dc)
Expand Down Expand Up @@ -623,7 +601,6 @@ static unsigned int dec10_reg(DisasContext *dc)
LOG_DIS("addi r%d r%d size=%d\n", dc->src, dc->dst, dc->size);
tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3);
tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t);
tcg_temp_free(t);
break;
case CRISV10_REG_LSL:
LOG_DIS("lsl $r%d, $r%d sz=%d\n", dc->src, dc->dst, size);
Expand Down Expand Up @@ -669,7 +646,6 @@ static unsigned int dec10_reg(DisasContext *dc)
} else {
tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t);
}
tcg_temp_free(t);
cris_set_prefix(dc);
break;

Expand Down Expand Up @@ -778,7 +754,6 @@ static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc,
dc->delayed_branch = 1;
}

tcg_temp_free(t);
return insn_len;
}

Expand All @@ -792,20 +767,18 @@ static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size)
crisv10_prepare_memaddr(dc, addr, size);
gen_store_v10(dc, addr, cpu_R[dc->dst], size);
insn_len += crisv10_post_memaddr(dc, size);
tcg_temp_free(addr);

return insn_len;
}

static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
{
unsigned int insn_len = 2, rd = dc->dst;
TCGv t, addr;
TCGv t;

LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src);
cris_lock_irq(dc);

addr = tcg_temp_new();
t = tcg_temp_new();
insn_len += dec10_prep_move_m(env, dc, 0, 4, t);
if (rd == 15) {
Expand All @@ -816,8 +789,6 @@ static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc)
tcg_gen_mov_tl(cpu_PR[rd], t);
dc->cpustate_changed = 1;
}
tcg_temp_free(addr);
tcg_temp_free(t);
return insn_len;
}

Expand All @@ -835,12 +806,10 @@ static unsigned int dec10_ind_move_pr_m(DisasContext *dc)
cris_evaluate_flags(dc);
tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG);
gen_store_v10(dc, addr, t0, size);
tcg_temp_free(t0);
} else {
gen_store_v10(dc, addr, cpu_PR[dc->dst], size);
}
insn_len += crisv10_post_memaddr(dc, size);
tcg_temp_free(addr);
cris_lock_irq(dc);

return insn_len;
Expand Down Expand Up @@ -874,8 +843,6 @@ static void dec10_movem_r_m(DisasContext *dc)
if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
tcg_gen_mov_tl(cpu_R[dc->src], addr);
}
tcg_temp_free(addr);
tcg_temp_free(t0);
}

static void dec10_movem_m_r(DisasContext *dc)
Expand All @@ -902,8 +869,6 @@ static void dec10_movem_m_r(DisasContext *dc)
if (!pfix && dc->mode == CRISV10_MODE_AUTOINC) {
tcg_gen_mov_tl(cpu_R[dc->src], addr);
}
tcg_temp_free(addr);
tcg_temp_free(t0);
}

static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
Expand All @@ -922,9 +887,6 @@ static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc,
dc->delayed_branch = 1;
return insn_len;
}

cris_alu_m_free_temps(t);

return insn_len;
}

Expand All @@ -944,7 +906,6 @@ static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
dc->delayed_branch = 1;
}

tcg_temp_free(t);
return insn_len;
}

Expand All @@ -969,7 +930,6 @@ static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op)
dc->delayed_branch = 1;
}

tcg_temp_free(t);
return insn_len;
}

Expand Down Expand Up @@ -1057,8 +1017,6 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
c = tcg_const_tl(0);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
t[0], c, size);
tcg_temp_free(c);
cris_alu_m_free_temps(t);
break;
case CRISV10_IND_ADD:
LOG_DIS("add size=%d op=%d %d\n", size, dc->src, dc->dst);
Expand Down Expand Up @@ -1155,7 +1113,6 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)

c = tcg_const_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
tcg_temp_free(c);
dc->jmp_pc = imm;
cris_prepare_jmp(dc, JMP_DIRECT);
dc->delayed_branch--; /* v10 has no dslot here. */
Expand All @@ -1166,7 +1123,6 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
tcg_gen_movi_tl(env_pc, dc->pc + 2);
c = tcg_const_tl(dc->src + 2);
t_gen_mov_env_TN(trap_vector, c);
tcg_temp_free(c);
t_gen_raise_exception(EXCP_BREAK);
dc->base.is_jmp = DISAS_NORETURN;
return insn_len;
Expand All @@ -1176,13 +1132,11 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
t[0] = tcg_temp_new();
c = tcg_const_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
tcg_temp_free(c);
crisv10_prepare_memaddr(dc, t[0], size);
gen_load(dc, env_btarget, t[0], 4, 0);
insn_len += crisv10_post_memaddr(dc, size);
cris_prepare_jmp(dc, JMP_INDIRECT);
dc->delayed_branch--; /* v10 has no dslot here. */
tcg_temp_free(t[0]);
}
break;

Expand All @@ -1201,7 +1155,6 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
c = tcg_const_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
tcg_temp_free(c);
cris_prepare_jmp(dc, JMP_INDIRECT);
dc->delayed_branch--; /* v10 has no dslot here. */
break;
Expand Down
5 changes: 0 additions & 5 deletions target/hexagon/README
View file
Expand Up @@ -88,7 +88,6 @@ tcg_funcs_generated.c.inc
gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
gen_log_reg_write(RdN, RdV);
ctx_log_reg_write(ctx, RdN);
tcg_temp_free(RdV);
}

helper_funcs_generated.c.inc
Expand Down Expand Up @@ -160,12 +159,8 @@ istruction.
tcg_gen_addi_ptr(VvV, cpu_env, VvV_off);
TCGv slot = tcg_constant_tl(insn->slot);
gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV, slot);
tcg_temp_free(slot);
gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false);
ctx_log_vreg_write(ctx, VdN, EXT_DFL, false);
tcg_temp_free_ptr(VdV);
tcg_temp_free_ptr(VuV);
tcg_temp_free_ptr(VvV);
}

Notice that we also generate a variable named <operand>_off for each operand of
Expand Down
29 changes: 0 additions & 29 deletions target/hexagon/gen_tcg.h
View file
Expand Up @@ -77,7 +77,6 @@
tcg_gen_mov_tl(EA, RxV); \
gen_read_ireg(ireg, MuV, (SHIFT)); \
gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
tcg_temp_free(ireg); \
} while (0)

/* Instructions with multiple definitions */
Expand Down Expand Up @@ -116,7 +115,6 @@
gen_read_ireg(ireg, MuV, SHIFT); \
gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
LOAD; \
tcg_temp_free(ireg); \
} while (0)

#define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \
Expand Down Expand Up @@ -168,8 +166,6 @@
for (int i = 0; i < 2; i++) { \
gen_set_half(i, RdV, gen_get_byte(byte, i, tmp, (SIGN))); \
} \
tcg_temp_free(tmp); \
tcg_temp_free(byte); \
} while (0)

#define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \
Expand Down Expand Up @@ -222,8 +218,6 @@
for (int i = 0; i < 4; i++) { \
gen_set_half_i64(i, RddV, gen_get_byte(byte, i, tmp, (SIGN))); \
} \
tcg_temp_free(tmp); \
tcg_temp_free(byte); \
} while (0)

#define fGEN_TCG_L2_loadbzw4_io(SHORTCODE) \
Expand Down Expand Up @@ -273,8 +267,6 @@
tcg_gen_extu_i32_i64(tmp_i64, tmp); \
tcg_gen_shri_i64(RyyV, RyyV, 16); \
tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \
tcg_temp_free(tmp); \
tcg_temp_free_i64(tmp_i64); \
} while (0)

#define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \
Expand Down Expand Up @@ -304,8 +296,6 @@
tcg_gen_extu_i32_i64(tmp_i64, tmp); \
tcg_gen_shri_i64(RyyV, RyyV, 8); \
tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \
tcg_temp_free(tmp); \
tcg_temp_free_i64(tmp_i64); \
} while (0)

#define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \
Expand Down Expand Up @@ -347,7 +337,6 @@
tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
fLOAD(1, SIZE, SIGN, EA, RdV); \
gen_set_label(label); \
tcg_temp_free(LSB); \
} while (0)

#define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \
Expand Down Expand Up @@ -407,7 +396,6 @@
tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
fLOAD(1, 8, u, EA, RddV); \
gen_set_label(label); \
tcg_temp_free(LSB); \
} while (0)

#define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \
Expand All @@ -434,8 +422,6 @@
TCGv HALF = tcg_temp_new(); \
TCGv BYTE = tcg_temp_new(); \
SHORTCODE; \
tcg_temp_free(HALF); \
tcg_temp_free(BYTE); \
} while (0)

#define fGEN_TCG_STORE_pcr(SHIFT, STORE) \
Expand All @@ -447,9 +433,6 @@
gen_read_ireg(ireg, MuV, SHIFT); \
gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \
STORE; \
tcg_temp_free(ireg); \
tcg_temp_free(HALF); \
tcg_temp_free(BYTE); \
} while (0)

#define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \
Expand Down Expand Up @@ -531,7 +514,6 @@
gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \
tcg_temp_free_i64(tmp); \
} while (0)

/*
Expand All @@ -547,7 +529,6 @@
gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \
tcg_gen_extrh_i64_i32(RdV, tmp); \
tcg_gen_extrl_i64_i32(PeV, tmp); \
tcg_temp_free_i64(tmp); \
} while (0)

/*
Expand All @@ -565,7 +546,6 @@
tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \
tcg_gen_extrl_i64_i32(PxV, carry); \
gen_8bitsof(PxV, PxV); \
tcg_temp_free_i64(carry); \
} while (0)

/* r5:4 = sub(r1:0, r3:2, p1):carry */
Expand All @@ -581,8 +561,6 @@
tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \
tcg_gen_extrl_i64_i32(PxV, carry); \
gen_8bitsof(PxV, PxV); \
tcg_temp_free_i64(carry); \
tcg_temp_free_i64(not_RttV); \
} while (0)

/*
Expand All @@ -607,9 +585,6 @@
tcg_gen_umin_tl(tmp, left, right); \
gen_set_byte_i64(i, RddV, tmp); \
} \
tcg_temp_free(left); \
tcg_temp_free(right); \
tcg_temp_free(tmp); \
} while (0)

#define fGEN_TCG_J2_call(SHORTCODE) \
Expand Down Expand Up @@ -815,14 +790,12 @@
TCGv LSB = tcg_temp_new(); \
COND; \
gen_cond_jump(ctx, TCG_COND_EQ, LSB, riV); \
tcg_temp_free(LSB); \
} while (0)
#define fGEN_TCG_cond_jumpf(COND) \
do { \
TCGv LSB = tcg_temp_new(); \
COND; \
gen_cond_jump(ctx, TCG_COND_NE, LSB, riV); \
tcg_temp_free(LSB); \
} while (0)

#define fGEN_TCG_J2_jumpt(SHORTCODE) \
Expand Down Expand Up @@ -863,14 +836,12 @@
TCGv LSB = tcg_temp_new(); \
COND; \
gen_cond_jumpr(ctx, RsV, TCG_COND_EQ, LSB); \
tcg_temp_free(LSB); \
} while (0)
#define fGEN_TCG_cond_jumprf(COND) \
do { \
TCGv LSB = tcg_temp_new(); \
COND; \
gen_cond_jumpr(ctx, RsV, TCG_COND_NE, LSB); \
tcg_temp_free(LSB); \
} while (0)

#define fGEN_TCG_J2_jumprt(SHORTCODE) \
Expand Down
79 changes: 1 addition & 78 deletions target/hexagon/gen_tcg_funcs.py
View file
Expand Up @@ -26,10 +26,7 @@
## Helpers for gen_tcg_func
##
def gen_decl_ea_tcg(f, tag):
f.write(" TCGv EA = tcg_temp_new();\n")

def gen_free_ea_tcg(f):
f.write(" tcg_temp_free(EA);\n")
f.write(" TCGv EA G_GNUC_UNUSED = tcg_temp_new();\n")

def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
Expand Down Expand Up @@ -269,73 +266,6 @@ def genptr_decl_imm(f,immlett):
f.write(" int %s = insn->immed[%d];\n" % \
(hex_common.imm_name(immlett), i))

def genptr_free(f, tag, regtype, regid, regno):
if (regtype == "R"):
if (regid in {"dd", "ss", "tt", "xx", "yy"}):
f.write(" tcg_temp_free_i64(%s%sV);\n" % (regtype, regid))
elif (regid in {"d", "e", "x", "y"}):
f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid))
elif (regid not in {"s", "t", "u", "v"}):
print("Bad register parse: ",regtype,regid)
elif (regtype == "P"):
if (regid in {"d", "e", "x"}):
f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid))
elif (regid not in {"s", "t", "u", "v"}):
print("Bad register parse: ",regtype,regid)
elif (regtype == "C"):
if (regid in {"dd", "ss"}):
f.write(" tcg_temp_free_i64(%s%sV);\n" % (regtype, regid))
elif (regid in {"d", "s"}):
f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid))
else:
print("Bad register parse: ",regtype,regid)
elif (regtype == "M"):
if (regid != "u"):
print("Bad register parse: ", regtype, regid)
elif (regtype == "V"):
if (regid in {"dd", "uu", "vv", "xx", \
"d", "s", "u", "v", "w", "x", "y"}):
if (not hex_common.skip_qemu_helper(tag)):
f.write(" tcg_temp_free_ptr(%s%sV);\n" % \
(regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
elif (regtype == "Q"):
if (regid in {"d", "e", "s", "t", "u", "v", "x"}):
if (not hex_common.skip_qemu_helper(tag)):
f.write(" tcg_temp_free_ptr(%s%sV);\n" % \
(regtype, regid))
else:
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)

def genptr_free_new(f, tag, regtype, regid, regno):
if (regtype == "N"):
if (regid not in {"s", "t"}):
print("Bad register parse: ", regtype, regid)
elif (regtype == "P"):
if (regid not in {"t", "u", "v"}):
print("Bad register parse: ", regtype, regid)
elif (regtype == "O"):
if (regid != "s"):
print("Bad register parse: ", regtype, regid)
else:
print("Bad register parse: ", regtype, regid)

def genptr_free_opn(f,regtype,regid,i,tag):
if (hex_common.is_pair(regid)):
genptr_free(f, tag, regtype, regid, i)
elif (hex_common.is_single(regid)):
if hex_common.is_old_val(regtype, regid, tag):
genptr_free(f, tag, regtype, regid, i)
elif hex_common.is_new_val(regtype, regid, tag):
genptr_free_new(f, tag, regtype, regid, i)
else:
print("Bad register parse: ",regtype,regid,toss,numregs)
else:
print("Bad register parse: ",regtype,regid,toss,numregs)

def genptr_src_read(f, tag, regtype, regid):
if (regtype == "R"):
if (regid in {"ss", "tt", "xx", "yy"}):
Expand Down Expand Up @@ -578,7 +508,6 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
## <GEN>
## gen_log_reg_write(RdN, RdV);
## ctx_log_reg_write(ctx, RdN);
## tcg_temp_free(RdV);
## }
##
## where <GEN> depends on hex_common.skip_qemu_helper(tag)
Expand Down Expand Up @@ -692,12 +621,6 @@ def gen_tcg_func(f, tag, regs, imms):
if (hex_common.is_written(regid)):
genptr_dst_write_opn(f,regtype, regid, tag)

## Free all the operands (regs and immediates)
if hex_common.need_ea(tag): gen_free_ea_tcg(f)
for regtype,regid,toss,numregs in regs:
genptr_free_opn(f,regtype,regid,i,tag)
i += 1

f.write("}\n\n")

def gen_def_tcg_func(f, tag, tagregs, tagimms):
Expand Down
15 changes: 0 additions & 15 deletions target/hexagon/gen_tcg_hvx.h
View file
Expand Up @@ -136,7 +136,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
TCGLabel *end_label = gen_new_label(); \
tcg_gen_andi_tl(lsb, PsV, 1); \
tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \
tcg_temp_free(lsb); \
tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_gen_br(end_label); \
Expand Down Expand Up @@ -212,7 +211,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_andi_tl(shift, RtV, 15); \
tcg_gen_gvec_sars(MO_16, VdV_off, VuV_off, shift, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \
Expand All @@ -224,7 +222,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
sizeof(MMVector), sizeof(MMVector)); \
tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vasrw(SHORTCODE) \
Expand All @@ -233,7 +230,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_andi_tl(shift, RtV, 31); \
tcg_gen_gvec_sars(MO_32, VdV_off, VuV_off, shift, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \
Expand All @@ -245,7 +241,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
sizeof(MMVector), sizeof(MMVector)); \
tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vlsrb(SHORTCODE) \
Expand All @@ -254,7 +249,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_andi_tl(shift, RtV, 7); \
tcg_gen_gvec_shrs(MO_8, VdV_off, VuV_off, shift, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vlsrh(SHORTCODE) \
Expand All @@ -263,7 +257,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_andi_tl(shift, RtV, 15); \
tcg_gen_gvec_shrs(MO_16, VdV_off, VuV_off, shift, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vlsrw(SHORTCODE) \
Expand All @@ -272,7 +265,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_andi_tl(shift, RtV, 31); \
tcg_gen_gvec_shrs(MO_32, VdV_off, VuV_off, shift, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

/* Vector shift left - various forms */
Expand All @@ -282,7 +274,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_andi_tl(shift, RtV, 7); \
tcg_gen_gvec_shls(MO_8, VdV_off, VuV_off, shift, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vaslh(SHORTCODE) \
Expand All @@ -291,7 +282,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_andi_tl(shift, RtV, 15); \
tcg_gen_gvec_shls(MO_16, VdV_off, VuV_off, shift, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \
Expand All @@ -303,7 +293,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
sizeof(MMVector), sizeof(MMVector)); \
tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vaslw(SHORTCODE) \
Expand All @@ -312,7 +301,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
tcg_gen_andi_tl(shift, RtV, 31); \
tcg_gen_gvec_shls(MO_32, VdV_off, VuV_off, shift, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

#define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \
Expand All @@ -324,7 +312,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
sizeof(MMVector), sizeof(MMVector)); \
tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \
sizeof(MMVector), sizeof(MMVector)); \
tcg_temp_free(shift); \
} while (0)

/* Vector max - various forms */
Expand Down Expand Up @@ -564,7 +551,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
GET_EA; \
PRED; \
tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \
tcg_temp_free(LSB); \
gen_vreg_load(ctx, DSTOFF, EA, true); \
INC; \
tcg_gen_br(end_label); \
Expand Down Expand Up @@ -735,7 +721,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
GET_EA; \
PRED; \
tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \
tcg_temp_free(LSB); \
gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \
INC; \
tcg_gen_br(end_label); \
Expand Down
58 changes: 0 additions & 58 deletions target/hexagon/genptr.c
View file
Expand Up @@ -65,8 +65,6 @@ static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val,
tcg_gen_andi_tl(new_val, new_val, ~reg_mask);
tcg_gen_andi_tl(tmp, cur_val, reg_mask);
tcg_gen_or_tl(new_val, new_val, tmp);

tcg_temp_free(tmp);
}
}

Expand All @@ -90,8 +88,6 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
}

tcg_temp_free(slot_mask);
}

void gen_log_reg_write(int rnum, TCGv val)
Expand Down Expand Up @@ -137,9 +133,6 @@ static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
slot_mask);
}

tcg_temp_free(val32);
tcg_temp_free(slot_mask);
}

static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
Expand All @@ -165,8 +158,6 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
/* Do this so HELPER(debug_commit_end) will know */
tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
}

tcg_temp_free(val32);
}

void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
Expand All @@ -189,8 +180,6 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
hex_new_pred_value[pnum], base_val);
}
tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);

tcg_temp_free(base_val);
}

static inline void gen_read_p3_0(TCGv control_reg)
Expand Down Expand Up @@ -238,7 +227,6 @@ static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
TCGv p3_0 = tcg_temp_new();
gen_read_p3_0(p3_0);
tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
tcg_temp_free(p3_0);
} else if (reg_num == HEX_REG_PC - 1) {
TCGv pc = tcg_constant_tl(ctx->base.pc_next);
tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc);
Expand All @@ -250,14 +238,11 @@ static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT],
ctx->num_insns);
tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt);
tcg_temp_free(pkt_cnt);
tcg_temp_free(insn_cnt);
} else if (reg_num == HEX_REG_QEMU_HVX_CNT) {
TCGv hvx_cnt = tcg_temp_new();
tcg_gen_addi_tl(hvx_cnt, hex_gpr[HEX_REG_QEMU_HVX_CNT],
ctx->num_hvx_insns);
tcg_gen_concat_i32_i64(dest, hvx_cnt, hex_gpr[reg_num + 1]);
tcg_temp_free(hvx_cnt);
} else {
tcg_gen_concat_i32_i64(dest,
hex_gpr[reg_num],
Expand All @@ -273,7 +258,6 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv control_reg)
gen_log_pred_write(ctx, i, hex_p8);
ctx_log_pred_write(ctx, i);
}
tcg_temp_free(hex_p8);
}

/*
Expand Down Expand Up @@ -312,7 +296,6 @@ static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
gen_write_p3_0(ctx, val32);
tcg_gen_extrh_i64_i32(val32, val);
gen_log_reg_write(reg_num + 1, val32);
tcg_temp_free(val32);
ctx_log_reg_write(ctx, reg_num + 1);
} else {
gen_log_reg_write_pair(reg_num, val);
Expand Down Expand Up @@ -346,7 +329,6 @@ TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
tcg_gen_extract_i64(res64, src, N * 8, 8);
}
tcg_gen_extrl_i64_i32(result, res64);
tcg_temp_free_i64(res64);

return result;
}
Expand All @@ -371,15 +353,13 @@ void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
TCGv_i64 src64 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(src64, src);
tcg_gen_deposit_i64(result, result, src64, N * 16, 16);
tcg_temp_free_i64(src64);
}

void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
{
TCGv_i64 src64 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(src64, src);
tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
tcg_temp_free_i64(src64);
}

static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
Expand Down Expand Up @@ -412,7 +392,6 @@ static inline void gen_store_conditional4(DisasContext *ctx,
ctx->mem_idx, MO_32);
tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val,
one, zero);
tcg_temp_free(tmp);
tcg_gen_br(done);

gen_set_label(fail);
Expand All @@ -439,7 +418,6 @@ static inline void gen_store_conditional8(DisasContext *ctx,
tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
one, zero);
tcg_gen_extrl_i64_i32(pred, tmp);
tcg_temp_free_i64(tmp);
tcg_gen_br(done);

gen_set_label(fail);
Expand Down Expand Up @@ -607,12 +585,10 @@ static void gen_cmpnd_cmp_jmp(DisasContext *ctx,
TCGv pred = tcg_temp_new();
gen_compare(cond1, pred, arg1, arg2);
gen_log_pred_write(ctx, pnum, pred);
tcg_temp_free(pred);
} else {
TCGv pred = tcg_temp_new();
tcg_gen_mov_tl(pred, hex_new_pred_value[pnum]);
gen_cond_jump(ctx, cond2, pred, pc_off);
tcg_temp_free(pred);
}
}

Expand Down Expand Up @@ -666,12 +642,10 @@ static void gen_cmpnd_tstbit0_jmp(DisasContext *ctx,
tcg_gen_andi_tl(pred, arg, 1);
gen_8bitsof(pred, pred);
gen_log_pred_write(ctx, pnum, pred);
tcg_temp_free(pred);
} else {
TCGv pred = tcg_temp_new();
tcg_gen_mov_tl(pred, hex_new_pred_value[pnum]);
gen_cond_jump(ctx, cond, pred, pc_off);
tcg_temp_free(pred);
}
}

Expand All @@ -681,7 +655,6 @@ static void gen_testbit0_jumpnv(DisasContext *ctx,
TCGv pred = tcg_temp_new();
tcg_gen_andi_tl(pred, arg, 1);
gen_cond_jump(ctx, cond, pred, pc_off);
tcg_temp_free(pred);
}

static void gen_jump(DisasContext *ctx, int pc_off)
Expand Down Expand Up @@ -711,7 +684,6 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred,
tcg_gen_andi_tl(lsb, pred, 1);
gen_write_new_pc_pcrel(ctx, pc_off, cond, lsb);
tcg_gen_brcondi_tl(cond, lsb, 0, skip);
tcg_temp_free(lsb);
next_PC =
tcg_constant_tl(ctx->pkt->pc + ctx->pkt->encod_pkt_size_in_bytes);
gen_log_reg_write(HEX_REG_LR, next_PC);
Expand Down Expand Up @@ -771,8 +743,6 @@ static void gen_endloop0(DisasContext *ctx)
}
gen_set_label(label3);
}

tcg_temp_free(lpcfg);
}

static void gen_cmp_jumpnv(DisasContext *ctx,
Expand All @@ -781,7 +751,6 @@ static void gen_cmp_jumpnv(DisasContext *ctx,
TCGv pred = tcg_temp_new();
tcg_gen_setcond_tl(cond, pred, val, src);
gen_cond_jump(ctx, TCG_COND_EQ, pred, pc_off);
tcg_temp_free(pred);
}

static void gen_cmpi_jumpnv(DisasContext *ctx,
Expand All @@ -790,7 +759,6 @@ static void gen_cmpi_jumpnv(DisasContext *ctx,
TCGv pred = tcg_temp_new();
tcg_gen_setcondi_tl(cond, pred, val, src);
gen_cond_jump(ctx, TCG_COND_EQ, pred, pc_off);
tcg_temp_free(pred);
}

/* Shift left with saturation */
Expand Down Expand Up @@ -830,11 +798,6 @@ static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift_amt)
tcg_gen_or_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR], ovf);

tcg_gen_movcond_tl(TCG_COND_EQ, dst, dst_sar, src, dst, satval);

tcg_temp_free(sh32);
tcg_temp_free(dst_sar);
tcg_temp_free(ovf);
tcg_temp_free(satval);
}

static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
Expand All @@ -846,7 +809,6 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
TCGv tmp = tcg_temp_new();
tcg_gen_umin_tl(tmp, shift_amt, tcg_constant_tl(31));
tcg_gen_sar_tl(dst, src, tmp);
tcg_temp_free(tmp);
}

/* Bidirectional shift right with saturation */
Expand All @@ -869,8 +831,6 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
gen_sar(RdV, RsV, shift_amt);

gen_set_label(done);

tcg_temp_free(shift_amt);
}

/* Bidirectional shift left with saturation */
Expand All @@ -893,8 +853,6 @@ static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
gen_shl_sat(RdV, RsV, shift_amt);

gen_set_label(done);

tcg_temp_free(shift_amt);
}

static intptr_t vreg_src_off(DisasContext *ctx, int num)
Expand Down Expand Up @@ -924,7 +882,6 @@ static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num,
/* Don't do anything if the slot was cancelled */
tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1);
tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
tcg_temp_free(cancelled);
}

if (type != EXT_TMP) {
Expand Down Expand Up @@ -965,7 +922,6 @@ static void gen_log_qreg_write(intptr_t srcoff, int num, int vnew,
/* Don't do anything if the slot was cancelled */
tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1);
tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
tcg_temp_free(cancelled);
}

dstoff = offsetof(CPUHexagonState, future_QRegs[num]);
Expand All @@ -989,7 +945,6 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
tcg_gen_addi_tl(src, src, 8);
tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
}
tcg_temp_free_i64(tmp);
}

static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff,
Expand Down Expand Up @@ -1061,10 +1016,6 @@ static void vec_to_qvec(size_t size, intptr_t dstoff, intptr_t srcoff)

tcg_gen_st8_i64(mask, cpu_env, dstoff + i);
}
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(word);
tcg_temp_free_i64(bits);
tcg_temp_free_i64(mask);
}

void probe_noshuf_load(TCGv va, int s, int mi)
Expand All @@ -1088,7 +1039,6 @@ void gen_set_usr_field_if(int field, TCGv val)
tcg_gen_or_tl(hex_new_value[HEX_REG_USR],
hex_new_value[HEX_REG_USR],
tmp);
tcg_temp_free(tmp);
} else {
TCGLabel *skip_label = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, val, 0, skip_label);
Expand Down Expand Up @@ -1140,7 +1090,6 @@ void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
ovfl_64 = tcg_temp_new_i64();
tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source);
tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
tcg_temp_free_i64(ovfl_64);
}

void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width)
Expand All @@ -1158,7 +1107,6 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
ovfl_64 = tcg_temp_new_i64();
tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source);
tcg_gen_trunc_i64_tl(ovfl, ovfl_64);
tcg_temp_free_i64(ovfl_64);
}

/* Implements the fADDSAT64 macro in TCG */
Expand All @@ -1182,15 +1130,12 @@ void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)

/* if (xor & mask) */
tcg_gen_and_i64(cond1, xor, mask);
tcg_temp_free_i64(xor);
tcg_gen_brcondi_i64(TCG_COND_NE, cond1, 0, no_ovfl_label);
tcg_temp_free_i64(cond1);

/* else if ((a ^ sum) & mask) */
tcg_gen_xor_i64(cond2, a, sum);
tcg_gen_and_i64(cond2, cond2, mask);
tcg_gen_brcondi_i64(TCG_COND_NE, cond2, 0, ovfl_label);
tcg_temp_free_i64(cond2);
/* fallthrough to no_ovfl_label branch */

/* if branch */
Expand All @@ -1201,10 +1146,7 @@ void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
/* else if branch */
gen_set_label(ovfl_label);
tcg_gen_and_i64(cond3, sum, mask);
tcg_temp_free_i64(mask);
tcg_temp_free_i64(sum);
tcg_gen_movcond_i64(TCG_COND_NE, ret, cond3, zero, max_pos, max_neg);
tcg_temp_free_i64(cond3);
SET_USR_FIELD(USR_OVF, 1);

gen_set_label(ret_label);
Expand Down
8 changes: 0 additions & 8 deletions target/hexagon/idef-parser/README.rst
View file
Expand Up @@ -31,7 +31,6 @@ idef-parser will compile the above code into the following code:
TCGv_i32 tmp_0 = tcg_temp_new_i32();
tcg_gen_add_i32(tmp_0, RsV, RtV);
tcg_gen_mov_i32(RdV, tmp_0);
tcg_temp_free_i32(tmp_0);
}
The output of the compilation process will be a function, containing the
Expand Down Expand Up @@ -102,12 +101,6 @@ The result of the addition is now stored in the temporary, we move it into the
correct destination register. This code may seem inefficient, but QEMU will
perform some optimizations on the tinycode, reducing the unnecessary copy.

::

tcg_temp_free_i32(tmp_0);

Finally, we free the temporary we used to hold the addition result.

Parser Input
------------

Expand Down Expand Up @@ -524,7 +517,6 @@ instruction,
TCGv_i32 tmp_0 = tcg_temp_new_i32();
tcg_gen_add_i32(tmp_0, RsV, RsV);
tcg_gen_mov_i32(RdV, tmp_0);
tcg_temp_free_i32(tmp_0);
}

Here the bug, albeit hard to spot, is in ``tcg_gen_add_i32(tmp_0, RsV, RsV);``
Expand Down
1 change: 0 additions & 1 deletion target/hexagon/idef-parser/idef-parser.h
View file
Expand Up @@ -185,7 +185,6 @@ typedef struct HexValue {
unsigned bit_width; /**< Bit width of the rvalue */
HexSignedness signedness; /**< Unsigned flag for the rvalue */
bool is_dotnew; /**< rvalue of predicate type is dotnew? */
bool is_manual; /**< Opt out of automatic freeing of params */
} HexValue;

/**
Expand Down
14 changes: 1 addition & 13 deletions target/hexagon/idef-parser/idef-parser.y
View file
Expand Up @@ -269,9 +269,6 @@ statements : statements statement
statement : control_statement
| var_decl ';'
| rvalue ';'
{
gen_rvalue_free(c, &@1, &$1);
}
| code_block
| ';'
;
Expand Down Expand Up @@ -347,7 +344,6 @@ assign_statement : lvalue '=' rvalue
$3 = gen_rvalue_truncate(c, &@1, &$3);
$3 = rvalue_materialize(c, &@1, &$3);
OUT(c, &@1, "gen_write_new_pc(", &$3, ");\n");
gen_rvalue_free(c, &@1, &$3); /* Free temporary value */
}
| LOAD '(' IMM ',' IMM ',' SIGN ',' var ',' lvalue ')'
{
Expand Down Expand Up @@ -376,7 +372,6 @@ assign_statement : lvalue '=' rvalue
$3 = gen_rvalue_truncate(c, &@1, &$3);
$3 = rvalue_materialize(c, &@1, &$3);
OUT(c, &@1, "SET_USR_FIELD(USR_LPCFG, ", &$3, ");\n");
gen_rvalue_free(c, &@1, &$3);
}
| DEPOSIT '(' rvalue ',' rvalue ',' rvalue ')'
{
Expand Down Expand Up @@ -421,10 +416,6 @@ control_statement : frame_check
;

frame_check : FCHK '(' rvalue ',' rvalue ')' ';'
{
gen_rvalue_free(c, &@1, &$3);
gen_rvalue_free(c, &@1, &$5);
}
;

cancel_statement : LOAD_CANCEL
Expand Down Expand Up @@ -543,7 +534,6 @@ rvalue : FAIL
rvalue.imm.type = IMM_CONSTEXT;
rvalue.signedness = UNSIGNED;
rvalue.is_dotnew = false;
rvalue.is_manual = false;
$$ = rvalue;
}
| var
Expand Down Expand Up @@ -702,7 +692,6 @@ rvalue : FAIL
}
| rvalue '?'
{
$1.is_manual = true;
Ternary t = { 0 };
t.state = IN_LEFT;
t.cond = $1;
Expand Down Expand Up @@ -774,7 +763,6 @@ rvalue : FAIL
@1.last_column = @6.last_column;
$$ = gen_tmp(c, &@1, 32, UNSIGNED);
OUT(c, &@1, "gen_read_ireg(", &$$, ", ", &$3, ", ", &$6, ");\n");
gen_rvalue_free(c, &@1, &$3);
}
| CIRCADD '(' rvalue ',' rvalue ',' rvalue ')'
{
Expand All @@ -795,7 +783,7 @@ rvalue : FAIL
}
| LPCFG
{
$$ = gen_tmp_value(c, &@1, "0", 32, UNSIGNED);
$$ = gen_tmp(c, &@1, 32, UNSIGNED);
OUT(c, &@1, "GET_USR_FIELD(USR_LPCFG, ", &$$, ");\n");
}
| EXTRACT '(' rvalue ',' rvalue ')'
Expand Down
206 changes: 12 additions & 194 deletions target/hexagon/idef-parser/parser-helpers.c
View file

Large diffs are not rendered by default.

10 changes: 0 additions & 10 deletions target/hexagon/idef-parser/parser-helpers.h
View file
Expand Up @@ -154,12 +154,6 @@ HexValue gen_tmp(Context *c,
unsigned bit_width,
HexSignedness signedness);

HexValue gen_tmp_value(Context *c,
YYLTYPE *locp,
const char *value,
unsigned bit_width,
HexSignedness signedness);

HexValue gen_imm_value(Context *c __attribute__((unused)),
YYLTYPE *locp,
int value,
Expand All @@ -169,8 +163,6 @@ HexValue gen_imm_value(Context *c __attribute__((unused)),
HexValue gen_imm_qemu_tmp(Context *c, YYLTYPE *locp, unsigned bit_width,
HexSignedness signedness);

void gen_rvalue_free(Context *c, YYLTYPE *locp, HexValue *rvalue);

HexValue rvalue_materialize(Context *c, YYLTYPE *locp, HexValue *rvalue);

HexValue gen_rvalue_extend(Context *c, YYLTYPE *locp, HexValue *rvalue);
Expand Down Expand Up @@ -365,8 +357,6 @@ void emit_footer(Context *c);

void track_string(Context *c, GString *s);

void free_variables(Context *c, YYLTYPE *locp);

void free_instruction(Context *c);

void assert_signedness(Context *c,
Expand Down
7 changes: 0 additions & 7 deletions target/hexagon/macros.h
View file
Expand Up @@ -220,8 +220,6 @@ static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num)
tcg_gen_andi_tl(tmp, pred, 1);
tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero,
slot_mask, hex_slot_cancelled);
tcg_temp_free(slot_mask);
tcg_temp_free(tmp);
}
#define PRED_LOAD_CANCEL(PRED, EA) \
gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot)
Expand Down Expand Up @@ -376,10 +374,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
tcg_gen_deposit_tl(result, msb, lsb, 0, 7);

tcg_gen_shli_tl(result, result, shift);

tcg_temp_free(msb);
tcg_temp_free(lsb);

return result;
}
#define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT))
Expand Down Expand Up @@ -512,7 +506,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
TCGv tmp = tcg_temp_new(); \
tcg_gen_shli_tl(tmp, REG2, SCALE); \
tcg_gen_add_tl(EA, REG, tmp); \
tcg_temp_free(tmp); \
} while (0)
#define fEA_IRs(IMM, REG, SCALE) \
do { \
Expand Down
7 changes: 0 additions & 7 deletions target/hexagon/translate.c
View file
Expand Up @@ -481,7 +481,6 @@ static void gen_pred_writes(DisasContext *ctx)
hex_new_pred_value[pred_num],
hex_pred[pred_num]);
}
tcg_temp_free(pred_written);
} else {
for (i = 0; i < ctx->preg_log_idx; i++) {
int pred_num = ctx->preg_log[i];
Expand Down Expand Up @@ -536,7 +535,6 @@ void process_store(DisasContext *ctx, int slot_num)
/* Don't do anything if the slot was cancelled */
tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1);
tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
tcg_temp_free(cancelled);
}
{
TCGv address = tcg_temp_new();
Expand Down Expand Up @@ -586,7 +584,6 @@ void process_store(DisasContext *ctx, int slot_num)
gen_helper_commit_store(cpu_env, slot);
}
}
tcg_temp_free(address);
}
if (is_predicated) {
gen_set_label(label_end);
Expand Down Expand Up @@ -627,8 +624,6 @@ static void process_dczeroa(DisasContext *ctx)
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
tcg_gen_addi_tl(addr, addr, 8);
tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);

tcg_temp_free(addr);
}
}

Expand Down Expand Up @@ -673,7 +668,6 @@ static void gen_commit_hvx(DisasContext *ctx)

tcg_gen_andi_tl(cmp, hex_VRegs_updated, 1 << rnum);
tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip);
tcg_temp_free(cmp);
tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
gen_set_label(label_skip);
} else {
Expand Down Expand Up @@ -706,7 +700,6 @@ static void gen_commit_hvx(DisasContext *ctx)

tcg_gen_andi_tl(cmp, hex_QRegs_updated, 1 << rnum);
tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip);
tcg_temp_free(cmp);
tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size);
gen_set_label(label_skip);
} else {
Expand Down
93 changes: 1 addition & 92 deletions target/hppa/translate.c
View file

Large diffs are not rendered by default.

15 changes: 0 additions & 15 deletions target/i386/tcg/decode-new.c.inc
View file
Expand Up @@ -1567,20 +1567,6 @@ illegal:
return false;
}

static void decode_temp_free(X86DecodedOp *op)
{
if (op->v_ptr) {
tcg_temp_free_ptr(op->v_ptr);
}
}

static void decode_temps_free(X86DecodedInsn *decode)
{
decode_temp_free(&decode->op[0]);
decode_temp_free(&decode->op[1]);
decode_temp_free(&decode->op[2]);
}

/*
* Convert one instruction. s->base.is_jmp is set if the translation must
* be stopped.
Expand Down Expand Up @@ -1835,7 +1821,6 @@ static void disas_insn_new(DisasContext *s, CPUState *cpu, int b)
decode.e.gen(s, env, &decode);
gen_writeback(s, &decode, 0, s->T0);
}
decode_temps_free(&decode);
return;
illegal_op:
gen_illegal_opcode(s);
Expand Down
6 changes: 0 additions & 6 deletions target/i386/tcg/emit.c.inc
View file
Expand Up @@ -629,7 +629,6 @@ static inline void gen_ternary_sse(DisasContext *s, CPUX86State *env, X86Decoded
/* The format of the fourth input is Lx */
tcg_gen_addi_ptr(ptr3, cpu_env, ZMM_OFFSET(op3));
fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3);
tcg_temp_free_ptr(ptr3);
}
#define TERNARY_SSE(uname, uvname, lname) \
static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
Expand Down Expand Up @@ -1001,7 +1000,6 @@ static inline void gen_vsib_avx(DisasContext *s, CPUX86State *env, X86DecodedIns
int ymmh_ofs = vector_elem_offset(&decode->op[1], MO_128, 1);
tcg_gen_gvec_dup_imm(MO_64, ymmh_ofs, 16, 16, 0);
}
tcg_temp_free_ptr(index);
}
#define VSIB_AVX(uname, lname) \
static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) \
Expand Down Expand Up @@ -1627,7 +1625,6 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8);
}
}
tcg_temp_free(t);
}

static void gen_PSHUFW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
Expand Down Expand Up @@ -1762,7 +1759,6 @@ static void gen_PSRLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
} else {
gen_helper_psrldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec);
}
tcg_temp_free_ptr(imm_vec);
}

static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
Expand All @@ -1775,7 +1771,6 @@ static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
} else {
gen_helper_pslldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec);
}
tcg_temp_free_ptr(imm_vec);
}

static void gen_RORX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
Expand Down Expand Up @@ -2293,7 +2288,6 @@ static void gen_VZEROALL(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco
tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_t0));
gen_helper_memset(ptr, ptr, tcg_constant_i32(0),
tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg)));
tcg_temp_free_ptr(ptr);
}

static void gen_VZEROUPPER(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
Expand Down
96 changes: 11 additions & 85 deletions target/i386/tcg/translate.c
View file
Expand Up @@ -899,10 +899,6 @@ static void gen_compute_eflags(DisasContext *s)
gen_update_cc_op(s);
gen_helper_cc_compute_all(cpu_cc_src, dst, src1, src2, cpu_cc_op);
set_cc_op(s, CC_OP_EFLAGS);

if (dead) {
tcg_temp_free(zero);
}
}

typedef struct CCPrepare {
Expand Down Expand Up @@ -1650,7 +1646,6 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
} else {
tcg_gen_mov_tl(cpu_cc_src, shm1);
}
tcg_temp_free(z_tl);

/* Get the two potential CC_OP values into temporaries. */
tcg_gen_movi_i32(s->tmp2_i32, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot);
Expand All @@ -1666,8 +1661,6 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
s32 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(s32, count);
tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, oldop);
tcg_temp_free_i32(z32);
tcg_temp_free_i32(s32);

/* The CC_OP value is no longer predictable. */
set_cc_op(s, CC_OP_DYNAMIC);
Expand Down Expand Up @@ -1827,8 +1820,6 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
tcg_gen_movi_i32(s->tmp3_i32, CC_OP_EFLAGS);
tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0,
s->tmp2_i32, s->tmp3_i32);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);

/* The CC_OP value is no longer predictable. */
set_cc_op(s, CC_OP_DYNAMIC);
Expand Down Expand Up @@ -2049,7 +2040,6 @@ static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, int op1,
gen_op_st_rm_T0_A0(s, ot, op1);

gen_shift_flags(s, ot, s->T0, s->tmp0, count, is_right);
tcg_temp_free(count);
}

static void gen_shift(DisasContext *s1, int op, MemOp ot, int d, int s)
Expand Down Expand Up @@ -2513,13 +2503,6 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,
tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2,
s->T0, cpu_regs[reg]);
gen_op_mov_reg_v(s, ot, reg, s->T0);

if (cc.mask != -1) {
tcg_temp_free(cc.reg);
}
if (!cc.use_reg2) {
tcg_temp_free(cc.reg2);
}
}

static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg)
Expand Down Expand Up @@ -2748,7 +2731,6 @@ static void gen_set_hflag(DisasContext *s, uint32_t mask)
tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
tcg_gen_ori_i32(t, t, mask);
tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
tcg_temp_free_i32(t);
s->flags |= mask;
}
}
Expand All @@ -2760,7 +2742,6 @@ static void gen_reset_hflag(DisasContext *s, uint32_t mask)
tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags));
tcg_gen_andi_i32(t, t, ~mask);
tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags));
tcg_temp_free_i32(t);
s->flags &= ~mask;
}
}
Expand All @@ -2772,7 +2753,6 @@ static void gen_set_eflags(DisasContext *s, target_ulong mask)
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags));
tcg_gen_ori_tl(t, t, mask);
tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags));
tcg_temp_free(t);
}

static void gen_reset_eflags(DisasContext *s, target_ulong mask)
Expand All @@ -2782,7 +2762,6 @@ static void gen_reset_eflags(DisasContext *s, target_ulong mask)
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags));
tcg_gen_andi_tl(t, t, ~mask);
tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags));
tcg_temp_free(t);
}

/* Clear BND registers during legacy branches. */
Expand Down Expand Up @@ -3015,13 +2994,11 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm)
tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val,
s->mem_index, MO_TEUQ);
}
tcg_temp_free_i64(val);

/* Set tmp0 to match the required value of Z. */
tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp);
Z = tcg_temp_new();
tcg_gen_trunc_i64_tl(Z, cmp);
tcg_temp_free_i64(cmp);

/*
* Extract the result values for the register pair.
Expand All @@ -3042,12 +3019,10 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm)
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero,
s->T1, cpu_regs[R_EDX]);
}
tcg_temp_free_i64(old);

/* Update Z. */
gen_compute_eflags(s);
tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1);
tcg_temp_free(Z);
}

#ifdef TARGET_X86_64
Expand All @@ -3072,22 +3047,18 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm)
}

tcg_gen_extr_i128_i64(s->T0, s->T1, val);
tcg_temp_free_i128(cmp);
tcg_temp_free_i128(val);

/* Determine success after the fact. */
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]);
tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]);
tcg_gen_or_i64(t0, t0, t1);
tcg_temp_free_i64(t1);

/* Update Z. */
gen_compute_eflags(s);
tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0);
tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1);
tcg_temp_free_i64(t0);

/*
* Extract the result values for the register pair. We may do this
Expand Down Expand Up @@ -3437,10 +3408,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_neg_tl(t1, t0);
tcg_gen_atomic_cmpxchg_tl(t0, a0, t0, t1,
s->mem_index, ot | MO_LE);
tcg_temp_free(t1);
tcg_gen_brcond_tl(TCG_COND_NE, t0, t2, label1);

tcg_temp_free(t2);
tcg_gen_neg_tl(s->T0, t0);
} else {
tcg_gen_neg_tl(s->T0, s->T0);
Expand Down Expand Up @@ -3927,9 +3896,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_mov_tl(s->cc_srcT, cmpv);
tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv);
set_cc_op(s, CC_OP_SUBB + ot);
tcg_temp_free(oldv);
tcg_temp_free(newv);
tcg_temp_free(cmpv);
}
break;
case 0x1c7: /* cmpxchg8b */
Expand Down Expand Up @@ -4380,7 +4346,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (shift) {
TCGv imm = tcg_const_tl(x86_ldub_code(env, s));
gen_shiftd_rm_T1(s, ot, opreg, op, imm);
tcg_temp_free(imm);
} else {
gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
}
Expand Down Expand Up @@ -4614,7 +4579,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_st_tl(last_addr, cpu_env,
offsetof(CPUX86State, fpdp));
}
tcg_temp_free(last_addr);
} else {
/* register float ops */
opreg = rm;
Expand Down Expand Up @@ -5262,52 +5226,19 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
case 0x9d: /* popf */
gen_svm_check_intercept(s, SVM_EXIT_POPF);
if (check_vm86_iopl(s)) {
ot = gen_pop_T0(s);
int mask = TF_MASK | AC_MASK | ID_MASK | NT_MASK;

if (CPL(s) == 0) {
if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, s->T0,
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK |
IF_MASK |
IOPL_MASK)));
} else {
gen_helper_write_eflags(cpu_env, s->T0,
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK |
IF_MASK | IOPL_MASK)
& 0xffff));
}
} else {
if (CPL(s) <= IOPL(s)) {
if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, s->T0,
tcg_const_i32((TF_MASK |
AC_MASK |
ID_MASK |
NT_MASK |
IF_MASK)));
} else {
gen_helper_write_eflags(cpu_env, s->T0,
tcg_const_i32((TF_MASK |
AC_MASK |
ID_MASK |
NT_MASK |
IF_MASK)
& 0xffff));
}
} else {
if (dflag != MO_16) {
gen_helper_write_eflags(cpu_env, s->T0,
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK)));
} else {
gen_helper_write_eflags(cpu_env, s->T0,
tcg_const_i32((TF_MASK | AC_MASK |
ID_MASK | NT_MASK)
& 0xffff));
}
}
mask |= IF_MASK | IOPL_MASK;
} else if (CPL(s) <= IOPL(s)) {
mask |= IF_MASK;
}
if (dflag == MO_16) {
mask &= 0xffff;
}

ot = gen_pop_T0(s);
gen_helper_write_eflags(cpu_env, s->T0, tcg_constant_i32(mask));
gen_pop_update(s, ot);
set_cc_op(s, CC_OP_EFLAGS);
/* abort translation because TF/AC flag may change */
Expand Down Expand Up @@ -6279,9 +6210,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
gen_compute_eflags(s);
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}
break;
case 0x102: /* lar */
Expand All @@ -6308,7 +6236,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
gen_op_mov_reg_v(s, ot, reg, t0);
gen_set_label(label1);
set_cc_op(s, CC_OP_EFLAGS);
tcg_temp_free(t0);
}
break;
case 0x118:
Expand Down Expand Up @@ -6353,7 +6280,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
TCGv_i64 notu = tcg_temp_new_i64();
tcg_gen_not_i64(notu, cpu_bndu[reg]);
gen_bndck(env, s, modrm, TCG_COND_GTU, notu);
tcg_temp_free_i64(notu);
} else if (prefixes & PREFIX_DATA) {
/* bndmov -- from reg/mem */
if (reg >= 4 || s->aflag == MO_16) {
Expand Down
12 changes: 0 additions & 12 deletions target/loongarch/insn_trans/trans_arith.c.inc
View file
Expand Up @@ -100,14 +100,12 @@ static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv discard = tcg_temp_new();
tcg_gen_muls2_tl(discard, dest, src1, src2);
tcg_temp_free(discard);
}

static void gen_mulh_du(TCGv dest, TCGv src1, TCGv src2)
{
TCGv discard = tcg_temp_new();
tcg_gen_mulu2_tl(discard, dest, src1, src2);
tcg_temp_free(discard);
}

static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
Expand All @@ -129,9 +127,6 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
tcg_gen_and_tl(ret, ret, t0);
tcg_gen_or_tl(ret, ret, t1);
tcg_gen_movcond_tl(TCG_COND_NE, ret, ret, zero, ret, src2);

tcg_temp_free(t0);
tcg_temp_free(t1);
}

static void prep_divisor_du(TCGv ret, TCGv src2)
Expand All @@ -152,31 +147,27 @@ static void gen_div_d(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 = tcg_temp_new();
prep_divisor_d(t0, src1, src2);
tcg_gen_div_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
prep_divisor_d(t0, src1, src2);
tcg_gen_rem_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_div_du(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
prep_divisor_du(t0, src2);
tcg_gen_divu_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
prep_divisor_du(t0, src2);
tcg_gen_remu_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
Expand All @@ -185,7 +176,6 @@ static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
/* We need not check for integer overflow for div_w. */
prep_divisor_du(t0, src2);
tcg_gen_div_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)
Expand All @@ -194,15 +184,13 @@ static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)
/* We need not check for integer overflow for rem_w. */
prep_divisor_du(t0, src2);
tcg_gen_rem_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa)
{
TCGv t0 = tcg_temp_new();
tcg_gen_shli_tl(t0, src1, sa);
tcg_gen_add_tl(dest, t0, src2);
tcg_temp_free(t0);
}

static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a)
Expand Down
3 changes: 0 additions & 3 deletions target/loongarch/insn_trans/trans_atomic.c.inc
View file
Expand Up @@ -14,7 +14,6 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr));
tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval));
gen_set_gpr(a->rd, dest, EXT_NONE);
tcg_temp_free(t0);

return true;
}
Expand Down Expand Up @@ -43,8 +42,6 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval);
gen_set_label(done);
gen_set_gpr(a->rd, dest, EXT_NONE);
tcg_temp_free(t0);
tcg_temp_free(val);

return true;
}
Expand Down
12 changes: 0 additions & 12 deletions target/loongarch/insn_trans/trans_bit.c.inc
View file
Expand Up @@ -122,9 +122,6 @@ static void gen_revb_2h(TCGv dest, TCGv src1)
tcg_gen_and_tl(t1, src1, mask);
tcg_gen_shli_tl(t1, t1, 8);
tcg_gen_or_tl(dest, t0, t1);

tcg_temp_free(t0);
tcg_temp_free(t1);
}

static void gen_revb_4h(TCGv dest, TCGv src1)
Expand All @@ -138,9 +135,6 @@ static void gen_revb_4h(TCGv dest, TCGv src1)
tcg_gen_and_tl(t1, src1, mask);
tcg_gen_shli_tl(t1, t1, 8);
tcg_gen_or_tl(dest, t0, t1);

tcg_temp_free(t0);
tcg_temp_free(t1);
}

static void gen_revh_2w(TCGv dest, TCGv src1)
Expand All @@ -154,9 +148,6 @@ static void gen_revh_2w(TCGv dest, TCGv src1)
tcg_gen_and_i64(t0, t0, mask);
tcg_gen_shli_i64(t1, t1, 16);
tcg_gen_or_i64(dest, t1, t0);

tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}

static void gen_revh_d(TCGv dest, TCGv src1)
Expand All @@ -171,9 +162,6 @@ static void gen_revh_d(TCGv dest, TCGv src1)
tcg_gen_shli_tl(t0, t0, 16);
tcg_gen_or_tl(t0, t0, t1);
tcg_gen_rotri_tl(dest, t0, 32);

tcg_temp_free(t0);
tcg_temp_free(t1);
}

static void gen_maskeqz(TCGv dest, TCGv src1, TCGv src2)
Expand Down
3 changes: 0 additions & 3 deletions target/loongarch/insn_trans/trans_fcmp.c.inc
View file
Expand Up @@ -38,7 +38,6 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));

tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
tcg_temp_free(var);
return true;
}

Expand All @@ -57,7 +56,5 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));

tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));

tcg_temp_free(var);
return true;
}
20 changes: 2 additions & 18 deletions target/loongarch/insn_trans/trans_fmemory.c.inc
View file
Expand Up @@ -13,44 +13,34 @@ static void maybe_nanbox_load(TCGv freg, MemOp mop)
static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
{
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv temp = NULL;

CHECK_FPE;

if (a->imm) {
temp = tcg_temp_new();
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}

tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);

if (temp) {
tcg_temp_free(temp);
}

return true;
}

static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
{
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv temp = NULL;

CHECK_FPE;

if (a->imm) {
temp = tcg_temp_new();
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}

tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);

if (temp) {
tcg_temp_free(temp);
}
return true;
}

Expand All @@ -66,7 +56,6 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
tcg_temp_free(addr);

return true;
}
Expand All @@ -82,7 +71,6 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
addr = tcg_temp_new();
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
tcg_temp_free(addr);

return true;
}
Expand All @@ -100,7 +88,6 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
tcg_temp_free(addr);

return true;
}
Expand All @@ -117,7 +104,6 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
gen_helper_asrtgt_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
tcg_temp_free(addr);

return true;
}
Expand All @@ -135,7 +121,6 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
tcg_temp_free(addr);

return true;
}
Expand All @@ -152,7 +137,6 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
gen_helper_asrtle_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
tcg_temp_free(addr);

return true;
}
Expand Down
6 changes: 0 additions & 6 deletions target/loongarch/insn_trans/trans_fmov.c.inc
View file
Expand Up @@ -18,7 +18,6 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca]));
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero,
cpu_fpr[a->fj], cpu_fpr[a->fk]);
tcg_temp_free(cond);

return true;
}
Expand Down Expand Up @@ -82,9 +81,6 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)
tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
tcg_gen_or_i32(fcsr0, fcsr0, temp);
tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0));

tcg_temp_free_i32(temp);
tcg_temp_free_i32(fcsr0);
}

/*
Expand Down Expand Up @@ -134,7 +130,6 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)
t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1);
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
tcg_temp_free(t0);

return true;
}
Expand All @@ -157,7 +152,6 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)
t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1);
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
tcg_temp_free(t0);

return true;
}
Expand Down
34 changes: 4 additions & 30 deletions target/loongarch/insn_trans/trans_memory.c.inc
View file
Expand Up @@ -7,42 +7,30 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv temp = NULL;

if (a->imm) {
temp = tcg_temp_new();
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}

tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);

if (temp) {
tcg_temp_free(temp);
}

return true;
}

static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop)
{
TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv temp = NULL;

if (a->imm) {
temp = tcg_temp_new();
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}

tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);

if (temp) {
tcg_temp_free(temp);
}

return true;
}

Expand All @@ -56,7 +44,6 @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop)
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
tcg_temp_free(addr);

return true;
}
Expand All @@ -70,7 +57,6 @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop)

tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
tcg_temp_free(addr);

return true;
}
Expand Down Expand Up @@ -146,42 +132,30 @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv temp = NULL;

if (a->imm) {
temp = tcg_temp_new();
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}

tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);

if (temp) {
tcg_temp_free(temp);
}

return true;
}

static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
{
TCGv data = gpr_src(ctx, a->rd, EXT_NONE);
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv temp = NULL;

if (a->imm) {
temp = tcg_temp_new();
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}

tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);

if (temp) {
tcg_temp_free(temp);
}

return true;
}

Expand Down
6 changes: 1 addition & 5 deletions target/loongarch/insn_trans/trans_privileged.c.inc
View file
Expand Up @@ -243,7 +243,7 @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
dest = gpr_dst(ctx, a->rd, EXT_NONE);
csr->writefn(dest, cpu_env, src1);
} else {
dest = temp_new(ctx);
dest = tcg_temp_new();
tcg_gen_ld_tl(dest, cpu_env, csr->offset);
tcg_gen_st_tl(src1, cpu_env, csr->offset);
}
Expand Down Expand Up @@ -291,10 +291,6 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
tcg_gen_st_tl(newv, cpu_env, csr->offset);
}
gen_set_gpr(a->rd, oldv, EXT_NONE);

tcg_temp_free(temp);
tcg_temp_free(newv);
tcg_temp_free(oldv);
return true;
}

Expand Down
11 changes: 0 additions & 11 deletions target/loongarch/insn_trans/trans_shift.c.inc
View file
Expand Up @@ -8,47 +8,41 @@ static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_shl_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_shr_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_sar_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_shl_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_shr_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_sar_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)
Expand All @@ -64,18 +58,13 @@ static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)

tcg_gen_rotr_i32(t1, t1, t2);
tcg_gen_ext_i32_tl(dest, t1);

tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
tcg_temp_free(t0);
}

static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_rotr_tl(dest, src1, t0);
tcg_temp_free(t0);
}

static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
Expand Down
21 changes: 3 additions & 18 deletions target/loongarch/translate.c
View file
Expand Up @@ -85,9 +85,6 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
ctx->base.max_insns = MIN(ctx->base.max_insns, bound);

ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));

ctx->zero = tcg_constant_tl(0);
}

Expand All @@ -110,12 +107,6 @@ static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
*
* Further, we may provide an extension for word operations.
*/
static TCGv temp_new(DisasContext *ctx)
{
assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
return ctx->temp[ctx->ntemp++] = tcg_temp_new();
}

static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
{
TCGv t;
Expand All @@ -128,11 +119,11 @@ static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
case EXT_NONE:
return cpu_gpr[reg_num];
case EXT_SIGN:
t = temp_new(ctx);
t = tcg_temp_new();
tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
return t;
case EXT_ZERO:
t = temp_new(ctx);
t = tcg_temp_new();
tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
return t;
}
Expand All @@ -142,7 +133,7 @@ static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext)
{
if (reg_num == 0 || dst_ext) {
return temp_new(ctx);
return tcg_temp_new();
}
return cpu_gpr[reg_num];
}
Expand Down Expand Up @@ -195,12 +186,6 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
generate_exception(ctx, EXCCODE_INE);
}

for (int i = ctx->ntemp - 1; i >= 0; --i) {
tcg_temp_free(ctx->temp[i]);
ctx->temp[i] = NULL;
}
ctx->ntemp = 0;

ctx->base.pc_next += 4;
}

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3 changes: 0 additions & 3 deletions target/loongarch/translate.h
View file
Expand Up @@ -32,9 +32,6 @@ typedef struct DisasContext {
uint16_t mem_idx;
uint16_t plv;
TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];
uint8_t ntemp;
} DisasContext;

void generate_exception(DisasContext *ctx, int excp);
Expand Down