18 changes: 9 additions & 9 deletions accel/tcg/translate-all.c
View file
Expand Up @@ -134,7 +134,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)

for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
if (i == 0) {
prev = (!TARGET_TB_PCREL && j == 0 ? tb_pc(tb) : 0);
prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0);
} else {
prev = tcg_ctx->gen_insn_data[i - 1][j];
}
Expand Down Expand Up @@ -169,8 +169,8 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
}

memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
if (!TARGET_TB_PCREL) {
data[0] = tb_pc(tb);
if (!(tb_cflags(tb) & CF_PCREL)) {
data[0] = tb->pc;
}

/*
Expand Down Expand Up @@ -280,7 +280,7 @@ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb,
tcg_func_start(tcg_ctx);

tcg_ctx->cpu = env_cpu(env);
gen_intermediate_code(env_cpu(env), tb, *max_insns, pc, host_pc);
gen_intermediate_code(env_cpu(env), tb, max_insns, pc, host_pc);
assert(tb->size != 0);
tcg_ctx->cpu = NULL;
*max_insns = tb->icount;
Expand Down Expand Up @@ -340,9 +340,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu,

gen_code_buf = tcg_ctx->code_gen_ptr;
tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf);
#if !TARGET_TB_PCREL
tb->pc = pc;
#endif
if (!(cflags & CF_PCREL)) {
tb->pc = pc;
}
tb->cs_base = cs_base;
tb->flags = flags;
tb->cflags = cflags;
Expand Down Expand Up @@ -407,8 +407,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tb->tc.size = gen_code_size;

/*
* For TARGET_TB_PCREL, attribute all executions of the generated
* code to its first mapping.
* For CF_PCREL, attribute all executions of the generated code
* to its first mapping.
*/
perf_report_code(pc, tb, tcg_splitwx_to_rx(gen_code_buf));

Expand Down
6 changes: 3 additions & 3 deletions accel/tcg/translator.c
View file
Expand Up @@ -42,7 +42,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
}

void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc,
const TranslatorOps *ops, DisasContextBase *db)
{
Expand All @@ -55,7 +55,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
db->pc_next = pc;
db->is_jmp = DISAS_NEXT;
db->num_insns = 0;
db->max_insns = max_insns;
db->max_insns = *max_insns;
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
db->host_addr[0] = host_pc;
db->host_addr[1] = NULL;
Expand All @@ -78,7 +78,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
plugin_enabled = plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY);

while (true) {
db->num_insns++;
*max_insns = ++db->num_insns;
ops->insn_start(db, cpu);
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */

Expand Down
5 changes: 3 additions & 2 deletions accel/tcg/user-exec.c
View file
Expand Up @@ -761,13 +761,14 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra);
}

int probe_access_flags(CPUArchState *env, target_ulong addr,
int probe_access_flags(CPUArchState *env, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost, uintptr_t ra)
{
int flags;

flags = probe_access_internal(env, addr, 0, access_type, nonfault, ra);
g_assert(-(addr | TARGET_PAGE_MASK) >= size);
flags = probe_access_internal(env, addr, size, access_type, nonfault, ra);
*phost = flags ? NULL : g2h(env_cpu(env), addr);
return flags;
}
Expand Down
230 changes: 129 additions & 101 deletions docs/devel/tcg-ops.rst
View file
Expand Up @@ -7,67 +7,51 @@ TCG Intermediate Representation
Introduction
============

TCG (Tiny Code Generator) began as a generic backend for a C
compiler. It was simplified to be used in QEMU. It also has its roots
in the QOP code generator written by Paul Brook.
TCG (Tiny Code Generator) began as a generic backend for a C compiler.
It was simplified to be used in QEMU. It also has its roots in the
QOP code generator written by Paul Brook.

Definitions
===========

TCG receives RISC-like *TCG ops* and performs some optimizations on them,
including liveness analysis and trivial constant expression
evaluation. TCG ops are then implemented in the host CPU back end,
also known as the TCG target.

The TCG *target* is the architecture for which we generate the
code. It is of course not the same as the "target" of QEMU which is
the emulated architecture. As TCG started as a generic C backend used
for cross compiling, it is assumed that the TCG target is different
from the host, although it is never the case for QEMU.
The TCG *target* is the architecture for which we generate the code.
It is of course not the same as the "target" of QEMU which is the
emulated architecture. As TCG started as a generic C backend used
for cross compiling, the assumption was that TCG target might be
different from the host, although this is never the case for QEMU.

In this document, we use *guest* to specify what architecture we are
emulating; *target* always means the TCG target, the machine on which
we are running QEMU.

A TCG *function* corresponds to a QEMU Translated Block (TB).

A TCG *temporary* is a variable only live in a basic block. Temporaries are allocated explicitly in each function.

A TCG *local temporary* is a variable only live in a function. Local temporaries are allocated explicitly in each function.

A TCG *global* is a variable which is live in all the functions
(equivalent of a C global variable). They are defined before the
functions defined. A TCG global can be a memory location (e.g. a QEMU
CPU register), a fixed host register (e.g. the QEMU CPU state pointer)
or a memory location which is stored in a register outside QEMU TBs
(not implemented yet).

A TCG *basic block* corresponds to a list of instructions terminated
by a branch instruction.

An operation with *undefined behavior* may result in a crash.

An operation with *unspecified behavior* shall not crash. However,
the result may be one of several possibilities so may be considered
an *undefined result*.

Intermediate representation
===========================
Basic Blocks
============

Introduction
------------
A TCG *basic block* is a single entry, multiple exit region which
corresponds to a list of instructions terminated by a label, or
any branch instruction.

TCG instructions operate on variables which are temporaries, local
temporaries or globals. TCG instructions and variables are strongly
typed. Two types are supported: 32 bit integers and 64 bit
integers. Pointers are defined as an alias to 32 bit or 64 bit
integers depending on the TCG target word size.
A TCG *extended basic block* is a single entry, multiple exit region
which corresponds to a list of instructions terminated by a label or
an unconditional branch. Specifically, an extended basic block is
a sequence of basic blocks connected by the fall-through paths of
zero or more conditional branch instructions.

Each instruction has a fixed number of output variable operands, input
variable operands and always constant operands.
Operations
==========

The notable exception is the call instruction which has a variable
number of outputs and inputs.
TCG instructions or *ops* operate on TCG *variables*, both of which
are strongly typed. Each instruction has a fixed number of output
variable operands, input variable operands and constant operands.
Vector instructions have a field specifying the element size within
the vector. The notable exception is the call instruction which has
a variable number of outputs and inputs.

In the textual form, output operands usually come first, followed by
input operands, followed by constant operands. The output type is
Expand All @@ -77,68 +61,127 @@ included in the instruction name. Constants are prefixed with a '$'.
add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */
Variables
=========

Assumptions
-----------
* ``TEMP_FIXED``

Basic blocks
^^^^^^^^^^^^
There is one TCG *fixed global* variable, ``cpu_env``, which is
live in all translation blocks, and holds a pointer to ``CPUArchState``.
This variable is held in a host cpu register at all times in all
translation blocks.

* Basic blocks end after branches (e.g. brcond_i32 instruction),
goto_tb and exit_tb instructions.
* ``TEMP_GLOBAL``

* Basic blocks start after the end of a previous basic block, or at a
set_label instruction.
A TCG *global* is a variable which is live in all translation blocks,
and corresponds to memory location that is within ``CPUArchState``.
These may be specified as an offset from ``cpu_env``, in which case
they are called *direct globals*, or may be specified as an offset
from a direct global, in which case they are called *indirect globals*.
Even indirect globals should still reference memory within
``CPUArchState``. All TCG globals are defined during
``TCGCPUOps.initialize``, before any translation blocks are generated.

After the end of a basic block, the content of temporaries is
destroyed, but local temporaries and globals are preserved.
* ``TEMP_CONST``

Floating point types
^^^^^^^^^^^^^^^^^^^^
A TCG *constant* is a variable which is live throughout the entire
translation block, and contains a constant value. These variables
are allocated on demand during translation and are hashed so that
there is exactly one variable holding a given value.

* Floating point types are not supported yet
* ``TEMP_TB``

Pointers
^^^^^^^^
A TCG *translation block temporary* is a variable which is live
throughout the entire translation block, but dies on any exit.
These temporaries are allocated explicitly during translation.

* Depending on the TCG target, pointer size is 32 bit or 64
bit. The type ``TCG_TYPE_PTR`` is an alias to ``TCG_TYPE_I32`` or
``TCG_TYPE_I64``.
* ``TEMP_EBB``

Helpers
^^^^^^^
A TCG *extended basic block temporary* is a variable which is live
throughout an extended basic block, but dies on any exit.
These temporaries are allocated explicitly during translation.

Types
=====

* ``TCG_TYPE_I32``

A 32-bit integer.

* ``TCG_TYPE_I64``

A 64-bit integer. For 32-bit hosts, such variables are split into a pair
of variables with ``type=TCG_TYPE_I32`` and ``base_type=TCG_TYPE_I64``.
The ``temp_subindex`` for each indicates where it falls within the
host-endian representation.

* Using the tcg_gen_helper_x_y it is possible to call any function
taking i32, i64 or pointer types. By default, before calling a helper,
all globals are stored at their canonical location and it is assumed
that the function can modify them. By default, the helper is allowed to
modify the CPU state or raise an exception.
* ``TCG_TYPE_PTR``

This can be overridden using the following function modifiers:
An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size
of a pointer for the host.

- ``TCG_CALL_NO_READ_GLOBALS`` means that the helper does not read globals,
either directly or via an exception. They will not be saved to their
canonical locations before calling the helper.
* ``TCG_TYPE_REG``

- ``TCG_CALL_NO_WRITE_GLOBALS`` means that the helper does not modify any globals.
They will only be saved to their canonical location before calling helpers,
but they won't be reloaded afterwards.
An alias for ``TCG_TYPE_I32`` or ``TCG_TYPE_I64``, depending on the size
of the integer registers for the host. This may be larger
than ``TCG_TYPE_PTR`` depending on the host ABI.

- ``TCG_CALL_NO_SIDE_EFFECTS`` means that the call to the function is removed if
the return value is not used.
* ``TCG_TYPE_I128``

Note that ``TCG_CALL_NO_READ_GLOBALS`` implies ``TCG_CALL_NO_WRITE_GLOBALS``.
A 128-bit integer. For all hosts, such variables are split into a number
of variables with ``type=TCG_TYPE_REG`` and ``base_type=TCG_TYPE_I128``.
The ``temp_subindex`` for each indicates where it falls within the
host-endian representation.

On some TCG targets (e.g. x86), several calling conventions are
supported.
* ``TCG_TYPE_V64``

Branches
^^^^^^^^
A 64-bit vector. This type is valid only if the TCG target
sets ``TCG_TARGET_HAS_v64``.

* Use the instruction 'br' to jump to a label.
* ``TCG_TYPE_V128``

A 128-bit vector. This type is valid only if the TCG target
sets ``TCG_TARGET_HAS_v128``.

* ``TCG_TYPE_V256``

A 256-bit vector. This type is valid only if the TCG target
sets ``TCG_TARGET_HAS_v256``.

Helpers
=======

Helpers are registered in a guest-specific ``helper.h``,
which is processed to generate ``tcg_gen_helper_*`` functions.
With these functions it is possible to call a function taking
i32, i64, i128 or pointer types.

By default, before calling a helper, all globals are stored at their
canonical location. By default, the helper is allowed to modify the
CPU state (including the state represented by tcg globals)
or may raise an exception. This default can be overridden using the
following function modifiers:

* ``TCG_CALL_NO_WRITE_GLOBALS``

The helper does not modify any globals, but may read them.
Globals will be saved to their canonical location before calling helpers,
but need not be reloaded afterwards.

* ``TCG_CALL_NO_READ_GLOBALS``

The helper does not read globals, either directly or via an exception.
They will not be saved to their canonical locations before calling
the helper. This implies ``TCG_CALL_NO_WRITE_GLOBALS``.

* ``TCG_CALL_NO_SIDE_EFFECTS``

The call to the helper function may be removed if the return value is
not used. This means that it may not modify any CPU state nor may it
raise an exception.

Code Optimizations
------------------
==================

When generating instructions, you can count on at least the following
optimizations:
Expand Down Expand Up @@ -908,20 +951,9 @@ Recommended coding rules for best performance
often modified, e.g. the integer registers and the condition
codes. TCG will be able to use host registers to store them.

- Avoid globals stored in fixed registers. They must be used only to
store the pointer to the CPU state and possibly to store a pointer
to a register window.

- Use temporaries. Use local temporaries only when really needed,
e.g. when you need to use a value after a jump. Local temporaries
introduce a performance hit in the current TCG implementation: their
content is saved to memory at end of each basic block.

- Free temporaries and local temporaries when they are no longer used
(tcg_temp_free). Since tcg_const_x() also creates a temporary, you
should free it after it is used. Freeing temporaries does not yield
a better generated code, but it reduces the memory usage of TCG and
the speed of the translation.
- Free temporaries when they are no longer used (``tcg_temp_free``).
Since ``tcg_const_x`` also creates a temporary, you should free it
after it is used.

- Don't hesitate to use helpers for complicated or seldom used guest
instructions. There is little performance advantage in using TCG to
Expand All @@ -932,10 +964,6 @@ Recommended coding rules for best performance
the instruction is mostly doing loads and stores, and in those cases
inline TCG may still be faster for longer sequences.

- The hard limit on the number of TCG instructions you can generate
per guest instruction is set by ``MAX_OP_PER_INSTR`` in ``exec-all.h`` --
you cannot exceed this without risking a buffer overrun.

- Use the 'discard' instruction if you know that TCG won't be able to
prove that a given global is "dead" at a given program point. The
x86 guest uses it to improve the condition codes optimisation.
3 changes: 0 additions & 3 deletions include/exec/cpu-defs.h
View file
Expand Up @@ -54,9 +54,6 @@
# error TARGET_PAGE_BITS must be defined in cpu-param.h
# endif
#endif
#ifndef TARGET_TB_PCREL
# define TARGET_TB_PCREL 0
#endif

#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)

Expand Down
26 changes: 8 additions & 18 deletions include/exec/exec-all.h
View file
Expand Up @@ -447,6 +447,7 @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
* probe_access_flags:
* @env: CPUArchState
* @addr: guest virtual address to look up
* @size: size of the access
* @access_type: read, write or execute permission
* @mmu_idx: MMU index to use for lookup
* @nonfault: suppress the fault
Expand All @@ -461,7 +462,7 @@ static inline void *probe_read(CPUArchState *env, target_ulong addr, int size,
* Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags.
* For simplicity, all "mmio-like" flags are folded to TLB_MMIO.
*/
int probe_access_flags(CPUArchState *env, target_ulong addr,
int probe_access_flags(CPUArchState *env, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost, uintptr_t retaddr);

Expand All @@ -474,7 +475,7 @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
* and must be consumed or copied immediately, before any further
* access or changes to TLB @mmu_idx.
*/
int probe_access_full(CPUArchState *env, target_ulong addr,
int probe_access_full(CPUArchState *env, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost,
CPUTLBEntryFull **pfull, uintptr_t retaddr);
Expand Down Expand Up @@ -505,22 +506,20 @@ struct tb_tc {
};

struct TranslationBlock {
#if !TARGET_TB_PCREL
/*
* Guest PC corresponding to this block. This must be the true
* virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and
* targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
* privilege, must store those bits elsewhere.
*
* If TARGET_TB_PCREL, the opcodes for the TranslationBlock are
* written such that the TB is associated only with the physical
* page and may be run in any virtual address context. In this case,
* PC must always be taken from ENV in a target-specific manner.
* If CF_PCREL, the opcodes for the TranslationBlock are written
* such that the TB is associated only with the physical page and
* may be run in any virtual address context. In this case, PC
* must always be taken from ENV in a target-specific manner.
* Unwind information is taken as offsets from the page, to be
* deposited into the "current" PC.
*/
target_ulong pc;
#endif

/*
* Target-specific data associated with the TranslationBlock, e.g.:
Expand All @@ -545,6 +544,7 @@ struct TranslationBlock {
#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */
#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */
#define CF_PCREL 0x00200000 /* Opcodes in TB are PC-relative */
#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */
#define CF_CLUSTER_SHIFT 24

Expand Down Expand Up @@ -613,16 +613,6 @@ struct TranslationBlock {
uintptr_t jmp_dest[2];
};

/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
static inline target_ulong tb_pc(const TranslationBlock *tb)
{
#if TARGET_TB_PCREL
qemu_build_not_reached();
#else
return tb->pc;
#endif
}

/* Hide the qatomic_read to make code a little easier on the eyes */
static inline uint32_t tb_cflags(const TranslationBlock *tb)
{
Expand Down
12 changes: 2 additions & 10 deletions include/exec/gen-icount.h
View file
Expand Up @@ -9,22 +9,14 @@ static TCGOp *icount_start_insn;

static inline void gen_io_start(void)
{
TCGv_i32 tmp = tcg_const_i32(1);
tcg_gen_st_i32(tmp, cpu_env,
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
offsetof(ArchCPU, parent_obj.can_do_io) -
offsetof(ArchCPU, env));
tcg_temp_free_i32(tmp);
}

static inline void gen_tb_start(const TranslationBlock *tb)
{
TCGv_i32 count;

if (tb_cflags(tb) & CF_USE_ICOUNT) {
count = tcg_temp_local_new_i32();
} else {
count = tcg_temp_new_i32();
}
TCGv_i32 count = tcg_temp_new_i32();

tcg_gen_ld_i32(count, cpu_env,
offsetof(ArchCPU, neg.icount_decr.u32) -
Expand Down
2 changes: 2 additions & 0 deletions include/exec/helper-head.h
View file
Expand Up @@ -18,6 +18,8 @@
#ifndef EXEC_HELPER_HEAD_H
#define EXEC_HELPER_HEAD_H

#include "fpu/softfloat-types.h"

#define HELPER(name) glue(helper_, name)

/* Some types that make sense in C, but not for TCG. */
Expand Down
4 changes: 2 additions & 2 deletions include/exec/translator.h
View file
Expand Up @@ -37,7 +37,7 @@
* This function must be provided by the target, which should create
* the target-specific DisasContext, and then invoke translator_loop.
*/
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc);

/**
Expand Down Expand Up @@ -146,7 +146,7 @@ typedef struct TranslatorOps {
* - When single-stepping is enabled (system-wide or on the current vCPU).
* - When too many instructions have been translated.
*/
void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc,
const TranslatorOps *ops, DisasContextBase *db);

Expand Down
7 changes: 5 additions & 2 deletions include/tcg/tcg-op.h
View file
Expand Up @@ -828,14 +828,12 @@ static inline void tcg_gen_plugin_cb_end(void)
#if TARGET_LONG_BITS == 32
#define tcg_temp_new() tcg_temp_new_i32()
#define tcg_global_mem_new tcg_global_mem_new_i32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
#define tcg_temp_free tcg_temp_free_i32
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
#else
#define tcg_temp_new() tcg_temp_new_i64()
#define tcg_global_mem_new tcg_global_mem_new_i64
#define tcg_temp_local_new() tcg_temp_local_new_i64()
#define tcg_temp_free tcg_temp_free_i64
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
Expand Down Expand Up @@ -1285,6 +1283,11 @@ static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s)
glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s);
}

static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s)
{
glue(tcg_gen_movi_,PTR)((NAT)d, s);
}

static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
intptr_t b, TCGLabel *label)
{
Expand Down
58 changes: 30 additions & 28 deletions include/tcg/tcg.h
View file
Expand Up @@ -431,13 +431,15 @@ typedef enum TCGTempVal {
} TCGTempVal;

typedef enum TCGTempKind {
/* Temp is dead at the end of all basic blocks. */
TEMP_NORMAL,
/* Temp is live across conditional branch, but dead otherwise. */
/*
* Temp is dead at the end of the extended basic block (EBB),
* the single-entry multiple-exit region that falls through
* conditional branches.
*/
TEMP_EBB,
/* Temp is saved across basic blocks but dead at the end of TBs. */
TEMP_LOCAL,
/* Temp is saved across both basic blocks and translation blocks. */
/* Temp is live across the entire translation block, but dead at end. */
TEMP_TB,
/* Temp is live across the entire translation block, and between them. */
TEMP_GLOBAL,
/* Temp is in a fixed register. */
TEMP_FIXED,
Expand Down Expand Up @@ -610,7 +612,7 @@ struct TCGContext {
#endif

GHashTable *const_table[TCG_TYPE_COUNT];
TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
TCGTempSet free_temps[TCG_TYPE_COUNT];
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */

QTAILQ_HEAD(, TCGOp) ops, free_ops;
Expand Down Expand Up @@ -853,7 +855,7 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);

TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
intptr_t, const char *);
TCGTemp *tcg_temp_new_internal(TCGType, bool);
TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind);
void tcg_temp_free_internal(TCGTemp *);
TCGv_vec tcg_temp_new_vec(TCGType type);
TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
Expand Down Expand Up @@ -890,15 +892,16 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_i32(t);
}

static inline TCGv_i32 tcg_temp_new_i32(void)
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i32 tcg_temp_ebb_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB);
return temp_tcgv_i32(t);
}

static inline TCGv_i32 tcg_temp_local_new_i32(void)
static inline TCGv_i32 tcg_temp_new_i32(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB);
return temp_tcgv_i32(t);
}

Expand All @@ -909,27 +912,29 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_i64(t);
}

static inline TCGv_i64 tcg_temp_new_i64(void)
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i64 tcg_temp_ebb_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB);
return temp_tcgv_i64(t);
}

static inline TCGv_i64 tcg_temp_local_new_i64(void)
static inline TCGv_i64 tcg_temp_new_i64(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB);
return temp_tcgv_i64(t);
}

static inline TCGv_i128 tcg_temp_new_i128(void)
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_i128 tcg_temp_ebb_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, false);
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB);
return temp_tcgv_i128(t);
}

static inline TCGv_i128 tcg_temp_local_new_i128(void)
static inline TCGv_i128 tcg_temp_new_i128(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, true);
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB);
return temp_tcgv_i128(t);
}

Expand All @@ -940,15 +945,16 @@ static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
return temp_tcgv_ptr(t);
}

static inline TCGv_ptr tcg_temp_new_ptr(void)
/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */
static inline TCGv_ptr tcg_temp_ebb_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB);
return temp_tcgv_ptr(t);
}

static inline TCGv_ptr tcg_temp_local_new_ptr(void)
static inline TCGv_ptr tcg_temp_new_ptr(void)
{
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB);
return temp_tcgv_ptr(t);
}

Expand Down Expand Up @@ -1054,8 +1060,6 @@ void tcg_optimize(TCGContext *s);
/* Allocate a new temporary and initialize it with a constant. */
TCGv_i32 tcg_const_i32(int32_t val);
TCGv_i64 tcg_const_i64(int64_t val);
TCGv_i32 tcg_const_local_i32(int32_t val);
TCGv_i64 tcg_const_local_i64(int64_t val);
TCGv_vec tcg_const_zeros_vec(TCGType);
TCGv_vec tcg_const_ones_vec(TCGType);
TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
Expand Down Expand Up @@ -1083,11 +1087,9 @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);

#if UINTPTR_MAX == UINT32_MAX
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)))
#else
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)))
#endif

Expand Down
2 changes: 1 addition & 1 deletion semihosting/uaccess.c
View file
Expand Up @@ -37,7 +37,7 @@ ssize_t softmmu_strlen_user(CPUArchState *env, target_ulong addr)
/* Find the number of bytes remaining in the page. */
left_in_page = TARGET_PAGE_SIZE - (addr & ~TARGET_PAGE_MASK);

flags = probe_access_flags(env, addr, MMU_DATA_LOAD,
flags = probe_access_flags(env, addr, 0, MMU_DATA_LOAD,
mmu_idx, true, &h, 0);
if (flags & TLB_INVALID_MASK) {
return -1;
Expand Down
2 changes: 1 addition & 1 deletion softmmu/physmem.c
View file
Expand Up @@ -2637,7 +2637,7 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
} else {
/* RAM case */
ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
memcpy(ram_ptr, buf, l);
memmove(ram_ptr, buf, l);
invalidate_and_set_dirty(mr, addr1, l);
}

Expand Down
2 changes: 1 addition & 1 deletion target/alpha/translate.c
View file
Expand Up @@ -3043,7 +3043,7 @@ static const TranslatorOps alpha_tr_ops = {
.disas_log = alpha_tr_disas_log,
};

void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
Expand Down
2 changes: 0 additions & 2 deletions target/arm/cpu-param.h
View file
Expand Up @@ -31,8 +31,6 @@
# define TARGET_PAGE_BITS_VARY
# define TARGET_PAGE_BITS_MIN 10

# define TARGET_TB_PCREL 1

/*
* Cache the attrs and shareability fields from the page table entry.
*
Expand Down
17 changes: 11 additions & 6 deletions target/arm/cpu.c
View file
Expand Up @@ -78,17 +78,17 @@ static vaddr arm_cpu_get_pc(CPUState *cs)
void arm_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
/* The program counter is always up to date with TARGET_TB_PCREL. */
if (!TARGET_TB_PCREL) {
/* The program counter is always up to date with CF_PCREL. */
if (!(tb_cflags(tb) & CF_PCREL)) {
CPUARMState *env = cs->env_ptr;
/*
* It's OK to look at env for the current mode here, because it's
* never possible for an AArch64 TB to chain to an AArch32 TB.
*/
if (is_a64(env)) {
env->pc = tb_pc(tb);
env->pc = tb->pc;
} else {
env->regs[15] = tb_pc(tb);
env->regs[15] = tb->pc;
}
}
}
Expand All @@ -100,15 +100,15 @@ void arm_restore_state_to_opc(CPUState *cs,
CPUARMState *env = cs->env_ptr;

if (is_a64(env)) {
if (TARGET_TB_PCREL) {
if (tb_cflags(tb) & CF_PCREL) {
env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
} else {
env->pc = data[0];
}
env->condexec_bits = 0;
env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
} else {
if (TARGET_TB_PCREL) {
if (tb_cflags(tb) & CF_PCREL) {
env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
} else {
env->regs[15] = data[0];
Expand Down Expand Up @@ -1557,6 +1557,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
Error *local_err = NULL;
bool no_aa32 = false;

/* Use pc-relative instructions in system-mode */
#ifndef CONFIG_USER_ONLY
cs->tcg_cflags |= CF_PCREL;
#endif

/* If we needed to query the host kernel for the CPU features
* then it's possible that might have failed in the initfn, but
* this is the first point where we can report it.
Expand Down
4 changes: 2 additions & 2 deletions target/arm/ptw.c
View file
Expand Up @@ -259,7 +259,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
int flags;

env->tlb_fi = fi;
flags = probe_access_full(env, addr, MMU_DATA_LOAD,
flags = probe_access_full(env, addr, 0, MMU_DATA_LOAD,
arm_to_core_mmu_idx(s2_mmu_idx),
true, &ptw->out_host, &full, 0);
env->tlb_fi = NULL;
Expand Down Expand Up @@ -411,7 +411,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
void *discard;

env->tlb_fi = fi;
flags = probe_access_flags(env, ptw->out_virt, MMU_DATA_STORE,
flags = probe_access_flags(env, ptw->out_virt, 0, MMU_DATA_STORE,
arm_to_core_mmu_idx(ptw->in_ptw_idx),
true, &discard, 0);
env->tlb_fi = NULL;
Expand Down
4 changes: 2 additions & 2 deletions target/arm/tcg/mte_helper.c
View file
Expand Up @@ -118,7 +118,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
* valid. Indicate to probe_access_flags no-fault, then assert that
* we received a valid page.
*/
flags = probe_access_full(env, ptr, ptr_access, ptr_mmu_idx,
flags = probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx,
ra == 0, &host, &full, ra);
assert(!(flags & TLB_INVALID_MASK));

Expand Down Expand Up @@ -154,7 +154,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
*/
in_page = -(ptr | TARGET_PAGE_MASK);
if (unlikely(ptr_size > in_page)) {
flags |= probe_access_full(env, ptr + in_page, ptr_access,
flags |= probe_access_full(env, ptr + in_page, 0, ptr_access,
ptr_mmu_idx, ra == 0, &host, &full, ra);
assert(!(flags & TLB_INVALID_MASK));
}
Expand Down
4 changes: 2 additions & 2 deletions target/arm/tcg/sve_helper.c
View file
Expand Up @@ -5352,11 +5352,11 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
addr = useronly_clean_ptr(addr);

#ifdef CONFIG_USER_ONLY
flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
flags = probe_access_flags(env, addr, 0, access_type, mmu_idx, nofault,
&info->host, retaddr);
#else
CPUTLBEntryFull *full;
flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
flags = probe_access_full(env, addr, 0, access_type, mmu_idx, nofault,
&info->host, &full, retaddr);
#endif
info->flags = flags;
Expand Down
16 changes: 5 additions & 11 deletions target/arm/tcg/translate-a64.c
View file
Expand Up @@ -143,7 +143,7 @@ static void reset_btype(DisasContext *s)
static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
{
assert(s->pc_save != -1);
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_i64(dest, cpu_pc, (s->pc_curr - s->pc_save) + diff);
} else {
tcg_gen_movi_i64(dest, s->pc_curr + diff);
Expand Down Expand Up @@ -393,7 +393,7 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
* update to pc to the unlinked path. A long chain of links
* can thus avoid many updates to the PC.
*/
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_a64_update_pc(s, diff);
tcg_gen_goto_tb(n);
} else {
Expand Down Expand Up @@ -436,12 +436,6 @@ TCGv_i64 new_tmp_a64(DisasContext *s)
return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
}

TCGv_i64 new_tmp_a64_local(DisasContext *s)
{
assert(s->tmp_a64_count < TMP_A64_MAX);
return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64();
}

TCGv_i64 new_tmp_a64_zero(DisasContext *s)
{
TCGv_i64 t = new_tmp_a64(s);
Expand Down Expand Up @@ -4297,7 +4291,7 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
if (page) {
/* ADRP (page based) */
offset <<= 12;
/* The page offset is ok for TARGET_TB_PCREL. */
/* The page offset is ok for CF_PCREL. */
offset -= s->pc_curr & 0xfff;
}

Expand Down Expand Up @@ -14651,7 +14645,7 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
* that the TLB entry must be present and valid, and thus this
* access will never raise an exception.
*/
flags = probe_access_full(env, addr, MMU_INST_FETCH, mmu_idx,
flags = probe_access_full(env, addr, 0, MMU_INST_FETCH, mmu_idx,
false, &host, &full, 0);
assert(!(flags & TLB_INVALID_MASK));

Expand Down Expand Up @@ -14809,7 +14803,7 @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
DisasContext *dc = container_of(dcbase, DisasContext, base);
target_ulong pc_arg = dc->base.pc_next;

if (TARGET_TB_PCREL) {
if (tb_cflags(dcbase->tb) & CF_PCREL) {
pc_arg &= ~TARGET_PAGE_MASK;
}
tcg_gen_insn_start(pc_arg, 0, 0);
Expand Down
1 change: 0 additions & 1 deletion target/arm/tcg/translate-a64.h
View file
Expand Up @@ -19,7 +19,6 @@
#define TARGET_ARM_TRANSLATE_A64_H

TCGv_i64 new_tmp_a64(DisasContext *s);
TCGv_i64 new_tmp_a64_local(DisasContext *s);
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
TCGv_i64 cpu_reg(DisasContext *s, int reg);
TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
Expand Down
38 changes: 3 additions & 35 deletions target/arm/tcg/translate-sve.c
View file
Expand Up @@ -2694,7 +2694,7 @@ static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before)
return true;
}

last = tcg_temp_local_new_i32();
last = tcg_temp_new_i32();
over = gen_new_label();

find_last_active(s, last, esz, a->pg);
Expand Down Expand Up @@ -4342,18 +4342,7 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
tcg_temp_free_i64(t0);
} else {
TCGLabel *loop = gen_new_label();
TCGv_ptr tp, i = tcg_const_local_ptr(0);

/* Copy the clean address into a local temp, live across the loop. */
t0 = clean_addr;
clean_addr = new_tmp_a64_local(s);
tcg_gen_mov_i64(clean_addr, t0);

if (base != cpu_env) {
TCGv_ptr b = tcg_temp_local_new_ptr();
tcg_gen_mov_ptr(b, base);
base = b;
}
TCGv_ptr tp, i = tcg_const_ptr(0);

gen_set_label(loop);

Expand All @@ -4370,11 +4359,6 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,

tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
tcg_temp_free_ptr(i);

if (base != cpu_env) {
tcg_temp_free_ptr(base);
assert(len_remain == 0);
}
}

/*
Expand Down Expand Up @@ -4443,18 +4427,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
tcg_temp_free_i64(t0);
} else {
TCGLabel *loop = gen_new_label();
TCGv_ptr tp, i = tcg_const_local_ptr(0);

/* Copy the clean address into a local temp, live across the loop. */
t0 = clean_addr;
clean_addr = new_tmp_a64_local(s);
tcg_gen_mov_i64(clean_addr, t0);

if (base != cpu_env) {
TCGv_ptr b = tcg_temp_local_new_ptr();
tcg_gen_mov_ptr(b, base);
base = b;
}
TCGv_ptr tp, i = tcg_const_ptr(0);

gen_set_label(loop);

Expand All @@ -4471,11 +4444,6 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,

tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop);
tcg_temp_free_ptr(i);

if (base != cpu_env) {
tcg_temp_free_ptr(base);
assert(len_remain == 0);
}
}

/* Predicate register stores can be any multiple of 2. */
Expand Down
14 changes: 7 additions & 7 deletions target/arm/tcg/translate.c
View file
Expand Up @@ -269,7 +269,7 @@ static target_long jmp_diff(DisasContext *s, target_long diff)
static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff)
{
assert(s->pc_save != -1);
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff);
} else {
tcg_gen_movi_i32(var, s->pc_curr + diff);
Expand Down Expand Up @@ -2620,7 +2620,7 @@ static void gen_goto_tb(DisasContext *s, int n, target_long diff)
* update to pc to the unlinked path. A long chain of links
* can thus avoid many updates to the PC.
*/
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_update_pc(s, diff);
tcg_gen_goto_tb(n);
} else {
Expand Down Expand Up @@ -7136,7 +7136,7 @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}

addr = tcg_temp_local_new_i32();
addr = tcg_temp_new_i32();
load_reg_var(s, addr, a->rn);
tcg_gen_addi_i32(addr, addr, a->imm);

Expand Down Expand Up @@ -7289,7 +7289,7 @@ static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq)
return true;
}

addr = tcg_temp_local_new_i32();
addr = tcg_temp_new_i32();
load_reg_var(s, addr, a->rn);
tcg_gen_addi_i32(addr, addr, a->imm);

Expand Down Expand Up @@ -8696,7 +8696,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
* Decrement by 1 << (4 - LTPSIZE). We need to use a TCG local
* so that decr stays live after the brcondi.
*/
TCGv_i32 decr = tcg_temp_local_new_i32();
TCGv_i32 decr = tcg_temp_new_i32();
TCGv_i32 ltpsize = load_cpu_field(v7m.ltpsize);
tcg_gen_sub_i32(decr, tcg_constant_i32(4), ltpsize);
tcg_gen_shl_i32(decr, tcg_constant_i32(1), decr);
Expand Down Expand Up @@ -9542,7 +9542,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
uint32_t condexec_bits;
target_ulong pc_arg = dc->base.pc_next;

if (TARGET_TB_PCREL) {
if (tb_cflags(dcbase->tb) & CF_PCREL) {
pc_arg &= ~TARGET_PAGE_MASK;
}
if (dc->eci) {
Expand Down Expand Up @@ -9970,7 +9970,7 @@ static const TranslatorOps thumb_translator_ops = {
};

/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc = { };
Expand Down
2 changes: 1 addition & 1 deletion target/arm/tcg/translate.h
View file
Expand Up @@ -23,7 +23,7 @@ typedef struct DisasContext {
/* The address of the current instruction being translated. */
target_ulong pc_curr;
/*
* For TARGET_TB_PCREL, the full value of cpu_pc is not known
* For CF_PCREL, the full value of cpu_pc is not known
* (although the page offset is known). For convenience, the
* translation loop uses the full virtual address that triggered
* the translation, from base.pc_start through pc_curr.
Expand Down
3 changes: 2 additions & 1 deletion target/avr/cpu.c
View file
Expand Up @@ -54,7 +54,8 @@ static void avr_cpu_synchronize_from_tb(CPUState *cs,
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;

env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->pc_w = tb->pc / 2; /* internally PC points to words */
}

static void avr_restore_state_to_opc(CPUState *cs,
Expand Down
2 changes: 1 addition & 1 deletion target/avr/translate.c
View file
Expand Up @@ -3049,7 +3049,7 @@ static const TranslatorOps avr_tr_ops = {
.disas_log = avr_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc = { };
Expand Down
8 changes: 4 additions & 4 deletions target/cris/translate.c
View file
Expand Up @@ -1621,7 +1621,7 @@ static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
LOG_DIS("bound.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
l0 = tcg_temp_local_new();
l0 = tcg_temp_new();
dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
tcg_temp_free(l0);
Expand Down Expand Up @@ -2404,8 +2404,8 @@ static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
dc->op1, dc->postinc ? "+]" : "]",
dc->op2);

l[0] = tcg_temp_local_new();
l[1] = tcg_temp_local_new();
l[0] = tcg_temp_new();
l[1] = tcg_temp_new();
insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
Expand Down Expand Up @@ -3286,7 +3286,7 @@ static const TranslatorOps cris_tr_ops = {
.disas_log = cris_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
Expand Down
10 changes: 5 additions & 5 deletions target/cris/translate_v10.c.inc
View file
Expand Up @@ -68,9 +68,9 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size, int mem_index)
{
TCGLabel *l1 = gen_new_label();
TCGv taddr = tcg_temp_local_new();
TCGv tval = tcg_temp_local_new();
TCGv t1 = tcg_temp_local_new();
TCGv taddr = tcg_temp_new();
TCGv tval = tcg_temp_new();
TCGv t1 = tcg_temp_new();
dc->postinc = 0;
cris_evaluate_flags(dc);

Expand Down Expand Up @@ -434,7 +434,7 @@ static void dec10_reg_bound(DisasContext *dc, int size)
{
TCGv t;

t = tcg_temp_local_new();
t = tcg_temp_new();
t_gen_zext(t, cpu_R[dc->src], size);
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4);
tcg_temp_free(t);
Expand Down Expand Up @@ -935,7 +935,7 @@ static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc,
int rd = dc->dst;
TCGv t;

t = tcg_temp_local_new();
t = tcg_temp_new();
insn_len += dec10_prep_move_m(env, dc, 0, size, t);
cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[rd], t, 4);
if (dc->dst == 15) {
Expand Down
8 changes: 4 additions & 4 deletions target/hexagon/README
View file
Expand Up @@ -81,7 +81,7 @@ tcg_funcs_generated.c.inc
Insn *insn,
Packet *pkt)
{
TCGv RdV = tcg_temp_local_new();
TCGv RdV = tcg_temp_new();
const int RdN = insn->regno[0];
TCGv RsV = hex_gpr[insn->regno[1]];
TCGv RtV = hex_gpr[insn->regno[2]];
Expand Down Expand Up @@ -146,16 +146,16 @@ istruction.
const int VdN = insn->regno[0];
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, VdN, 1, true);
TCGv_ptr VdV = tcg_temp_local_new_ptr();
TCGv_ptr VdV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VdV, cpu_env, VdV_off);
const int VuN = insn->regno[1];
const intptr_t VuV_off =
vreg_src_off(ctx, VuN);
TCGv_ptr VuV = tcg_temp_local_new_ptr();
TCGv_ptr VuV = tcg_temp_new_ptr();
const int VvN = insn->regno[2];
const intptr_t VvV_off =
vreg_src_off(ctx, VvN);
TCGv_ptr VvV = tcg_temp_local_new_ptr();
TCGv_ptr VvV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VuV, cpu_env, VuV_off);
tcg_gen_addi_ptr(VvV, cpu_env, VvV_off);
TCGv slot = tcg_constant_tl(insn->slot);
Expand Down
4 changes: 3 additions & 1 deletion target/hexagon/cpu.c
View file
Expand Up @@ -23,6 +23,7 @@
#include "qapi/error.h"
#include "hw/qdev-properties.h"
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"

static void hexagon_v67_cpu_init(Object *obj)
{
Expand Down Expand Up @@ -263,7 +264,8 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
{
HexagonCPU *cpu = HEXAGON_CPU(cs);
CPUHexagonState *env = &cpu->env;
env->gpr[HEX_REG_PC] = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->gpr[HEX_REG_PC] = tb->pc;
}

static bool hexagon_cpu_has_work(CPUState *cs)
Expand Down
4 changes: 2 additions & 2 deletions target/hexagon/gen_tcg.h
View file
Expand Up @@ -337,7 +337,7 @@
*/
#define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \
do { \
TCGv LSB = tcg_temp_local_new(); \
TCGv LSB = tcg_temp_new(); \
TCGLabel *label = gen_new_label(); \
tcg_gen_movi_tl(EA, 0); \
PRED; \
Expand Down Expand Up @@ -397,7 +397,7 @@
/* Predicated loads into a register pair */
#define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \
do { \
TCGv LSB = tcg_temp_local_new(); \
TCGv LSB = tcg_temp_new(); \
TCGLabel *label = gen_new_label(); \
tcg_gen_movi_tl(EA, 0); \
PRED; \
Expand Down
18 changes: 7 additions & 11 deletions target/hexagon/gen_tcg_funcs.py
View file
Expand Up @@ -26,18 +26,14 @@
## Helpers for gen_tcg_func
##
def gen_decl_ea_tcg(f, tag):
if ('A_CONDEXEC' in hex_common.attribdict[tag] or
'A_LOAD' in hex_common.attribdict[tag]):
f.write(" TCGv EA = tcg_temp_local_new();\n")
else:
f.write(" TCGv EA = tcg_temp_new();\n")
f.write(" TCGv EA = tcg_temp_new();\n")

def gen_free_ea_tcg(f):
f.write(" tcg_temp_free(EA);\n")

def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
if (regtype == "C"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
Expand All @@ -56,7 +52,7 @@ def genptr_decl_pair_writable(f, tag, regtype, regid, regno):

def genptr_decl_writable(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
f.write(" TCGv %s%sV = tcg_temp_local_new();\n" % \
f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
(regtype, regid))
if (regtype == "C"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
Expand All @@ -73,7 +69,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
if (regtype == "R"):
if (regid in {"ss", "tt"}):
f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
Expand All @@ -96,14 +92,14 @@ def genptr_decl(f, tag, regtype, regid, regno):
print("Bad register parse: ", regtype, regid)
elif (regtype == "C"):
if (regid == "ss"):
f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
elif (regid == "dd"):
genptr_decl_pair_writable(f, tag, regtype, regid, regno)
elif (regid == "s"):
f.write(" TCGv %s%sV = tcg_temp_local_new();\n" % \
f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
(regtype, regid))
f.write(" const int %s%sN = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regtype, regid, regno))
Expand Down Expand Up @@ -575,7 +571,7 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
## We produce:
## static void generate_A2_add(DisasContext *ctx)
## {
## TCGv RdV = tcg_temp_local_new();
## TCGv RdV = tcg_temp_new();
## const int RdN = insn->regno[0];
## TCGv RsV = hex_gpr[insn->regno[1]];
## TCGv RtV = hex_gpr[insn->regno[2]];
Expand Down
16 changes: 8 additions & 8 deletions target/hexagon/genptr.c
View file
Expand Up @@ -706,7 +706,7 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred,
TCGCond cond, int pc_off)
{
TCGv next_PC;
TCGv lsb = tcg_temp_local_new();
TCGv lsb = tcg_temp_new();
TCGLabel *skip = gen_new_label();
tcg_gen_andi_tl(lsb, pred, 1);
gen_write_new_pc_pcrel(ctx, pc_off, cond, lsb);
Expand All @@ -720,7 +720,7 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred,

static void gen_endloop0(DisasContext *ctx)
{
TCGv lpcfg = tcg_temp_local_new();
TCGv lpcfg = tcg_temp_new();

GET_USR_FIELD(USR_LPCFG, lpcfg);

Expand Down Expand Up @@ -852,7 +852,7 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
/* Bidirectional shift right with saturation */
static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
{
TCGv shift_amt = tcg_temp_local_new();
TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
TCGLabel *done = gen_new_label();

Expand All @@ -876,7 +876,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
/* Bidirectional shift left with saturation */
static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
{
TCGv shift_amt = tcg_temp_local_new();
TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
TCGLabel *done = gen_new_label();

Expand Down Expand Up @@ -918,7 +918,7 @@ static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num,
intptr_t dstoff;

if (is_predicated) {
TCGv cancelled = tcg_temp_local_new();
TCGv cancelled = tcg_temp_new();
label_end = gen_new_label();

/* Don't do anything if the slot was cancelled */
Expand Down Expand Up @@ -959,7 +959,7 @@ static void gen_log_qreg_write(intptr_t srcoff, int num, int vnew,
intptr_t dstoff;

if (is_predicated) {
TCGv cancelled = tcg_temp_local_new();
TCGv cancelled = tcg_temp_new();
label_end = gen_new_label();

/* Don't do anything if the slot was cancelled */
Expand Down Expand Up @@ -1164,10 +1164,10 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
/* Implements the fADDSAT64 macro in TCG */
void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 sum = tcg_temp_local_new_i64();
TCGv_i64 sum = tcg_temp_new_i64();
TCGv_i64 xor = tcg_temp_new_i64();
TCGv_i64 cond1 = tcg_temp_new_i64();
TCGv_i64 cond2 = tcg_temp_local_new_i64();
TCGv_i64 cond2 = tcg_temp_new_i64();
TCGv_i64 cond3 = tcg_temp_new_i64();
TCGv_i64 mask = tcg_constant_i64(0x8000000000000000ULL);
TCGv_i64 max_pos = tcg_constant_i64(0x7FFFFFFFFFFFFFFFLL);
Expand Down
4 changes: 2 additions & 2 deletions target/hexagon/idef-parser/README.rst
View file
Expand Up @@ -294,9 +294,9 @@ generators the previous declarations are mapped to

::

int var1; -> TCGv_i32 var1 = tcg_temp_local_new_i32();
int var1; -> TCGv_i32 var1 = tcg_temp_new_i32();

int var2 = 0; -> TCGv_i32 var1 = tcg_temp_local_new_i32();
int var2 = 0; -> TCGv_i32 var1 = tcg_temp_new_i32();
tcg_gen_movi_i32(j, ((int64_t) 0ULL));

which are later automatically freed at the end of the function they're declared
Expand Down
26 changes: 3 additions & 23 deletions target/hexagon/idef-parser/parser-helpers.c
View file
Expand Up @@ -307,26 +307,6 @@ HexValue gen_tmp(Context *c,
return rvalue;
}

HexValue gen_tmp_local(Context *c,
YYLTYPE *locp,
unsigned bit_width,
HexSignedness signedness)
{
HexValue rvalue;
assert(bit_width == 32 || bit_width == 64);
memset(&rvalue, 0, sizeof(HexValue));
rvalue.type = TEMP;
rvalue.bit_width = bit_width;
rvalue.signedness = signedness;
rvalue.is_dotnew = false;
rvalue.is_manual = false;
rvalue.tmp.index = c->inst.tmp_count;
OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count,
" = tcg_temp_local_new_i", &bit_width, "();\n");
c->inst.tmp_count++;
return rvalue;
}

HexValue gen_tmp_value(Context *c,
YYLTYPE *locp,
const char *value,
Expand Down Expand Up @@ -554,7 +534,7 @@ void gen_varid_allocate(Context *c,
new_var.signedness = signedness;

EMIT_HEAD(c, "TCGv_%s %s", bit_suffix, varid->var.name->str);
EMIT_HEAD(c, " = tcg_temp_local_new_%s();\n", bit_suffix);
EMIT_HEAD(c, " = tcg_temp_new_%s();\n", bit_suffix);
g_array_append_val(c->inst.allocated, new_var);
}

Expand Down Expand Up @@ -2161,8 +2141,8 @@ HexValue gen_rvalue_sat(Context *c, YYLTYPE *locp, HexSat *sat,
assert_signedness(c, locp, sat->signedness);

unsigned_str = (sat->signedness == UNSIGNED) ? "u" : "";
res = gen_tmp_local(c, locp, value->bit_width, sat->signedness);
ovfl = gen_tmp_local(c, locp, 32, sat->signedness);
res = gen_tmp(c, locp, value->bit_width, sat->signedness);
ovfl = gen_tmp(c, locp, 32, sat->signedness);
OUT(c, locp, "gen_sat", unsigned_str, "_", bit_suffix, "_ovfl(");
OUT(c, locp, &ovfl, ", ", &res, ", ", value, ", ", &width->imm.value,
");\n");
Expand Down
4 changes: 2 additions & 2 deletions target/hexagon/translate.c
View file
Expand Up @@ -539,7 +539,7 @@ void process_store(DisasContext *ctx, int slot_num)
tcg_temp_free(cancelled);
}
{
TCGv address = tcg_temp_local_new();
TCGv address = tcg_temp_new();
tcg_gen_mov_tl(address, hex_store_addr[slot_num]);

/*
Expand Down Expand Up @@ -962,7 +962,7 @@ static const TranslatorOps hexagon_tr_ops = {
.disas_log = hexagon_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
8 changes: 5 additions & 3 deletions target/hppa/cpu.c
View file
Expand Up @@ -26,7 +26,7 @@
#include "qemu/module.h"
#include "exec/exec-all.h"
#include "fpu/softfloat.h"

#include "tcg/tcg.h"

static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
{
Expand All @@ -48,8 +48,10 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
{
HPPACPU *cpu = HPPA_CPU(cs);

tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));

#ifdef CONFIG_USER_ONLY
cpu->env.iaoq_f = tb_pc(tb);
cpu->env.iaoq_f = tb->pc;
cpu->env.iaoq_b = tb->cs_base;
#else
/* Recover the IAOQ values from the GVA + PRIV. */
Expand All @@ -59,7 +61,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
int32_t diff = cs_base;

cpu->env.iasq_f = iasq_f;
cpu->env.iaoq_f = (tb_pc(tb) & ~iasq_f) + priv;
cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
if (diff) {
cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
}
Expand Down
5 changes: 1 addition & 4 deletions target/hppa/translate.c
View file
Expand Up @@ -35,7 +35,6 @@
#undef TCGv
#undef tcg_temp_new
#undef tcg_global_mem_new
#undef tcg_temp_local_new
#undef tcg_temp_free

#if TARGET_LONG_BITS == 64
Expand All @@ -59,7 +58,6 @@

#define tcg_temp_new tcg_temp_new_i64
#define tcg_global_mem_new tcg_global_mem_new_i64
#define tcg_temp_local_new tcg_temp_local_new_i64
#define tcg_temp_free tcg_temp_free_i64

#define tcg_gen_movi_reg tcg_gen_movi_i64
Expand Down Expand Up @@ -155,7 +153,6 @@
#define TCGv_reg TCGv_i32
#define tcg_temp_new tcg_temp_new_i32
#define tcg_global_mem_new tcg_global_mem_new_i32
#define tcg_temp_local_new tcg_temp_local_new_i32
#define tcg_temp_free tcg_temp_free_i32

#define tcg_gen_movi_reg tcg_gen_movi_i32
Expand Down Expand Up @@ -4359,7 +4356,7 @@ static const TranslatorOps hppa_tr_ops = {
.disas_log = hppa_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
4 changes: 0 additions & 4 deletions target/i386/cpu-param.h
View file
Expand Up @@ -25,8 +25,4 @@
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 5

#ifndef CONFIG_USER_ONLY
# define TARGET_TB_PCREL 1
#endif

#endif
5 changes: 5 additions & 0 deletions target/i386/cpu.c
View file
Expand Up @@ -6534,6 +6534,11 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
static bool ht_warned;
unsigned requested_lbr_fmt;

/* Use pc-relative instructions in system-mode */
#ifndef CONFIG_USER_ONLY
cs->tcg_cflags |= CF_PCREL;
#endif

if (cpu->apic_id == UNASSIGNED_APIC_ID) {
error_setg(errp, "apic-id property was not initialized properly");
return;
Expand Down
2 changes: 1 addition & 1 deletion target/i386/helper.c
View file
Expand Up @@ -520,7 +520,7 @@ static inline target_ulong get_memio_eip(CPUX86State *env)
}

/* Per x86_restore_state_to_opc. */
if (TARGET_TB_PCREL) {
if (cs->tcg_cflags & CF_PCREL) {
return (env->eip & TARGET_PAGE_MASK) | data[0];
} else {
return data[0] - env->segs[R_CS].base;
Expand Down
4 changes: 2 additions & 2 deletions target/i386/tcg/sysemu/excp_helper.c
View file
Expand Up @@ -64,7 +64,7 @@ static bool ptw_translate(PTETranslate *inout, hwaddr addr)
int flags;

inout->gaddr = addr;
flags = probe_access_full(inout->env, addr, MMU_DATA_STORE,
flags = probe_access_full(inout->env, addr, 0, MMU_DATA_STORE,
inout->ptw_idx, true, &inout->haddr, &full, 0);

if (unlikely(flags & TLB_INVALID_MASK)) {
Expand Down Expand Up @@ -428,7 +428,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
CPUTLBEntryFull *full;
int flags, nested_page_size;

flags = probe_access_full(env, paddr, access_type,
flags = probe_access_full(env, paddr, 0, access_type,
MMU_NESTED_IDX, true,
&pte_trans.haddr, &full, 0);
if (unlikely(flags & TLB_INVALID_MASK)) {
Expand Down
8 changes: 4 additions & 4 deletions target/i386/tcg/tcg-cpu.c
View file
Expand Up @@ -49,10 +49,10 @@ static void x86_cpu_exec_exit(CPUState *cs)
static void x86_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
/* The instruction pointer is always up to date with TARGET_TB_PCREL. */
if (!TARGET_TB_PCREL) {
/* The instruction pointer is always up to date with CF_PCREL. */
if (!(tb_cflags(tb) & CF_PCREL)) {
CPUX86State *env = cs->env_ptr;
env->eip = tb_pc(tb) - tb->cs_base;
env->eip = tb->pc - tb->cs_base;
}
}

Expand All @@ -64,7 +64,7 @@ static void x86_restore_state_to_opc(CPUState *cs,
CPUX86State *env = &cpu->env;
int cc_op = data[1];

if (TARGET_TB_PCREL) {
if (tb_cflags(tb) & CF_PCREL) {
env->eip = (env->eip & TARGET_PAGE_MASK) | data[0];
} else {
env->eip = data[0] - tb->cs_base;
Expand Down
55 changes: 23 additions & 32 deletions target/i386/tcg/translate.c
View file
Expand Up @@ -545,7 +545,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
static void gen_update_eip_cur(DisasContext *s)
{
assert(s->pc_save != -1);
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_tl(cpu_eip, cpu_eip, s->base.pc_next - s->pc_save);
} else {
tcg_gen_movi_tl(cpu_eip, s->base.pc_next - s->cs_base);
Expand All @@ -556,7 +556,7 @@ static void gen_update_eip_cur(DisasContext *s)
static void gen_update_eip_next(DisasContext *s)
{
assert(s->pc_save != -1);
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_tl(cpu_eip, cpu_eip, s->pc - s->pc_save);
} else {
tcg_gen_movi_tl(cpu_eip, s->pc - s->cs_base);
Expand Down Expand Up @@ -588,7 +588,7 @@ static TCGv_i32 eip_next_i32(DisasContext *s)
if (CODE64(s)) {
return tcg_constant_i32(-1);
}
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
TCGv_i32 ret = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(ret, cpu_eip);
tcg_gen_addi_i32(ret, ret, s->pc - s->pc_save);
Expand All @@ -601,7 +601,7 @@ static TCGv_i32 eip_next_i32(DisasContext *s)
static TCGv eip_next_tl(DisasContext *s)
{
assert(s->pc_save != -1);
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
TCGv ret = tcg_temp_new();
tcg_gen_addi_tl(ret, cpu_eip, s->pc - s->pc_save);
return ret;
Expand All @@ -613,7 +613,7 @@ static TCGv eip_next_tl(DisasContext *s)
static TCGv eip_cur_tl(DisasContext *s)
{
assert(s->pc_save != -1);
if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
TCGv ret = tcg_temp_new();
tcg_gen_addi_tl(ret, cpu_eip, s->base.pc_next - s->pc_save);
return ret;
Expand Down Expand Up @@ -1830,7 +1830,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);

/* The CC_OP value is no longer predictable. */
/* The CC_OP value is no longer predictable. */
set_cc_op(s, CC_OP_DYNAMIC);
}

Expand Down Expand Up @@ -1923,7 +1923,7 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1,
gen_op_ld_v(s, ot, s->T0, s->A0);
else
gen_op_mov_v_reg(s, ot, s->T0, op1);

if (is_right) {
switch (ot) {
case MO_8:
Expand Down Expand Up @@ -2319,7 +2319,7 @@ static TCGv gen_lea_modrm_1(DisasContext *s, AddressParts a, bool is_vsib)
ea = cpu_regs[a.base];
}
if (!ea) {
if (TARGET_TB_PCREL && a.base == -2) {
if (tb_cflags(s->base.tb) & CF_PCREL && a.base == -2) {
/* With cpu_eip ~= pc_save, the expression is pc-relative. */
tcg_gen_addi_tl(s->A0, cpu_eip, a.disp - s->pc_save);
} else {
Expand Down Expand Up @@ -2867,7 +2867,7 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num)
if (!CODE64(s)) {
if (ot == MO_16) {
mask = 0xffff;
if (TARGET_TB_PCREL && CODE32(s)) {
if (tb_cflags(s->base.tb) & CF_PCREL && CODE32(s)) {
use_goto_tb = false;
}
} else {
Expand All @@ -2879,7 +2879,7 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num)
gen_update_cc_op(s);
set_cc_op(s, CC_OP_DYNAMIC);

if (TARGET_TB_PCREL) {
if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_tl(cpu_eip, cpu_eip, new_pc - s->pc_save);
/*
* If we can prove the branch does not leave the page and we have
Expand All @@ -2896,13 +2896,13 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num)
translator_use_goto_tb(&s->base, new_eip + s->cs_base)) {
/* jump to same page: we can use a direct jump */
tcg_gen_goto_tb(tb_num);
if (!TARGET_TB_PCREL) {
if (!(tb_cflags(s->base.tb) & CF_PCREL)) {
tcg_gen_movi_tl(cpu_eip, new_eip);
}
tcg_gen_exit_tb(s->base.tb, tb_num);
s->base.is_jmp = DISAS_NORETURN;
} else {
if (!TARGET_TB_PCREL) {
if (!(tb_cflags(s->base.tb) & CF_PCREL)) {
tcg_gen_movi_tl(cpu_eip, new_eip);
}
if (s->jmp_opt) {
Expand Down Expand Up @@ -3426,13 +3426,10 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (mod == 3) {
goto illegal_op;
}
a0 = tcg_temp_local_new();
t0 = tcg_temp_local_new();
a0 = s->A0;
t0 = s->T0;
label1 = gen_new_label();

tcg_gen_mov_tl(a0, s->A0);
tcg_gen_mov_tl(t0, s->T0);

gen_set_label(label1);
t1 = tcg_temp_new();
t2 = tcg_temp_new();
Expand All @@ -3444,9 +3441,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_brcond_tl(TCG_COND_NE, t0, t2, label1);

tcg_temp_free(t2);
tcg_temp_free(a0);
tcg_gen_neg_tl(s->T0, t0);
tcg_temp_free(t0);
} else {
tcg_gen_neg_tl(s->T0, s->T0);
if (mod != 3) {
Expand Down Expand Up @@ -6248,13 +6243,13 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
#endif
{
TCGLabel *label1;
TCGv t0, t1, t2, a0;
TCGv t0, t1, t2;

if (!PE(s) || VM86(s))
goto illegal_op;
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
t2 = tcg_temp_local_new();
t0 = tcg_temp_new();
t1 = tcg_temp_new();
t2 = tcg_temp_new();
ot = MO_16;
modrm = x86_ldub_code(env, s);
reg = (modrm >> 3) & 7;
Expand All @@ -6263,11 +6258,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (mod != 3) {
gen_lea_modrm(env, s, modrm);
gen_op_ld_v(s, ot, t0, s->A0);
a0 = tcg_temp_local_new();
tcg_gen_mov_tl(a0, s->A0);
} else {
gen_op_mov_v_reg(s, ot, t0, rm);
a0 = NULL;
}
gen_op_mov_v_reg(s, ot, t1, reg);
tcg_gen_andi_tl(s->tmp0, t0, 3);
Expand All @@ -6280,8 +6272,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_movi_tl(t2, CC_Z);
gen_set_label(label1);
if (mod != 3) {
gen_op_st_v(s, ot, t0, a0);
tcg_temp_free(a0);
gen_op_st_v(s, ot, t0, s->A0);
} else {
gen_op_mov_reg_v(s, ot, rm, t0);
}
Expand All @@ -6304,7 +6295,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
modrm = x86_ldub_code(env, s);
reg = ((modrm >> 3) & 7) | REX_R(s);
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
t0 = tcg_temp_local_new();
t0 = tcg_temp_new();
gen_update_cc_op(s);
if (b == 0x102) {
gen_helper_lar(t0, cpu_env, s->T0);
Expand Down Expand Up @@ -7052,7 +7043,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
dc->tmp2_i32 = tcg_temp_new_i32();
dc->tmp3_i32 = tcg_temp_new_i32();
dc->tmp4 = tcg_temp_new();
dc->cc_srcT = tcg_temp_local_new();
dc->cc_srcT = tcg_temp_new();
}

static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)
Expand All @@ -7065,7 +7056,7 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
target_ulong pc_arg = dc->base.pc_next;

dc->prev_insn_end = tcg_last_op();
if (TARGET_TB_PCREL) {
if (tb_cflags(dcbase->tb) & CF_PCREL) {
pc_arg -= dc->cs_base;
pc_arg &= ~TARGET_PAGE_MASK;
}
Expand Down Expand Up @@ -7158,7 +7149,7 @@ static const TranslatorOps i386_tr_ops = {
};

/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
Expand Down
6 changes: 4 additions & 2 deletions target/loongarch/cpu.c
View file
Expand Up @@ -18,6 +18,7 @@
#include "fpu/softfloat-helpers.h"
#include "cpu-csr.h"
#include "sysemu/reset.h"
#include "tcg/tcg.h"

const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
Expand Down Expand Up @@ -321,7 +322,8 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;

env->pc = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->pc = tb->pc;
}

static void loongarch_restore_state_to_opc(CPUState *cs,
Expand Down Expand Up @@ -599,7 +601,7 @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)

oc = object_class_by_name(cpu_model);
if (!oc) {
g_autofree char *typename
g_autofree char *typename
= g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model);
oc = object_class_by_name(typename);
if (!oc) {
Expand Down
2 changes: 1 addition & 1 deletion target/loongarch/translate.c
View file
Expand Up @@ -245,7 +245,7 @@ static const TranslatorOps loongarch_tr_ops = {
.disas_log = loongarch_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
2 changes: 1 addition & 1 deletion target/m68k/translate.c
View file
Expand Up @@ -6393,7 +6393,7 @@ static const TranslatorOps m68k_tr_ops = {
.disas_log = m68k_tr_disas_log,
};

void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
Expand Down
4 changes: 3 additions & 1 deletion target/microblaze/cpu.c
View file
Expand Up @@ -30,6 +30,7 @@
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"

static const struct {
const char *name;
Expand Down Expand Up @@ -97,7 +98,8 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs,
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);

cpu->env.pc = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
}

Expand Down
2 changes: 1 addition & 1 deletion target/microblaze/translate.c
View file
Expand Up @@ -1849,7 +1849,7 @@ static const TranslatorOps mb_tr_ops = {
.disas_log = mb_tr_disas_log,
};

void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
Expand Down
3 changes: 2 additions & 1 deletion target/mips/tcg/exception.c
View file
Expand Up @@ -82,7 +82,8 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;

env->active_tc.PC = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->active_tc.PC = tb->pc;
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
Expand Down
4 changes: 2 additions & 2 deletions target/mips/tcg/nanomips_translate.c.inc
View file
Expand Up @@ -1017,8 +1017,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
uint32_t reg1, uint32_t reg2, bool eva)
{
TCGv taddr = tcg_temp_local_new();
TCGv lladdr = tcg_temp_local_new();
TCGv taddr = tcg_temp_new();
TCGv lladdr = tcg_temp_new();
TCGv_i64 tval = tcg_temp_new_i64();
TCGv_i64 llval = tcg_temp_new_i64();
TCGv_i64 val = tcg_temp_new_i64();
Expand Down
2 changes: 1 addition & 1 deletion target/mips/tcg/sysemu/special_helper.c
View file
Expand Up @@ -94,7 +94,7 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
CPUMIPSState *env = &cpu->env;

if ((env->hflags & MIPS_HFLAG_BMASK) != 0
&& env->active_tc.PC != tb_pc(tb)) {
&& !(cs->tcg_cflags & CF_PCREL) && env->active_tc.PC != tb->pc) {
env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
env->hflags &= ~MIPS_HFLAG_BMASK;
return true;
Expand Down
59 changes: 15 additions & 44 deletions target/mips/tcg/translate.c
View file
Expand Up @@ -2400,7 +2400,7 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
switch (opc) {
case OPC_ADDI:
{
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGLabel *l1 = gen_new_label();
Expand Down Expand Up @@ -2434,7 +2434,7 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
#if defined(TARGET_MIPS64)
case OPC_DADDI:
{
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGLabel *l1 = gen_new_label();
Expand Down Expand Up @@ -2630,7 +2630,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
switch (opc) {
case OPC_ADD:
{
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGLabel *l1 = gen_new_label();
Expand Down Expand Up @@ -2666,7 +2666,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
break;
case OPC_SUB:
{
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGLabel *l1 = gen_new_label();
Expand Down Expand Up @@ -2707,7 +2707,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
#if defined(TARGET_MIPS64)
case OPC_DADD:
{
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGLabel *l1 = gen_new_label();
Expand Down Expand Up @@ -2741,7 +2741,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc,
break;
case OPC_DSUB:
{
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGLabel *l1 = gen_new_label();
Expand Down Expand Up @@ -3759,26 +3759,8 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
return;
}

switch (opc) {
case OPC_MULT_G_2E:
case OPC_MULT_G_2F:
case OPC_MULTU_G_2E:
case OPC_MULTU_G_2F:
#if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E:
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2E:
case OPC_DMULTU_G_2F:
#endif
t0 = tcg_temp_new();
t1 = tcg_temp_new();
break;
default:
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
break;
}

t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);

Expand Down Expand Up @@ -3955,21 +3937,10 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
TCGCond cond;

opc = MASK_LMMI(ctx->opcode);
switch (opc) {
case OPC_ADD_CP2:
case OPC_SUB_CP2:
case OPC_DADD_CP2:
case OPC_DSUB_CP2:
t0 = tcg_temp_local_new_i64();
t1 = tcg_temp_local_new_i64();
break;
default:
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
break;
}

check_cp1_enabled(ctx);

t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_load_fpr64(ctx, t0, rs);
gen_load_fpr64(ctx, t1, rt);

Expand Down Expand Up @@ -8650,7 +8621,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();

if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
Expand Down Expand Up @@ -8878,7 +8849,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
int u, int sel, int h)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();

gen_load_gpr(t0, rt);
if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
Expand Down Expand Up @@ -11409,7 +11380,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
case OPC_ALNV_PS:
check_ps(ctx);
{
TCGv t0 = tcg_temp_local_new();
TCGv t0 = tcg_temp_new();
TCGv_i32 fp = tcg_temp_new_i32();
TCGv_i32 fph = tcg_temp_new_i32();
TCGLabel *l1 = gen_new_label();
Expand Down Expand Up @@ -16159,7 +16130,7 @@ static const TranslatorOps mips_tr_ops = {
.disas_log = mips_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
2 changes: 1 addition & 1 deletion target/nios2/translate.c
View file
Expand Up @@ -1037,7 +1037,7 @@ static const TranslatorOps nios2_tr_ops = {
.disas_log = nios2_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
Expand Down
4 changes: 3 additions & 1 deletion target/openrisc/cpu.c
View file
Expand Up @@ -22,6 +22,7 @@
#include "qemu/qemu-print.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"

static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
Expand All @@ -43,7 +44,8 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);

cpu->env.pc = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
cpu->env.pc = tb->pc;
}

static void openrisc_restore_state_to_opc(CPUState *cs,
Expand Down
2 changes: 1 addition & 1 deletion target/openrisc/translate.c
View file
Expand Up @@ -1705,7 +1705,7 @@ static const TranslatorOps openrisc_tr_ops = {
.disas_log = openrisc_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
8 changes: 4 additions & 4 deletions target/ppc/translate.c
View file
Expand Up @@ -4415,7 +4415,7 @@ static void gen_bcond(DisasContext *ctx, int type)
TCGv target;

if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
target = tcg_temp_local_new();
target = tcg_temp_new();
if (type == BCOND_CTR) {
tcg_gen_mov_tl(target, cpu_ctr);
} else if (type == BCOND_TAR) {
Expand Down Expand Up @@ -5594,8 +5594,8 @@ static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
{
TCGv t0, t1;

t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
t0 = tcg_temp_new();
t1 = tcg_temp_new();

switch (opc3 & 0x0D) {
case 0x05:
Expand Down Expand Up @@ -7707,7 +7707,7 @@ static const TranslatorOps ppc_tr_ops = {
.disas_log = ppc_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
8 changes: 4 additions & 4 deletions target/ppc/translate/spe-impl.c.inc
View file
Expand Up @@ -168,7 +168,7 @@ static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32();
TCGv_i32 t0 = tcg_temp_new_i32();

/* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F);
Expand All @@ -185,7 +185,7 @@ static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32();
TCGv_i32 t0 = tcg_temp_new_i32();

/* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F);
Expand All @@ -202,7 +202,7 @@ static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32();
TCGv_i32 t0 = tcg_temp_new_i32();

/* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F);
Expand Down Expand Up @@ -378,7 +378,7 @@ static inline void gen_evsel(DisasContext *ctx)
TCGLabel *l2 = gen_new_label();
TCGLabel *l3 = gen_new_label();
TCGLabel *l4 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32();
TCGv_i32 t0 = tcg_temp_new_i32();

tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
Expand Down
4 changes: 2 additions & 2 deletions target/ppc/translate/vmx-impl.c.inc
View file
Expand Up @@ -1508,8 +1508,8 @@ static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a, bool sign)
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx);

vra = tcg_temp_local_new_i64();
vrb = tcg_temp_local_new_i64();
vra = tcg_temp_new_i64();
vrb = tcg_temp_new_i64();
gt = gen_new_label();
lt = gen_new_label();
done = gen_new_label();
Expand Down
7 changes: 5 additions & 2 deletions target/riscv/cpu.c
View file
Expand Up @@ -34,6 +34,7 @@
#include "fpu/softfloat-helpers.h"
#include "sysemu/kvm.h"
#include "kvm_riscv.h"
#include "tcg/tcg.h"

/* RISC-V CPU definitions */

Expand Down Expand Up @@ -533,10 +534,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
CPURISCVState *env = &cpu->env;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);

tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));

if (xl == MXL_RV32) {
env->pc = (int32_t)tb_pc(tb);
env->pc = (int32_t) tb->pc;
} else {
env->pc = tb_pc(tb);
env->pc = tb->pc;
}
}

Expand Down
2 changes: 1 addition & 1 deletion target/riscv/translate.c
View file
Expand Up @@ -1309,7 +1309,7 @@ static const TranslatorOps riscv_tr_ops = {
.disas_log = riscv_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
3 changes: 2 additions & 1 deletion target/rx/cpu.c
View file
Expand Up @@ -44,7 +44,8 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs,
{
RXCPU *cpu = RX_CPU(cs);

cpu->env.pc = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
cpu->env.pc = tb->pc;
}

static void rx_restore_state_to_opc(CPUState *cs,
Expand Down
2 changes: 1 addition & 1 deletion target/rx/translate.c
View file
Expand Up @@ -2363,7 +2363,7 @@ static const TranslatorOps rx_tr_ops = {
.disas_log = rx_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
Expand Down
2 changes: 1 addition & 1 deletion target/s390x/tcg/mem_helper.c
View file
Expand Up @@ -145,7 +145,7 @@ static inline int s390_probe_access(CPUArchState *env, target_ulong addr,
int mmu_idx, bool nonfault,
void **phost, uintptr_t ra)
{
int flags = probe_access_flags(env, addr, access_type, mmu_idx,
int flags = probe_access_flags(env, addr, 0, access_type, mmu_idx,
nonfault, phost, ra);

if (unlikely(flags & TLB_INVALID_MASK)) {
Expand Down
2 changes: 1 addition & 1 deletion target/s390x/tcg/translate.c
View file
Expand Up @@ -6619,7 +6619,7 @@ static const TranslatorOps s390x_tr_ops = {
.disas_log = s390x_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc;
Expand Down
6 changes: 4 additions & 2 deletions target/sh4/cpu.c
View file
Expand Up @@ -26,6 +26,7 @@
#include "migration/vmstate.h"
#include "exec/exec-all.h"
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"

static void superh_cpu_set_pc(CPUState *cs, vaddr value)
{
Expand All @@ -46,7 +47,8 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
{
SuperHCPU *cpu = SUPERH_CPU(cs);

cpu->env.pc = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
}

Expand All @@ -73,7 +75,7 @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
CPUSH4State *env = &cpu->env;

if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
&& env->pc != tb_pc(tb)) {
&& !(cs->tcg_cflags & CF_PCREL) && env->pc != tb->pc) {
env->pc -= 2;
env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
return true;
Expand Down
2 changes: 1 addition & 1 deletion target/sh4/translate.c
View file
Expand Up @@ -2374,7 +2374,7 @@ static const TranslatorOps sh4_tr_ops = {
.disas_log = sh4_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
4 changes: 3 additions & 1 deletion target/sparc/cpu.c
View file
Expand Up @@ -25,6 +25,7 @@
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
#include "qapi/visitor.h"
#include "tcg/tcg.h"

//#define DEBUG_FEATURES

Expand Down Expand Up @@ -707,7 +708,8 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs,
{
SPARCCPU *cpu = SPARC_CPU(cs);

cpu->env.pc = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
cpu->env.pc = tb->pc;
cpu->env.npc = tb->cs_base;
}

Expand Down
2 changes: 1 addition & 1 deletion target/sparc/translate.c
View file
Expand Up @@ -5904,7 +5904,7 @@ static const TranslatorOps sparc_tr_ops = {
.disas_log = sparc_tr_disas_log,
};

void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc = {};
Expand Down
3 changes: 2 additions & 1 deletion target/tricore/cpu.c
View file
Expand Up @@ -55,7 +55,8 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs,
TriCoreCPU *cpu = TRICORE_CPU(cs);
CPUTriCoreState *env = &cpu->env;

env->PC = tb_pc(tb);
tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
env->PC = tb->pc;
}

static void tricore_restore_state_to_opc(CPUState *cs,
Expand Down
2 changes: 1 addition & 1 deletion target/tricore/translate.c
View file
Expand Up @@ -8881,7 +8881,7 @@ static const TranslatorOps tricore_tr_ops = {
};


void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext ctx;
Expand Down
18 changes: 9 additions & 9 deletions target/xtensa/translate.c
View file
Expand Up @@ -307,7 +307,7 @@ static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
if (!dc->sar_m32_allocated) {
dc->sar_m32 = tcg_temp_local_new_i32();
dc->sar_m32 = tcg_temp_new_i32();
dc->sar_m32_allocated = true;
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
Expand Down Expand Up @@ -1074,10 +1074,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
if (i == 0 || arg_copy[i].resource != resource) {
resource = arg_copy[i].resource;
if (arg_copy[i].arg->num_bits <= 32) {
temp = tcg_temp_local_new_i32();
temp = tcg_temp_new_i32();
tcg_gen_mov_i32(temp, arg_copy[i].arg->in);
} else if (arg_copy[i].arg->num_bits <= 64) {
temp = tcg_temp_local_new_i64();
temp = tcg_temp_new_i64();
tcg_gen_mov_i64(temp, arg_copy[i].arg->in);
} else {
g_assert_not_reached();
Expand Down Expand Up @@ -1187,7 +1187,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
DisasContext *dc = container_of(dcbase, DisasContext, base);

if (dc->icount) {
dc->next_icount = tcg_temp_local_new_i32();
dc->next_icount = tcg_temp_new_i32();
}
}

Expand Down Expand Up @@ -1279,7 +1279,7 @@ static const TranslatorOps xtensa_translator_ops = {
.disas_log = xtensa_tr_disas_log,
};

void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
target_ulong pc, void *host_pc)
{
DisasContext dc = {};
Expand Down Expand Up @@ -2273,8 +2273,8 @@ static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr)
static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 tmp = tcg_temp_local_new_i32();
TCGv_i32 addr = tcg_temp_local_new_i32();
TCGv_i32 tmp = tcg_temp_new_i32();
TCGv_i32 addr = tcg_temp_new_i32();
MemOp mop;

tcg_gen_mov_i32(tmp, arg[0].in);
Expand Down Expand Up @@ -2303,8 +2303,8 @@ static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 prev = tcg_temp_new_i32();
TCGv_i32 addr = tcg_temp_local_new_i32();
TCGv_i32 res = tcg_temp_local_new_i32();
TCGv_i32 addr = tcg_temp_new_i32();
TCGv_i32 res = tcg_temp_new_i32();
TCGLabel *label = gen_new_label();
MemOp mop;

Expand Down
2 changes: 1 addition & 1 deletion tcg/optimize.c
View file
Expand Up @@ -190,7 +190,7 @@ static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
} else if (i->kind > ts->kind) {
if (i->kind == TEMP_GLOBAL) {
g = i;
} else if (i->kind == TEMP_LOCAL) {
} else if (i->kind == TEMP_TB) {
l = i;
}
}
Expand Down