168 changes: 73 additions & 95 deletions target/arm/tcg/translate-a64.c
View file

Large diffs are not rendered by default.

56 changes: 30 additions & 26 deletions target/arm/tcg/translate-mve.c
View file
Expand Up @@ -588,7 +588,7 @@ DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs)
DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu)

static bool do_vcvt_rmode(DisasContext *s, arg_1op *a,
enum arm_fprounding rmode, bool u)
ARMFPRounding rmode, bool u)
{
/*
* Handle VCVT fp to int with specified rounding mode.
Expand Down Expand Up @@ -1150,7 +1150,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
MVEGenLongDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
TCGv_i64 rda;
TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;

if (!dc_isar_feature(aa32_mve, s) ||
Expand All @@ -1177,21 +1177,22 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current rda value, not 0.
*/
rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
rda = tcg_temp_new_i64();
rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
rda = tcg_const_i64(0);
rda_i = tcg_constant_i64(0);
}

fn(rda, cpu_env, qn, qm, rda);
fn(rda_o, cpu_env, qn, qm, rda_i);

rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
tcg_gen_extrl_i64_i32(rdalo, rda_o);
tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
Expand Down Expand Up @@ -1258,7 +1259,7 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
TCGv_i32 rda;
TCGv_i32 rda_i, rda_o;

if (!dc_isar_feature(aa32_mve, s) ||
!mve_check_qreg_bank(s, a->qn) ||
Expand All @@ -1278,13 +1279,14 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
* beat must start with the current rda value, not 0.
*/
if (a->a || mve_skip_first_beat(s)) {
rda = load_reg(s, a->rda);
rda_o = rda_i = load_reg(s, a->rda);
} else {
rda = tcg_const_i32(0);
rda_i = tcg_constant_i32(0);
rda_o = tcg_temp_new_i32();
}

fn(rda, cpu_env, qn, qm, rda);
store_reg(s, a->rda, rda);
fn(rda_o, cpu_env, qn, qm, rda_i);
store_reg(s, a->rda, rda_o);

mve_update_eci(s);
return true;
Expand Down Expand Up @@ -1396,7 +1398,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
{ NULL, NULL }
};
TCGv_ptr qm;
TCGv_i32 rda;
TCGv_i32 rda_i, rda_o;

if (!dc_isar_feature(aa32_mve, s) ||
a->size == 3) {
Expand All @@ -1413,15 +1415,16 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
*/
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from Rda */
rda = load_reg(s, a->rda);
rda_o = rda_i = load_reg(s, a->rda);
} else {
/* Accumulate starting at zero */
rda = tcg_const_i32(0);
rda_i = tcg_constant_i32(0);
rda_o = tcg_temp_new_i32();
}

qm = mve_qreg_ptr(a->qm);
fns[a->size][a->u](rda, cpu_env, qm, rda);
store_reg(s, a->rda, rda);
fns[a->size][a->u](rda_o, cpu_env, qm, rda_i);
store_reg(s, a->rda, rda_o);

mve_update_eci(s);
return true;
Expand All @@ -1436,7 +1439,7 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* No need to check Qm's bank: it is only 3 bits in decode.
*/
TCGv_ptr qm;
TCGv_i64 rda;
TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;

if (!dc_isar_feature(aa32_mve, s)) {
Expand All @@ -1458,28 +1461,29 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current value of RdaHi:RdaLo, not zero.
*/
rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from RdaHi:RdaLo */
rda = tcg_temp_new_i64();
rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
/* Accumulate starting at zero */
rda = tcg_const_i64(0);
rda_i = tcg_constant_i64(0);
}

qm = mve_qreg_ptr(a->qm);
if (a->u) {
gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i);
} else {
gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i);
}

rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(rdalo, rda);
tcg_gen_extrh_i64_i32(rdahi, rda);
tcg_gen_extrl_i64_i32(rdalo, rda_o);
tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
Expand Down
28 changes: 14 additions & 14 deletions target/arm/tcg/translate-sve.c
View file
Expand Up @@ -4082,7 +4082,7 @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);

static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
int mode, gen_helper_gvec_3_ptr *fn)
ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
{
unsigned vsz;
TCGv_i32 tmode;
Expand All @@ -4096,30 +4096,28 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}

vsz = vec_full_reg_size(s);
tmode = tcg_const_i32(mode);
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);

gen_helper_set_rmode(tmode, tmode, status);
tmode = gen_set_rmode(mode, status);

tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
status, vsz, vsz, 0, fn);

gen_helper_set_rmode(tmode, tmode, status);
gen_restore_rmode(tmode, status);
return true;
}

TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a,
float_round_nearest_even, frint_fns[a->esz])
FPROUNDING_TIEEVEN, frint_fns[a->esz])
TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a,
float_round_up, frint_fns[a->esz])
FPROUNDING_POSINF, frint_fns[a->esz])
TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a,
float_round_down, frint_fns[a->esz])
FPROUNDING_NEGINF, frint_fns[a->esz])
TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a,
float_round_to_zero, frint_fns[a->esz])
FPROUNDING_ZERO, frint_fns[a->esz])
TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a,
float_round_ties_away, frint_fns[a->esz])
FPROUNDING_TIEAWAY, frint_fns[a->esz])

static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
NULL, gen_helper_sve_frecpx_h,
Expand Down Expand Up @@ -4208,8 +4206,9 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
TCGv_ptr tp, i = tcg_const_ptr(0);
TCGv_ptr tp, i = tcg_temp_new_ptr();

tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);

t0 = tcg_temp_new_i64();
Expand Down Expand Up @@ -4286,8 +4285,9 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
TCGv_ptr tp, i = tcg_const_ptr(0);
TCGv_ptr tp, i = tcg_temp_new_ptr();

tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);

t0 = tcg_temp_new_i64();
Expand Down Expand Up @@ -7145,9 +7145,9 @@ TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)

TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
float_round_to_odd, gen_helper_sve_fcvt_ds)
FPROUNDING_ODD, gen_helper_sve_fcvt_ds)
TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds)

static gen_helper_gvec_3_ptr * const flogb_fns[] = {
NULL, gen_helper_flogb_h,
Expand Down
26 changes: 10 additions & 16 deletions target/arm/tcg/translate-vfp.c
View file
Expand Up @@ -464,8 +464,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
fpst = fpstatus_ptr(FPST_FPCR);
}

tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(rounding, fpst);

if (sz == 3) {
TCGv_i64 tcg_op;
Expand All @@ -489,7 +488,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
vfp_store_reg32(tcg_res, rd);
}

gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
return true;
}

Expand Down Expand Up @@ -533,9 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}

tcg_shift = tcg_constant_i32(0);

tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(rounding, fpst);

if (sz == 3) {
TCGv_i64 tcg_double, tcg_res;
Expand Down Expand Up @@ -572,7 +569,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
vfp_store_reg32(tcg_res, rd);
}

gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
return true;
}

Expand Down Expand Up @@ -2783,10 +2780,9 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR_F16);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rinth(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
Expand All @@ -2808,10 +2804,9 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rints(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
Expand Down Expand Up @@ -2842,10 +2837,9 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
tcg_rmode = tcg_const_i32(float_round_to_zero);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rintd(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
}
Expand Down
13 changes: 5 additions & 8 deletions target/arm/tcg/translate.c
View file
Expand Up @@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)

static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
{
TCGv_i32 tmp;
int msb = a->msb, lsb = a->lsb;
TCGv_i32 t_in, t_rd;
int width;

if (!ENABLE_ARCH_6T2) {
Expand All @@ -7277,16 +7277,13 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
width = msb + 1 - lsb;
if (a->rn == 15) {
/* BFC */
tmp = tcg_const_i32(0);
t_in = tcg_constant_i32(0);
} else {
/* BFI */
tmp = load_reg(s, a->rn);
}
if (width != 32) {
TCGv_i32 tmp2 = load_reg(s, a->rd);
tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
t_in = load_reg(s, a->rn);
}
store_reg(s, a->rd, tmp);
t_rd = load_reg(s, a->rd);
tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
return true;
}

Expand Down
17 changes: 17 additions & 0 deletions target/arm/tcg/translate.h
View file
Expand Up @@ -616,6 +616,23 @@ static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
return ret;
}

/*
* Set and reset rounding mode around another operation.
*/
static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
{
TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
TCGv_i32 old = tcg_temp_new_i32();

gen_helper_set_rmode(old, new, fpst);
return old;
}

static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
{
gen_helper_set_rmode(old, old, fpst);
}

/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
Expand Down
35 changes: 8 additions & 27 deletions target/arm/vfp_helper.c
View file
Expand Up @@ -1104,33 +1104,14 @@ float64 HELPER(rintd)(float64 x, void *fp_status)
}

/* Convert ARM rounding mode to softfloat */
int arm_rmode_to_sf(int rmode)
{
switch (rmode) {
case FPROUNDING_TIEAWAY:
rmode = float_round_ties_away;
break;
case FPROUNDING_ODD:
/* FIXME: add support for TIEAWAY and ODD */
qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
rmode);
/* fall through for now */
case FPROUNDING_TIEEVEN:
default:
rmode = float_round_nearest_even;
break;
case FPROUNDING_POSINF:
rmode = float_round_up;
break;
case FPROUNDING_NEGINF:
rmode = float_round_down;
break;
case FPROUNDING_ZERO:
rmode = float_round_to_zero;
break;
}
return rmode;
}
const FloatRoundMode arm_rmode_to_sf_map[] = {
[FPROUNDING_TIEEVEN] = float_round_nearest_even,
[FPROUNDING_POSINF] = float_round_up,
[FPROUNDING_NEGINF] = float_round_down,
[FPROUNDING_ZERO] = float_round_to_zero,
[FPROUNDING_TIEAWAY] = float_round_ties_away,
[FPROUNDING_ODD] = float_round_to_odd,
};

/*
* Implement float64 to int32_t conversion without saturation;
Expand Down
1 change: 0 additions & 1 deletion target/avr/cpu-param.h
View file
Expand Up @@ -31,6 +31,5 @@
#define TARGET_PAGE_BITS 8
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
#define NB_MMU_MODES 2

#endif
48 changes: 25 additions & 23 deletions target/avr/translate.c
View file
Expand Up @@ -400,7 +400,7 @@ static bool trans_SUB(DisasContext *ctx, arg_SUB *a)
static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv Rr = tcg_const_i32(a->imm);
TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();

tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Imm */
Expand All @@ -425,7 +425,7 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);

tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
Expand Down Expand Up @@ -453,9 +453,9 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a)
static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv Rr = tcg_const_i32(a->imm);
TCGv Rr = tcg_constant_i32(a->imm);
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);

tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
Expand Down Expand Up @@ -637,7 +637,7 @@ static bool trans_COM(DisasContext *ctx, arg_COM *a)
static bool trans_NEG(DisasContext *ctx, arg_NEG *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv t0 = tcg_const_i32(0);
TCGv t0 = tcg_constant_i32(0);
TCGv R = tcg_temp_new_i32();

tcg_gen_sub_tl(R, t0, Rd); /* R = 0 - Rd */
Expand Down Expand Up @@ -930,19 +930,19 @@ static void gen_jmp_z(DisasContext *ctx)
static void gen_push_ret(DisasContext *ctx, int ret)
{
if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) {
TCGv t0 = tcg_const_i32((ret & 0x0000ff));
TCGv t0 = tcg_constant_i32(ret & 0x0000ff);

tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) {
TCGv t0 = tcg_const_i32((ret & 0x00ffff));
TCGv t0 = tcg_constant_i32(ret & 0x00ffff);

tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
} else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) {
TCGv lo = tcg_const_i32((ret & 0x0000ff));
TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
TCGv lo = tcg_constant_i32(ret & 0x0000ff);
TCGv hi = tcg_constant_i32((ret & 0xffff00) >> 8);

tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
Expand Down Expand Up @@ -1211,7 +1211,7 @@ static bool trans_CPC(DisasContext *ctx, arg_CPC *a)
TCGv Rd = cpu_r[a->rd];
TCGv Rr = cpu_r[a->rr];
TCGv R = tcg_temp_new_i32();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);

tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr - Cf */
tcg_gen_sub_tl(R, R, cpu_Cf);
Expand All @@ -1238,7 +1238,7 @@ static bool trans_CPI(DisasContext *ctx, arg_CPI *a)
{
TCGv Rd = cpu_r[a->rd];
int Imm = a->imm;
TCGv Rr = tcg_const_i32(Imm);
TCGv Rr = tcg_constant_i32(Imm);
TCGv R = tcg_temp_new_i32();

tcg_gen_sub_tl(R, Rd, Rr); /* R = Rd - Rr */
Expand Down Expand Up @@ -1288,12 +1288,13 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
*/
static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
{
TCGv temp = tcg_const_i32(a->reg);
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);

gen_helper_inb(temp, cpu_env, temp);
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = temp;
ctx->skip_var0 = data;

return true;
}
Expand All @@ -1305,12 +1306,13 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a)
*/
static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a)
{
TCGv temp = tcg_const_i32(a->reg);
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_constant_i32(a->reg);

gen_helper_inb(temp, cpu_env, temp);
tcg_gen_andi_tl(temp, temp, 1 << a->bit);
gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, 1 << a->bit);
ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = temp;
ctx->skip_var0 = data;

return true;
}
Expand Down Expand Up @@ -2122,7 +2124,7 @@ static bool trans_SPMX(DisasContext *ctx, arg_SPMX *a)
static bool trans_IN(DisasContext *ctx, arg_IN *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_const_i32(a->imm);
TCGv port = tcg_constant_i32(a->imm);

gen_helper_inb(Rd, cpu_env, port);
return true;
Expand All @@ -2135,7 +2137,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a)
static bool trans_OUT(DisasContext *ctx, arg_OUT *a)
{
TCGv Rd = cpu_r[a->rd];
TCGv port = tcg_const_i32(a->imm);
TCGv port = tcg_constant_i32(a->imm);

gen_helper_outb(cpu_env, port, Rd);
return true;
Expand Down Expand Up @@ -2403,7 +2405,7 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *a)
static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
{
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_const_i32(a->reg);
TCGv port = tcg_constant_i32(a->reg);

gen_helper_inb(data, cpu_env, port);
tcg_gen_ori_tl(data, data, 1 << a->bit);
Expand All @@ -2418,7 +2420,7 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a)
static bool trans_CBI(DisasContext *ctx, arg_CBI *a)
{
TCGv data = tcg_temp_new_i32();
TCGv port = tcg_const_i32(a->reg);
TCGv port = tcg_constant_i32(a->reg);

gen_helper_inb(data, cpu_env, port);
tcg_gen_andi_tl(data, data, ~(1 << a->bit));
Expand Down
1 change: 0 additions & 1 deletion target/cris/cpu-param.h
View file
Expand Up @@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 2

#endif
46 changes: 21 additions & 25 deletions target/cris/translate.c
View file
Expand Up @@ -175,10 +175,7 @@ static const int preg_sizes[] = {
#define t_gen_mov_env_TN(member, tn) \
tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
#define t_gen_movi_env_TN(member, c) \
do { \
TCGv tc = tcg_const_tl(c); \
t_gen_mov_env_TN(member, tc); \
} while (0)
t_gen_mov_env_TN(member, tcg_constant_tl(c))

static inline void t_gen_mov_TN_preg(TCGv tn, int r)
{
Expand Down Expand Up @@ -268,16 +265,15 @@ static void cris_lock_irq(DisasContext *dc)

static inline void t_gen_raise_exception(uint32_t index)
{
TCGv_i32 tmp = tcg_const_i32(index);
gen_helper_raise_exception(cpu_env, tmp);
gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
}

static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
{
TCGv t0, t_31;

t0 = tcg_temp_new();
t_31 = tcg_const_tl(31);
t_31 = tcg_constant_tl(31);
tcg_gen_shl_tl(d, a, b);

tcg_gen_sub_tl(t0, t_31, b);
Expand Down Expand Up @@ -1250,7 +1246,7 @@ static int dec_addq(CPUCRISState *env, DisasContext *dc)

cris_cc_mask(dc, CC_MASK_NZVC);

c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_alu(dc, CC_OP_ADD,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
Expand All @@ -1274,7 +1270,7 @@ static int dec_subq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);

cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_alu(dc, CC_OP_SUB,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
Expand All @@ -1289,7 +1285,7 @@ static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);

c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
Expand All @@ -1304,7 +1300,7 @@ static int dec_andq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);

c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_AND,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
Expand All @@ -1318,7 +1314,7 @@ static int dec_orq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);

c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_OR,
cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
return 2;
Expand All @@ -1330,7 +1326,7 @@ static int dec_btstq(CPUCRISState *env, DisasContext *dc)
LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);

cris_cc_mask(dc, CC_MASK_NZ);
c = tcg_const_tl(dc->op1);
c = tcg_constant_tl(dc->op1);
cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
c, cpu_PR[PR_CCS]);
Expand Down Expand Up @@ -1945,8 +1941,8 @@ static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
{
TCGv c2, c1;
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
c1 = tcg_const_tl(dc->op1);
c2 = tcg_const_tl(dc->op2);
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_sreg_reg(cpu_env, c2, c1);
return 2;
Expand All @@ -1955,8 +1951,8 @@ static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
{
TCGv c2, c1;
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
c1 = tcg_const_tl(dc->op1);
c2 = tcg_const_tl(dc->op2);
c1 = tcg_constant_tl(dc->op1);
c2 = tcg_constant_tl(dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_reg_sreg(cpu_env, c1, c2);
return 2;
Expand Down Expand Up @@ -2237,7 +2233,7 @@ static int dec_test_m(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZ);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);

c = tcg_const_tl(0);
c = tcg_constant_tl(0);
cris_alu(dc, CC_OP_CMP,
cpu_R[dc->op2], t[1], c, memsize_zz(dc));
do_postinc(dc, memsize);
Expand Down Expand Up @@ -2582,7 +2578,7 @@ static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
if (dc->op2 > 15) {
abort();
}
c = tcg_const_tl(dc->pc + 4);
c = tcg_constant_tl(dc->pc + 4);
t_gen_mov_preg_TN(dc, dc->op2, c);

cris_prepare_jmp(dc, JMP_INDIRECT);
Expand All @@ -2598,7 +2594,7 @@ static int dec_jas_im(CPUCRISState *env, DisasContext *dc)

LOG_DIS("jas 0x%x\n", imm);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8);
c = tcg_constant_tl(dc->pc + 8);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);

Expand All @@ -2616,7 +2612,7 @@ static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)

LOG_DIS("jasc 0x%x\n", imm);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8 + 4);
c = tcg_constant_tl(dc->pc + 8 + 4);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);

Expand All @@ -2632,7 +2628,7 @@ static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
c = tcg_const_tl(dc->pc + 4 + 4);
c = tcg_constant_tl(dc->pc + 4 + 4);
t_gen_mov_preg_TN(dc, dc->op2, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
return 2;
Expand Down Expand Up @@ -2664,7 +2660,7 @@ static int dec_bas_im(CPUCRISState *env, DisasContext *dc)

LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 8);
c = tcg_constant_tl(dc->pc + 8);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);

Expand All @@ -2681,7 +2677,7 @@ static int dec_basc_im(CPUCRISState *env, DisasContext *dc)

LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
c = tcg_const_tl(dc->pc + 12);
c = tcg_constant_tl(dc->pc + 12);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, c);

Expand All @@ -2695,7 +2691,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
cris_cc_mask(dc, 0);

if (dc->op2 == 15) {
tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
-offsetof(CRISCPU, env) + offsetof(CPUState, halted));
tcg_gen_movi_tl(env_pc, dc->pc + 2);
t_gen_raise_exception(EXCP_HLT);
Expand Down
26 changes: 13 additions & 13 deletions target/cris/translate_v10.c.inc
View file
Expand Up @@ -251,31 +251,31 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
LOG_DIS("moveq %d, $r%d\n", simm, dc->dst);

cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
case CRISV10_QIMM_CMPQ:
LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst);

cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
case CRISV10_QIMM_ADDQ:
LOG_DIS("addq %d, $r%d\n", imm, dc->dst);

cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
case CRISV10_QIMM_ANDQ:
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);

cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_AND, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
Expand All @@ -285,7 +285,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
cris_cc_mask(dc, CC_MASK_NZVC);
op = imm & (1 << 5);
imm &= 0x1f;
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
if (op) {
cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
Expand All @@ -305,23 +305,23 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
}
imm &= 0x1f;
cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, op, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
case CRISV10_QIMM_SUBQ:
LOG_DIS("subq %d, $r%d\n", imm, dc->dst);

cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(imm);
c = tcg_constant_tl(imm);
cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
case CRISV10_QIMM_ORQ:
LOG_DIS("andq %d, $r%d\n", simm, dc->dst);

cris_cc_mask(dc, CC_MASK_NZVC);
c = tcg_const_tl(simm);
c = tcg_constant_tl(simm);
cris_alu(dc, CC_OP_OR, cpu_R[dc->dst],
cpu_R[dc->dst], c, 4);
break;
Expand Down Expand Up @@ -1014,7 +1014,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
cris_alu_m_alloc_temps(t);
insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]);
tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
c = tcg_const_tl(0);
c = tcg_constant_tl(0);
cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst],
t[0], c, size);
break;
Expand Down Expand Up @@ -1111,7 +1111,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
if (dc->mode == CRISV10_MODE_AUTOINC)
insn_len += size;

c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
dc->jmp_pc = imm;
cris_prepare_jmp(dc, JMP_DIRECT);
Expand All @@ -1121,7 +1121,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("break %d\n", dc->src);
cris_evaluate_flags(dc);
tcg_gen_movi_tl(env_pc, dc->pc + 2);
c = tcg_const_tl(dc->src + 2);
c = tcg_constant_tl(dc->src + 2);
t_gen_mov_env_TN(trap_vector, c);
t_gen_raise_exception(EXCP_BREAK);
dc->base.is_jmp = DISAS_NORETURN;
Expand All @@ -1130,7 +1130,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size,
dc->opcode, dc->src, dc->dst);
t[0] = tcg_temp_new();
c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
crisv10_prepare_memaddr(dc, t[0], size);
gen_load(dc, env_btarget, t[0], 4, 0);
Expand All @@ -1153,7 +1153,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n",
dc->pc, dc->opcode, dc->dst, dc->src);
tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]);
c = tcg_const_tl(dc->pc + insn_len);
c = tcg_constant_tl(dc->pc + insn_len);
t_gen_mov_preg_TN(dc, dc->dst, c);
cris_prepare_jmp(dc, JMP_INDIRECT);
dc->delayed_branch--; /* v10 has no dslot here. */
Expand Down
2 changes: 0 additions & 2 deletions target/hexagon/cpu-param.h
View file
Expand Up @@ -24,6 +24,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define NB_MMU_MODES 1

#endif
1 change: 0 additions & 1 deletion target/hppa/cpu-param.h
View file
Expand Up @@ -29,6 +29,5 @@
# define TARGET_PHYS_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 5

#endif
35 changes: 20 additions & 15 deletions target/hppa/translate.c
View file
Expand Up @@ -135,8 +135,6 @@
#define tcg_gen_extract_reg tcg_gen_extract_i64
#define tcg_gen_sextract_reg tcg_gen_sextract_i64
#define tcg_gen_extract2_reg tcg_gen_extract2_i64
#define tcg_const_reg tcg_const_i64
#define tcg_const_local_reg tcg_const_local_i64
#define tcg_constant_reg tcg_constant_i64
#define tcg_gen_movcond_reg tcg_gen_movcond_i64
#define tcg_gen_add2_reg tcg_gen_add2_i64
Expand Down Expand Up @@ -228,8 +226,6 @@
#define tcg_gen_extract_reg tcg_gen_extract_i32
#define tcg_gen_sextract_reg tcg_gen_sextract_i32
#define tcg_gen_extract2_reg tcg_gen_extract2_i32
#define tcg_const_reg tcg_const_i32
#define tcg_const_local_reg tcg_const_local_i32
#define tcg_constant_reg tcg_constant_i32
#define tcg_gen_movcond_reg tcg_gen_movcond_i32
#define tcg_gen_add2_reg tcg_gen_add2_i32
Expand Down Expand Up @@ -574,23 +570,25 @@ static TCGv_i32 load_frw_i32(unsigned rt)
static TCGv_i32 load_frw0_i32(unsigned rt)
{
if (rt == 0) {
return tcg_const_i32(0);
TCGv_i32 ret = tcg_temp_new_i32();
tcg_gen_movi_i32(ret, 0);
return ret;
} else {
return load_frw_i32(rt);
}
}

static TCGv_i64 load_frw0_i64(unsigned rt)
{
TCGv_i64 ret = tcg_temp_new_i64();
if (rt == 0) {
return tcg_const_i64(0);
tcg_gen_movi_i64(ret, 0);
} else {
TCGv_i64 ret = tcg_temp_new_i64();
tcg_gen_ld32u_i64(ret, cpu_env,
offsetof(CPUHPPAState, fr[rt & 31])
+ (rt & 32 ? LO_OFS : HI_OFS));
return ret;
}
return ret;
}

static void save_frw_i32(unsigned rt, TCGv_i32 val)
Expand All @@ -613,7 +611,9 @@ static TCGv_i64 load_frd(unsigned rt)
static TCGv_i64 load_frd0(unsigned rt)
{
if (rt == 0) {
return tcg_const_i64(0);
TCGv_i64 ret = tcg_temp_new_i64();
tcg_gen_movi_i64(ret, 0);
return ret;
} else {
return load_frd(rt);
}
Expand Down Expand Up @@ -3330,7 +3330,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
/* Convert big-endian bit numbering in SAR to left-shift. */
tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1);

mask = tcg_const_reg(msb + (msb - 1));
mask = tcg_temp_new();
tcg_gen_movi_reg(mask, msb + (msb - 1));
tcg_gen_and_reg(tmp, val, mask);
if (rs) {
tcg_gen_shl_reg(mask, mask, shift);
Expand Down Expand Up @@ -3547,12 +3548,16 @@ static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)

static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a)
{
uint64_t ret;

if (TARGET_REGISTER_BITS == 64) {
ret = 0x13080000000000ULL; /* PA8700 (PCX-W2) */
} else {
ret = 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */
}

nullify_over(ctx);
#if TARGET_REGISTER_BITS == 64
save_frd(0, tcg_const_i64(0x13080000000000ULL)); /* PA8700 (PCX-W2) */
#else
save_frd(0, tcg_const_i64(0x0f080000000000ULL)); /* PA7300LC (PCX-L2) */
#endif
save_frd(0, tcg_constant_i64(ret));
return nullify_end(ctx);
}

Expand Down
1 change: 0 additions & 1 deletion target/i386/cpu-param.h
View file
Expand Up @@ -23,6 +23,5 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 5

#endif
83 changes: 42 additions & 41 deletions target/i386/tcg/translate.c
View file

Large diffs are not rendered by default.

1 change: 0 additions & 1 deletion target/loongarch/cpu-param.h
View file
Expand Up @@ -13,6 +13,5 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 48

#define TARGET_PAGE_BITS 14
#define NB_MMU_MODES 5

#endif
1 change: 0 additions & 1 deletion target/m68k/cpu-param.h
View file
Expand Up @@ -17,6 +17,5 @@
#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 2

#endif
231 changes: 114 additions & 117 deletions target/m68k/translate.c
View file

Large diffs are not rendered by default.

1 change: 0 additions & 1 deletion target/microblaze/cpu-param.h
View file
Expand Up @@ -28,6 +28,5 @@

/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 3

#endif
2 changes: 1 addition & 1 deletion target/microblaze/cpu.h
View file
Expand Up @@ -394,7 +394,7 @@ void mb_tcg_init(void);
#define MMU_NOMMU_IDX 0
#define MMU_KERNEL_IDX 1
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
/* See NB_MMU_MODES in cpu-defs.h. */

#include "exec/cpu-all.h"

Expand Down
1 change: 0 additions & 1 deletion target/mips/cpu-param.h
View file
Expand Up @@ -29,6 +29,5 @@
#define TARGET_PAGE_BITS_VARY
#define TARGET_PAGE_BITS_MIN 12
#endif
#define NB_MMU_MODES 4

#endif
12 changes: 2 additions & 10 deletions target/mips/tcg/micromips_translate.c.inc
View file
Expand Up @@ -704,8 +704,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,

gen_base_offset_addr(ctx, t0, base, offset);

t1 = tcg_const_tl(reglist);
t2 = tcg_const_i32(ctx->mem_idx);
t1 = tcg_constant_tl(reglist);
t2 = tcg_constant_i32(ctx->mem_idx);

save_cpu_state(ctx, 1);
switch (opc) {
Expand All @@ -724,9 +724,6 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
break;
#endif
}
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free_i32(t2);
}


Expand Down Expand Up @@ -1018,8 +1015,6 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
break;
#endif
}
tcg_temp_free(t0);
tcg_temp_free(t1);
}

static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
Expand Down Expand Up @@ -1067,7 +1062,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)

gen_load_gpr(t0, rt);
gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
tcg_temp_free(t0);
}
break;
#endif
Expand Down Expand Up @@ -1276,7 +1270,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
* mode.
*/
ctx->base.is_jmp = DISAS_STOP;
tcg_temp_free(t0);
}
break;
case EI:
Expand All @@ -1293,7 +1286,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
*/
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
tcg_temp_free(t0);
}
break;
default:
Expand Down
9 changes: 0 additions & 9 deletions target/mips/tcg/msa_translate.c
View file
Expand Up @@ -217,8 +217,6 @@ static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
/* if some bit is non-zero then some element is zero */
tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(tresult, t0);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}

static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
Expand All @@ -237,7 +235,6 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
tcg_gen_setcondi_i64(cond, t0, t0, 0);
tcg_gen_trunc_i64_tl(bcond, t0);
tcg_temp_free_i64(t0);

ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;

Expand Down Expand Up @@ -545,8 +542,6 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm *a)
gen_load_gpr(telm, a->ws);
gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd));

tcg_temp_free(telm);

return true;
}

Expand All @@ -563,8 +558,6 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a)
gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws));
gen_store_gpr(telm, a->wd);

tcg_temp_free(telm);

return true;
}

Expand Down Expand Up @@ -782,8 +775,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,
gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);
gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr);

tcg_temp_free(taddr);

return true;
}

Expand Down
55 changes: 2 additions & 53 deletions target/mips/tcg/mxu_translate.c
View file
Expand Up @@ -513,8 +513,6 @@ static void gen_mxu_s32i2m(DisasContext *ctx)
} else if (XRa == 16) {
gen_store_mxu_cr(t0);
}

tcg_temp_free(t0);
}

/*
Expand All @@ -537,8 +535,6 @@ static void gen_mxu_s32m2i(DisasContext *ctx)
}

gen_store_gpr(t0, Rb);

tcg_temp_free(t0);
}

/*
Expand Down Expand Up @@ -613,9 +609,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
}

gen_store_mxu_gpr(t0, XRa);

tcg_temp_free(t0);
tcg_temp_free(t1);
}

/*
Expand Down Expand Up @@ -664,11 +657,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
}
gen_store_mxu_gpr(t3, XRa);
gen_store_mxu_gpr(t2, XRd);

tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(t3);
}

/*
Expand Down Expand Up @@ -741,11 +729,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
}
gen_store_mxu_gpr(t3, XRa);
gen_store_mxu_gpr(t2, XRd);

tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(t3);
}

/*
Expand Down Expand Up @@ -821,15 +804,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)

gen_store_mxu_gpr(t0, XRd);
gen_store_mxu_gpr(t1, XRa);

tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
tcg_temp_free(t3);
tcg_temp_free(t4);
tcg_temp_free(t5);
tcg_temp_free(t6);
tcg_temp_free(t7);
}

/*
Expand Down Expand Up @@ -860,9 +834,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP));

gen_store_mxu_gpr(t1, XRa);

tcg_temp_free(t0);
tcg_temp_free(t1);
}


Expand Down Expand Up @@ -1101,7 +1072,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do half-word-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_const_i32(0);
TCGv_i32 t1 = tcg_constant_i32(0);

/* the left half-word first */
tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);
Expand All @@ -1125,9 +1096,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
tcg_gen_shri_i32(t0, t0, 16);
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);

tcg_temp_free(t1);
tcg_temp_free(t0);
} else if (unlikely(XRb == XRc)) {
/* both operands same -> just set destination to one of them */
tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
Expand Down Expand Up @@ -1161,9 +1129,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
tcg_gen_shri_i32(t0, t0, 16);
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);

tcg_temp_free(t1);
tcg_temp_free(t0);
}
}

Expand Down Expand Up @@ -1198,7 +1163,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
uint32_t XRx = XRb ? XRb : XRc;
/* ...and do byte-wise max/min with one operand 0 */
TCGv_i32 t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_const_i32(0);
TCGv_i32 t1 = tcg_constant_i32(0);
int32_t i;

/* the leftmost byte (byte 3) first */
Expand Down Expand Up @@ -1226,9 +1191,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}

tcg_temp_free(t1);
tcg_temp_free(t0);
} else if (unlikely(XRb == XRc)) {
/* both operands same -> just set destination to one of them */
tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
Expand Down Expand Up @@ -1266,9 +1228,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
/* finally update the destination */
tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);
}

tcg_temp_free(t1);
tcg_temp_free(t0);
}
}

Expand Down Expand Up @@ -1384,9 +1343,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 24);

tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);

tcg_temp_free(t1);
tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN2:
Expand All @@ -1410,9 +1366,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 16);

tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);

tcg_temp_free(t1);
tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN3:
Expand All @@ -1436,9 +1389,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)
tcg_gen_shri_i32(t1, t1, 8);

tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);

tcg_temp_free(t1);
tcg_temp_free(t0);
}
break;
case MXU_OPTN3_PTN4:
Expand Down Expand Up @@ -1598,7 +1548,6 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
}

gen_set_label(l_exit);
tcg_temp_free(t_mxu_cr);
}

return true;
Expand Down
143 changes: 19 additions & 124 deletions target/mips/tcg/nanomips_translate.c.inc
View file

Large diffs are not rendered by default.

23 changes: 0 additions & 23 deletions target/mips/tcg/octeon_translate.c
View file
Expand Up @@ -40,8 +40,6 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
ctx->hflags |= MIPS_HFLAG_BC;
ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;
ctx->hflags |= MIPS_HFLAG_BDS32;

tcg_temp_free(t0);
return true;
}

Expand All @@ -61,10 +59,6 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)

tcg_gen_add_tl(t0, t0, t1);
tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);

tcg_temp_free(t0);
tcg_temp_free(t1);

return true;
}

Expand All @@ -83,10 +77,6 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
gen_load_gpr(t1, a->rt);

tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);

tcg_temp_free(t0);
tcg_temp_free(t1);

return true;
}

Expand All @@ -103,8 +93,6 @@ static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
gen_load_gpr(t0, a->rs);
tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);
gen_store_gpr(t0, a->rt);
tcg_temp_free(t0);

return true;
}

Expand All @@ -121,8 +109,6 @@ static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
gen_load_gpr(t0, a->rs);
tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);
gen_store_gpr(t0, a->rt);
tcg_temp_free(t0);

return true;
}

Expand All @@ -142,8 +128,6 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a)
}
tcg_gen_ctpop_tl(t0, t0);
gen_store_gpr(t0, a->rd);
tcg_temp_free(t0);

return true;
}

Expand All @@ -167,10 +151,6 @@ static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)
} else {
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
}

tcg_temp_free(t0);
tcg_temp_free(t1);

return true;
}

Expand All @@ -194,8 +174,5 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
} else {
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
}

tcg_temp_free(t0);

return true;
}
819 changes: 120 additions & 699 deletions target/mips/tcg/translate.c
View file

Large diffs are not rendered by default.

7 changes: 0 additions & 7 deletions target/mips/tcg/translate_addr_const.c
View file
Expand Up @@ -30,10 +30,6 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);

tcg_temp_free(t1);
tcg_temp_free(t0);

return true;
}

Expand All @@ -54,8 +50,5 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
gen_load_gpr(t1, rt);
tcg_gen_shli_tl(t0, t0, sa + 1);
tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
tcg_temp_free(t1);
tcg_temp_free(t0);

return true;
}
45 changes: 2 additions & 43 deletions target/mips/tcg/tx79_translate.c
View file
Expand Up @@ -138,10 +138,6 @@ static bool trans_parallel_arith(DisasContext *ctx, arg_r *a,
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx);

tcg_temp_free(bx);
tcg_temp_free(ax);

return true;
}

Expand Down Expand Up @@ -247,8 +243,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
return true;
}

c0 = tcg_const_tl(0);
c1 = tcg_const_tl(0xffffffff);
c0 = tcg_constant_tl(0);
c1 = tcg_constant_tl(0xffffffff);
ax = tcg_temp_new_i64();
bx = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
Expand All @@ -273,15 +269,6 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,
tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0);
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen);
}

tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_temp_free(t0);
tcg_temp_free(bx);
tcg_temp_free(ax);
tcg_temp_free(c1);
tcg_temp_free(c0);

return true;
}

Expand Down Expand Up @@ -362,10 +349,6 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_addi_i64(addr, addr, 8);
tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
gen_store_gpr_hi(t0, a->rt);

tcg_temp_free(t0);
tcg_temp_free(addr);

return true;
}

Expand All @@ -389,10 +372,6 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ);

tcg_temp_free(addr);
tcg_temp_free(t0);

return true;
}

Expand Down Expand Up @@ -458,11 +437,6 @@ static bool trans_PPACW(DisasContext *ctx, arg_r *a)

gen_load_gpr_hi(t0, a->rs); /* a1 */
tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32);

tcg_temp_free(t0);
tcg_temp_free(b0);
tcg_temp_free(a0);

return true;
}

Expand Down Expand Up @@ -506,10 +480,6 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen)
tcg_gen_shri_i64(bx, bx, wlen);
tcg_gen_shri_i64(ax, ax, wlen);
}

tcg_temp_free(bx);
tcg_temp_free(ax);

return true;
}

Expand Down Expand Up @@ -541,10 +511,6 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_r *a)
gen_load_gpr(ax, a->rs);
gen_load_gpr(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);

tcg_temp_free(bx);
tcg_temp_free(ax);

return true;
}

Expand All @@ -564,10 +530,6 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_r *a)
gen_load_gpr_hi(ax, a->rs);
gen_load_gpr_hi(bx, a->rt);
gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx);

tcg_temp_free(bx);
tcg_temp_free(ax);

return true;
}

Expand Down Expand Up @@ -678,8 +640,5 @@ static bool trans_PROT3W(DisasContext *ctx, arg_r *a)

tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32);
tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32);

tcg_temp_free(ax);

return true;
}
4 changes: 0 additions & 4 deletions target/mips/tcg/vr54xx_translate.c
View file
Expand Up @@ -49,10 +49,6 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a,
gen_helper_mult_acc(t0, cpu_env, t0, t1);

gen_store_gpr(t0, a->rd);

tcg_temp_free(t0);
tcg_temp_free(t1);

return true;
}

Expand Down
1 change: 0 additions & 1 deletion target/nios2/cpu-param.h
View file
Expand Up @@ -16,6 +16,5 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define NB_MMU_MODES 2

#endif
1 change: 0 additions & 1 deletion target/openrisc/cpu-param.h
View file
Expand Up @@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 3

#endif
1 change: 0 additions & 1 deletion target/ppc/cpu-param.h
View file
Expand Up @@ -32,6 +32,5 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define TARGET_PAGE_BITS 12
#define NB_MMU_MODES 10

#endif
4 changes: 2 additions & 2 deletions target/ppc/power8-pmu-regs.c.inc
View file
Expand Up @@ -177,7 +177,7 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)

void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
{
TCGv_i32 t_sprn = tcg_const_i32(sprn);
TCGv_i32 t_sprn = tcg_constant_i32(sprn);

gen_icount_io_start(ctx);
gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
Expand Down Expand Up @@ -210,7 +210,7 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)

void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t_sprn = tcg_const_i32(sprn);
TCGv_i32 t_sprn = tcg_constant_i32(sprn);

gen_icount_io_start(ctx);
gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
Expand Down
148 changes: 74 additions & 74 deletions target/ppc/translate.c
View file

Large diffs are not rendered by default.

50 changes: 26 additions & 24 deletions target/ppc/translate/fixedpoint-impl.c.inc
View file
Expand Up @@ -484,33 +484,35 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)

static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
{
const uint64_t carry_bits = 0x1111111111111111ULL;
TCGv t0, t1, carry, zero = tcg_constant_tl(0);
const target_ulong carry_bits = (target_ulong)-1 / 0xf;
TCGv in1, in2, carryl, carryh, tmp;
TCGv zero = tcg_constant_tl(0);

REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);

t0 = tcg_temp_new();
t1 = tcg_const_tl(0);
carry = tcg_const_tl(0);

for (int i = 0; i < 16; i++) {
tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4);
tcg_gen_andi_tl(t0, t0, 0xf);
tcg_gen_add_tl(t1, t1, t0);

tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4);
tcg_gen_andi_tl(t0, t0, 0xf);
tcg_gen_add_tl(t1, t1, t0);

tcg_gen_andi_tl(t1, t1, 0x10);
tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero);

tcg_gen_shli_tl(t0, t1, i * 4);
tcg_gen_or_tl(carry, carry, t0);
}

tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);
in1 = cpu_gpr[a->ra];
in2 = cpu_gpr[a->rb];
tmp = tcg_temp_new();
carryl = tcg_temp_new();
carryh = tcg_temp_new();

/* Addition with carry. */
tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero);
/* Addition without carry. */
tcg_gen_xor_tl(tmp, in1, in2);
/* Difference between the two is carry in to each bit. */
tcg_gen_xor_tl(carryl, carryl, tmp);

/*
* The carry-out that we're looking for is the carry-in to
* the next nibble. Shift the double-word down one nibble,
* which puts all of the bits back into one word.
*/
tcg_gen_extract2_tl(carryl, carryl, carryh, 4);

/* Invert, isolate the carry bits, and produce 6's. */
tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl);
tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
return true;
}

Expand Down
26 changes: 12 additions & 14 deletions target/ppc/translate/fp-impl.c.inc
View file
Expand Up @@ -348,7 +348,7 @@ static void gen_fcmpo(DisasContext *ctx)
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
crf = tcg_const_i32(crfD(ctx->opcode));
crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpo(cpu_env, t0, t1, crf);
Expand All @@ -368,7 +368,7 @@ static void gen_fcmpu(DisasContext *ctx)
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
crf = tcg_const_i32(crfD(ctx->opcode));
crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpu(cpu_env, t0, t1, crf);
Expand Down Expand Up @@ -541,7 +541,7 @@ static void gen_mcrfs(DisasContext *ctx)
tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
~((0xF << shift) & FP_EX_CLEAR_BITS));
/* FEX and VX need to be updated, so don't set fpscr directly */
tmask = tcg_const_i32(1 << nibble);
tmask = tcg_constant_i32(1 << nibble);
gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
}

Expand Down Expand Up @@ -681,9 +681,7 @@ static void gen_mtfsb0(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
gen_reset_fpstatus();
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
TCGv_i32 t0;
t0 = tcg_const_i32(crb);
gen_helper_fpscr_clrbit(cpu_env, t0);
gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
Expand All @@ -703,9 +701,7 @@ static void gen_mtfsb1(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
/* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
TCGv_i32 t0;
t0 = tcg_const_i32(crb);
gen_helper_fpscr_setbit(cpu_env, t0);
gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
Expand Down Expand Up @@ -733,10 +729,12 @@ static void gen_mtfsf(DisasContext *ctx)
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
if (l) {
t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
if (!l) {
t0 = tcg_constant_i32(flm << (w * 8));
} else if (ctx->insns_flags2 & PPC2_ISA205) {
t0 = tcg_constant_i32(0xffff);
} else {
t0 = tcg_const_i32(flm << (w * 8));
t0 = tcg_constant_i32(0xff);
}
t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode));
Expand Down Expand Up @@ -767,8 +765,8 @@ static void gen_mtfsfi(DisasContext *ctx)
return;
}
sh = (8 * w) + 7 - bf;
t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
t1 = tcg_const_i32(1 << sh);
t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
t1 = tcg_constant_i32(1 << sh);
gen_helper_store_fpscr(cpu_env, t0, t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
Expand Down
130 changes: 68 additions & 62 deletions target/ppc/translate/vmx-impl.c.inc
View file
Expand Up @@ -171,53 +171,56 @@ static void gen_mtvscr(DisasContext *ctx)
gen_helper_mtvscr(cpu_env, val);
}

static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry)
{
TCGv_i64 t0;
TCGv_i64 t1;
TCGv_i64 t2;
TCGv_i64 avr;
TCGv_i64 ten, z;

if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}

t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
avr = tcg_temp_new_i64();
ten = tcg_constant_i64(10);
z = tcg_constant_i64(0);

if (add_cin) {
get_avr64(avr, rA(ctx->opcode), false);
tcg_gen_mulu2_i64(t0, t1, avr, ten);
get_avr64(avr, rB(ctx->opcode), false);
tcg_gen_andi_i64(t2, avr, 0xF);
tcg_gen_add2_i64(avr, t2, t0, t1, t2, z);
set_avr64(rD(ctx->opcode), avr, false);
} else {
get_avr64(avr, rA(ctx->opcode), false);
tcg_gen_mulu2_i64(avr, t2, avr, ten);
set_avr64(rD(ctx->opcode), avr, false);
}

if (ret_carry) {
get_avr64(avr, rA(ctx->opcode), true);
tcg_gen_mulu2_i64(t0, t1, avr, ten);
tcg_gen_add2_i64(t0, avr, t0, t1, t2, z);
set_avr64(rD(ctx->opcode), avr, false);
set_avr64(rD(ctx->opcode), z, true);
} else {
get_avr64(avr, rA(ctx->opcode), true);
tcg_gen_mul_i64(t0, avr, ten);
tcg_gen_add_i64(avr, t0, t2);
set_avr64(rD(ctx->opcode), avr, true);
}
}

#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_i64 t0; \
TCGv_i64 t1; \
TCGv_i64 t2; \
TCGv_i64 avr; \
TCGv_i64 ten, z; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
\
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
t2 = tcg_temp_new_i64(); \
avr = tcg_temp_new_i64(); \
ten = tcg_const_i64(10); \
z = tcg_const_i64(0); \
\
if (add_cin) { \
get_avr64(avr, rA(ctx->opcode), false); \
tcg_gen_mulu2_i64(t0, t1, avr, ten); \
get_avr64(avr, rB(ctx->opcode), false); \
tcg_gen_andi_i64(t2, avr, 0xF); \
tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
set_avr64(rD(ctx->opcode), avr, false); \
} else { \
get_avr64(avr, rA(ctx->opcode), false); \
tcg_gen_mulu2_i64(avr, t2, avr, ten); \
set_avr64(rD(ctx->opcode), avr, false); \
} \
\
if (ret_carry) { \
get_avr64(avr, rA(ctx->opcode), true); \
tcg_gen_mulu2_i64(t0, t1, avr, ten); \
tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
set_avr64(rD(ctx->opcode), avr, false); \
set_avr64(rD(ctx->opcode), z, true); \
} else { \
get_avr64(avr, rA(ctx->opcode), true); \
tcg_gen_mul_i64(t0, avr, ten); \
tcg_gen_add_i64(avr, t0, t2); \
set_avr64(rD(ctx->opcode), avr, true); \
} \
} \
static void glue(gen_, name)(DisasContext *ctx) \
{ gen_vx_vmul10(ctx, add_cin, ret_carry); }

GEN_VX_VMUL10(vmul10uq, 0, 0);
GEN_VX_VMUL10(vmul10euq, 1, 0);
Expand Down Expand Up @@ -903,7 +906,6 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
hi = tcg_temp_new_i64();
lo = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_const_i64(0);

get_avr64(lo, a->vra, false);
get_avr64(hi, a->vra, true);
Expand All @@ -914,7 +916,10 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
if (right) {
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
if (alg) {
t1 = tcg_temp_new_i64();
tcg_gen_sari_i64(t1, lo, 63);
} else {
t1 = zero;
}
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi);
} else {
Expand Down Expand Up @@ -1619,7 +1624,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, rb, uimm); \
Expand Down Expand Up @@ -1960,7 +1965,7 @@ static void gen_vsldoi(DisasContext *ctx)
ra = gen_avr_ptr(rA(ctx->opcode));
rb = gen_avr_ptr(rB(ctx->opcode));
rd = gen_avr_ptr(rD(ctx->opcode));
sh = tcg_const_i32(VSH(ctx->opcode));
sh = tcg_constant_i32(VSH(ctx->opcode));
gen_helper_vsldoi(rd, ra, rb, sh);
}

Expand Down Expand Up @@ -2231,24 +2236,25 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)

static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
{
TCGv_i64 rt, vrb, mask;
rt = tcg_const_i64(0);
vrb = tcg_temp_new_i64();
TCGv_i64 r[2], mask;

r[0] = tcg_temp_new_i64();
r[1] = tcg_temp_new_i64();
mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));

for (int i = 0; i < 2; i++) {
get_avr64(vrb, a->vrb, i);
get_avr64(r[i], a->vrb, i);
if (a->mp) {
tcg_gen_and_i64(vrb, mask, vrb);
tcg_gen_and_i64(r[i], mask, r[i]);
} else {
tcg_gen_andc_i64(vrb, mask, vrb);
tcg_gen_andc_i64(r[i], mask, r[i]);
}
tcg_gen_ctpop_i64(vrb, vrb);
tcg_gen_add_i64(rt, rt, vrb);
tcg_gen_ctpop_i64(r[i], r[i]);
}

tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
tcg_gen_add_i64(r[0], r[0], r[1]);
tcg_gen_shli_i64(r[0], r[0], TARGET_LONG_BITS - 8 + vece);
tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], r[0]);
return true;
}

Expand Down Expand Up @@ -2569,7 +2575,7 @@ static void gen_##op(DisasContext *ctx) \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
}
Expand All @@ -2588,7 +2594,7 @@ static void gen_##op(DisasContext *ctx) \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, rb, ps); \
}
Expand Down Expand Up @@ -2720,7 +2726,7 @@ static void gen_##op(DisasContext *ctx) \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
st_six = tcg_const_i32(rB(ctx->opcode)); \
st_six = tcg_constant_i32(rB(ctx->opcode)); \
gen_helper_##op(rd, ra, st_six); \
}

Expand Down
36 changes: 19 additions & 17 deletions target/ppc/translate/vsx-impl.c.inc
View file
Expand Up @@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx)
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{
TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();

Expand Down Expand Up @@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);

ro = tcg_const_i32(a->rc);
ro = tcg_constant_i32(a->rc);

xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
Expand Down Expand Up @@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
gen_helper_##name(cpu_env, opc); \
}

Expand Down Expand Up @@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xa, xb); \
Expand All @@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xb); \
}
Expand All @@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
Expand All @@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xt, xb); \
Expand All @@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
opc = tcg_const_i32(ctx->opcode); \
opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xa, xb); \
Expand Down Expand Up @@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx)
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
zr = tcg_constant_i64(0);
nan = tcg_constant_i64(2047);

get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_extract_i64(exp, t1, 52, 11);
Expand Down Expand Up @@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
nan = tcg_const_i64(32767);
zr = tcg_constant_i64(0);
nan = tcg_constant_i64(32767);

tcg_gen_extract_i64(exp, xbh, 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
Expand Down Expand Up @@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
get_cpu_vsr(xbl, xB(ctx->opcode), false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
zr = tcg_constant_i64(0);
nan = tcg_constant_i64(2047);

tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
Expand Down Expand Up @@ -2449,7 +2449,8 @@ static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c,
TCGv_i64 conj, disj;

conj = tcg_temp_new_i64();
disj = tcg_const_i64(0);
disj = tcg_temp_new_i64();
tcg_gen_movi_i64(disj, 0);

/* Iterate over set bits from the least to the most significant bit */
while (imm) {
Expand Down Expand Up @@ -2492,8 +2493,9 @@ static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
int bit;
TCGv_vec disj, conj;

disj = tcg_const_zeros_vec_matching(t);
conj = tcg_temp_new_vec_matching(t);
disj = tcg_temp_new_vec_matching(t);
tcg_gen_dupi_vec(vece, disj, 0);

/* Iterate over set bits from the least to the most significant bit */
while (imm) {
Expand Down Expand Up @@ -2546,7 +2548,7 @@ static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a)

/* Equivalent functions that can be implemented with a single gen_gvec */
switch (a->imm) {
case 0b00000000: /* true */
case 0b00000000: /* false */
set_cpu_vsr(a->xt, tcg_constant_i64(0), true);
set_cpu_vsr(a->xt, tcg_constant_i64(0), false);
break;
Expand Down
1 change: 0 additions & 1 deletion target/riscv/cpu-param.h
View file
Expand Up @@ -27,6 +27,5 @@
* - S mode HLV/HLVX/HSV 0b101
* - M mode HLV/HLVX/HSV 0b111
*/
#define NB_MMU_MODES 8

#endif
2 changes: 0 additions & 2 deletions target/rx/cpu-param.h
View file
Expand Up @@ -25,6 +25,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32

#define NB_MMU_MODES 1

#endif
84 changes: 36 additions & 48 deletions target/rx/translate.c
View file
Expand Up @@ -456,7 +456,7 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
{
TCGv imm, mem;
imm = tcg_const_i32(a->imm);
imm = tcg_constant_i32(a->imm);
mem = tcg_temp_new();
tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
rx_gen_st(a->sz, imm, mem);
Expand Down Expand Up @@ -729,8 +729,8 @@ static inline void stcond(TCGCond cond, int rd, int imm)
{
TCGv z;
TCGv _imm;
z = tcg_const_i32(0);
_imm = tcg_const_i32(imm);
z = tcg_constant_i32(0);
_imm = tcg_constant_i32(imm);
tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
_imm, cpu_regs[rd]);
}
Expand Down Expand Up @@ -815,7 +815,7 @@ static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)

static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
{
TCGv imm = tcg_const_i32(src2);
TCGv imm = tcg_constant_i32(src2);
opr(cpu_regs[dst], cpu_regs[src], imm);
}

Expand Down Expand Up @@ -967,14 +967,13 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
/* ret = arg1 + arg2 + psw_c */
static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv z;
z = tcg_const_i32(0);
TCGv z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
tcg_gen_xor_i32(z, arg1, arg2);
tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_mov_i32(ret, cpu_psw_s);
}

Expand Down Expand Up @@ -1006,13 +1005,12 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a)
/* ret = arg1 + arg2 */
static void rx_add(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv z;
z = tcg_const_i32(0);
TCGv z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
tcg_gen_xor_i32(z, arg1, arg2);
tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_mov_i32(ret, cpu_psw_s);
}

Expand Down Expand Up @@ -1042,23 +1040,23 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a)
/* ret = arg1 - arg2 */
static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv temp;
tcg_gen_sub_i32(cpu_psw_s, arg1, arg2);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
temp = tcg_temp_new_i32();
tcg_gen_xor_i32(temp, arg1, arg2);
tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
/* CMP not required return */
if (ret) {
tcg_gen_mov_i32(ret, cpu_psw_s);
}
}

static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2)
{
rx_sub(NULL, arg1, arg2);
}

/* ret = arg1 - arg2 - !psw_c */
/* -> ret = arg1 + ~arg2 + psw_c */
static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2)
Expand Down Expand Up @@ -1126,21 +1124,11 @@ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
return true;
}

static void rx_abs(TCGv ret, TCGv arg1)
{
TCGv neg;
TCGv zero;
neg = tcg_temp_new();
zero = tcg_const_i32(0);
tcg_gen_neg_i32(neg, arg1);
tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1);
}

/* abs rd */
/* abs rs, rd */
static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a)
{
rx_gen_op_rr(rx_abs, a->rd, a->rs);
rx_gen_op_rr(tcg_gen_abs_i32, a->rd, a->rs);
return true;
}

Expand Down Expand Up @@ -1200,7 +1188,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
/* emul #imm, rd */
static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
{
TCGv imm = tcg_const_i32(a->imm);
TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
Expand All @@ -1227,7 +1215,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
/* emulu #imm, rd */
static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
{
TCGv imm = tcg_const_i32(a->imm);
TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
Expand Down Expand Up @@ -1325,10 +1313,10 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
done = gen_new_label();
/* if (cpu_regs[a->rs]) { */
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift);
count = tcg_const_i32(32);
count = tcg_temp_new();
tmp = tcg_temp_new();
tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31);
tcg_gen_sub_i32(count, count, tmp);
tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp);
tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count);
tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp);
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0);
Expand Down Expand Up @@ -1597,7 +1585,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)

static inline void rx_save_pc(DisasContext *ctx)
{
TCGv pc = tcg_const_i32(ctx->base.pc_next);
TCGv pc = tcg_constant_i32(ctx->base.pc_next);
push(pc);
}

Expand Down Expand Up @@ -1680,7 +1668,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)

#define STRING(op) \
do { \
TCGv size = tcg_const_i32(a->sz); \
TCGv size = tcg_constant_i32(a->sz); \
gen_helper_##op(cpu_env, size); \
} while (0)

Expand Down Expand Up @@ -1811,7 +1799,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
/* racw #imm */
static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
{
TCGv imm = tcg_const_i32(a->imm + 1);
TCGv imm = tcg_constant_i32(a->imm + 1);
gen_helper_racw(cpu_env, imm);
return true;
}
Expand All @@ -1821,7 +1809,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
{
TCGv tmp, z;
tmp = tcg_temp_new();
z = tcg_const_i32(0);
z = tcg_constant_i32(0);
/* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
/* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
Expand All @@ -1843,7 +1831,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
cat3(arg_, name, _ir) * a) \
{ \
TCGv imm = tcg_const_i32(li(ctx, 0)); \
TCGv imm = tcg_constant_i32(li(ctx, 0)); \
gen_helper_##op(cpu_regs[a->rd], cpu_env, \
cpu_regs[a->rd], imm); \
return true; \
Expand Down Expand Up @@ -1877,7 +1865,7 @@ FOP(FDIV, fdiv)
/* fcmp #imm, rd */
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{
TCGv imm = tcg_const_i32(li(ctx, 0));
TCGv imm = tcg_constant_i32(li(ctx, 0));
gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
return true;
}
Expand Down Expand Up @@ -1974,7 +1962,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
{ \
TCGv mask, mem, addr; \
mem = tcg_temp_new(); \
mask = tcg_const_i32(1 << a->imm); \
mask = tcg_constant_i32(1 << a->imm); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \
return true; \
Expand All @@ -1983,29 +1971,29 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _ir) * a) \
{ \
TCGv mask; \
mask = tcg_const_i32(1 << a->imm); \
mask = tcg_constant_i32(1 << a->imm); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \
} \
static bool cat3(trans_, name, _rr)(DisasContext *ctx, \
cat3(arg_, name, _rr) * a) \
{ \
TCGv mask, b; \
mask = tcg_const_i32(1); \
mask = tcg_temp_new(); \
b = tcg_temp_new(); \
tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
tcg_gen_shl_i32(mask, mask, b); \
tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \
} \
static bool cat3(trans_, name, _rm)(DisasContext *ctx, \
cat3(arg_, name, _rm) * a) \
{ \
TCGv mask, mem, addr, b; \
mask = tcg_const_i32(1); \
mask = tcg_temp_new(); \
b = tcg_temp_new(); \
tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
tcg_gen_shl_i32(mask, mask, b); \
tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
mem = tcg_temp_new(); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \
Expand Down Expand Up @@ -2128,7 +2116,7 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
{
TCGv imm;

imm = tcg_const_i32(a->imm);
imm = tcg_constant_i32(a->imm);
move_to_cr(ctx, imm, a->cr);
return true;
}
Expand Down Expand Up @@ -2190,7 +2178,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
TCGv vec;

tcg_debug_assert(a->imm < 0x100);
vec = tcg_const_i32(a->imm);
vec = tcg_constant_i32(a->imm);
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_rxint(cpu_env, vec);
ctx->base.is_jmp = DISAS_NORETURN;
Expand Down
1 change: 0 additions & 1 deletion target/s390x/cpu-param.h
View file
Expand Up @@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define NB_MMU_MODES 4

#endif
208 changes: 21 additions & 187 deletions target/s390x/tcg/translate.c
View file

Large diffs are not rendered by default.

143 changes: 0 additions & 143 deletions target/s390x/tcg/translate_vx.c.inc
View file

Large diffs are not rendered by default.

1 change: 0 additions & 1 deletion target/sh4/cpu-param.h
View file
Expand Up @@ -16,6 +16,5 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
#define NB_MMU_MODES 2

#endif
35 changes: 16 additions & 19 deletions target/sh4/translate.c
View file
Expand Up @@ -526,13 +526,13 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x9000: /* mov.w @(disp,PC),Rn */
{
TCGv addr = tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2);
TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
}
return;
case 0xd000: /* mov.l @(disp,PC),Rn */
{
TCGv addr = tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3);
TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
}
return;
Expand Down Expand Up @@ -694,7 +694,7 @@ static void _decode_opc(DisasContext * ctx)
case 0x300e: /* addc Rm,Rn */
{
TCGv t0, t1;
t0 = tcg_const_tl(0);
t0 = tcg_constant_tl(0);
t1 = tcg_temp_new();
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
Expand Down Expand Up @@ -754,7 +754,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv zero = tcg_const_i32(0);
TCGv zero = tcg_constant_i32(0);

/* shift left arg1, saving the bit being pushed out and inserting
T on the right */
Expand Down Expand Up @@ -849,7 +849,7 @@ static void _decode_opc(DisasContext * ctx)
return;
case 0x600a: /* negc Rm,Rn */
{
TCGv t0 = tcg_const_i32(0);
TCGv t0 = tcg_constant_i32(0);
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
REG(B7_4), t0, cpu_sr_t, t0);
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
Expand Down Expand Up @@ -913,7 +913,7 @@ static void _decode_opc(DisasContext * ctx)
case 0x300a: /* subc Rm,Rn */
{
TCGv t0, t1;
t0 = tcg_const_tl(0);
t0 = tcg_constant_tl(0);
t1 = tcg_temp_new();
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
Expand Down Expand Up @@ -1242,7 +1242,7 @@ static void _decode_opc(DisasContext * ctx)
TCGv imm;
CHECK_NOT_DELAY_SLOT
gen_save_cpu_state(ctx, true);
imm = tcg_const_i32(B7_0);
imm = tcg_constant_i32(B7_0);
gen_helper_trapa(cpu_env, imm);
ctx->base.is_jmp = DISAS_NORETURN;
}
Expand Down Expand Up @@ -1610,12 +1610,9 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
return;
case 0x401b: /* tas.b @Rn */
{
TCGv val = tcg_const_i32(0x80);
tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val,
ctx->memidx, MO_UB);
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
}
tcg_gen_atomic_fetch_or_i32(cpu_sr_t, REG(B11_8),
tcg_constant_i32(0x80), ctx->memidx, MO_UB);
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0);
return;
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
CHECK_FPU_ENABLED
Expand Down Expand Up @@ -1712,8 +1709,8 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
CHECK_FPSCR_PR_1
{
TCGv m = tcg_const_i32((ctx->opcode >> 8) & 3);
TCGv n = tcg_const_i32((ctx->opcode >> 10) & 3);
TCGv m = tcg_constant_i32((ctx->opcode >> 8) & 3);
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
gen_helper_fipr(cpu_env, m, n);
return;
}
Expand All @@ -1725,7 +1722,7 @@ static void _decode_opc(DisasContext * ctx)
if ((ctx->opcode & 0x0300) != 0x0100) {
goto do_illegal;
}
TCGv n = tcg_const_i32((ctx->opcode >> 10) & 3);
TCGv n = tcg_constant_i32((ctx->opcode >> 10) & 3);
gen_helper_ftrv(cpu_env, n);
return;
}
Expand Down Expand Up @@ -1929,15 +1926,15 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
}
op_dst = B11_8;
op_opc = INDEX_op_xor_i32;
op_arg = tcg_const_i32(-1);
op_arg = tcg_constant_i32(-1);
break;

case 0x7000 ... 0x700f: /* add #imm,Rn */
if (op_dst != B11_8 || mv_src >= 0) {
goto fail;
}
op_opc = INDEX_op_add_i32;
op_arg = tcg_const_i32(B7_0s);
op_arg = tcg_constant_i32(B7_0s);
break;

case 0x3000: /* cmp/eq Rm,Rn */
Expand Down Expand Up @@ -1983,7 +1980,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
goto fail;
}
op_opc = INDEX_op_setcond_i32;
op_arg = tcg_const_i32(0);
op_arg = tcg_constant_i32(0);

NEXT_INSN;
if ((ctx->opcode & 0xff00) != 0x8900 /* bt label */
Expand Down
2 changes: 0 additions & 2 deletions target/sparc/cpu-param.h
View file
Expand Up @@ -16,13 +16,11 @@
# else
# define TARGET_VIRT_ADDR_SPACE_BITS 44
# endif
# define NB_MMU_MODES 6
#else
# define TARGET_LONG_BITS 32
# define TARGET_PAGE_BITS 12 /* 4k */
# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
# define NB_MMU_MODES 3
#endif

#endif
14 changes: 6 additions & 8 deletions target/sparc/translate.c
View file
Expand Up @@ -2838,7 +2838,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env)
static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
int width, bool cc, bool left)
{
TCGv lo1, lo2, t1, t2;
TCGv lo1, lo2;
uint64_t amask, tabl, tabr;
int shift, imask, omask;

Expand Down Expand Up @@ -2905,10 +2905,8 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
tcg_gen_shli_tl(lo1, lo1, shift);
tcg_gen_shli_tl(lo2, lo2, shift);

t1 = tcg_const_tl(tabl);
t2 = tcg_const_tl(tabr);
tcg_gen_shr_tl(lo1, t1, lo1);
tcg_gen_shr_tl(lo2, t2, lo2);
tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1);
tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2);
tcg_gen_andi_tl(dst, lo1, omask);
tcg_gen_andi_tl(lo2, lo2, omask);

Expand All @@ -2927,9 +2925,9 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
lo2 |= -(s1 == s2)
dst &= lo2
*/
tcg_gen_setcond_tl(TCG_COND_EQ, t1, s1, s2);
tcg_gen_neg_tl(t1, t1);
tcg_gen_or_tl(lo2, lo2, t1);
tcg_gen_setcond_tl(TCG_COND_EQ, lo1, s1, s2);
tcg_gen_neg_tl(lo1, lo1);
tcg_gen_or_tl(lo2, lo2, lo1);
tcg_gen_and_tl(dst, dst, lo2);
}

Expand Down
1 change: 0 additions & 1 deletion target/tricore/cpu-param.h
View file
Expand Up @@ -12,6 +12,5 @@
#define TARGET_PAGE_BITS 14
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define NB_MMU_MODES 3

#endif