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[Core] Copy RP2040 vector table to RAM on startup #18424

Merged
merged 1 commit into from
Sep 22, 2022
Merged

[Core] Copy RP2040 vector table to RAM on startup #18424

merged 1 commit into from
Sep 22, 2022

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KarlK90
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@KarlK90 KarlK90 commented Sep 19, 2022 •
edited

Description

Depends on ChibiOS/ChibiOS-Contrib#336 being merged first. merged, also to QMK develop.

...this reduces possible latency when invoking interrupt handlers by mitigating XIP cache misses which are not existent when running code from RAM.

Types of Changes

  • Core
  • Bugfix
  • New feature
  • Enhancement/optimization
  • Keyboard (addition or update)
  • Keymap/layout/userspace (addition or update)
  • Documentation

Issues Fixed or Closed by This PR

Checklist

  • My code follows the code style of this project: C, Python
  • I have read the PR Checklist document and have made the appropriate changes.
  • My change requires a change to the documentation.
  • I have updated the documentation accordingly.
  • I have read the CONTRIBUTING document.
  • I have added tests to cover my changes.
  • I have tested the changes and verified that they work and don't break anything (as well as I can manage).

@KarlK90
Copy RP2040 vector table to RAM on startup
6d5badd 
...this reduces possible latency when invoking interrupt handlers by
mitigating XIP cache misses which are not existent when running code from
RAM.
@github-actions github-actions bot added the core label Sep 19, 2022
@KarlK90 KarlK90 changed the title Copy RP2040 vector table to RAM on startup [Core] Copy RP2040 vector table to RAM on startup Sep 19, 2022
@KarlK90 KarlK90 marked this pull request as ready for review September 22, 2022 20:43
@KarlK90 KarlK90 requested a review from a team September 22, 2022 20:43
@zvecr zvecr merged commit b8ffaa6 into qmk:develop Sep 22, 2022
ramonimbao pushed a commit to ramonimbao/qmk_firmware that referenced this pull request Nov 28, 2022
@KarlK90 @ramonimbao
Copy RP2040 vector table to RAM on startup (qmk#18424)
f942067 
...this reduces possible latency when invoking interrupt handlers by
mitigating XIP cache misses which are not existent when running code from
RAM.
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@zvecr zvecr zvecr approved these changes

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