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编译了一个 小智 S3 的 u-boot 版本, 但是串口没有反应.

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qq516333132 committed Apr 7, 2019
1 parent dd6e874 commit 404c4f2d1a8c88c8db338111173683043d3ba6cf
@@ -282,6 +282,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-nanopi-neo.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN8I_S3) += \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
@@ -451,7 +451,7 @@ struct sunxi_ccm_reg {
/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
#define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
#define CCM_DE2_CTRL_PLL_MASK (3 << 24)
#ifndef CONFIG_MACH_SUN8I_V3S
#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
#define CCM_DE2_CTRL_PLL6_2X (0 << 24)
#define CCM_DE2_CTRL_PLL10 (1 << 24)
#else
@@ -31,7 +31,7 @@
#define SUNXI_PWM_MUX SUN8I_GPH_PWM
#endif

#if defined CONFIG_MACH_SUN8I_V3S
#if defined CONFIG_MACH_SUN8I_V3S || defined CONFIG_MACH_SUN8I_S3
#define SUNXI_PWM_PIN0 SUNXI_GPB(4)
#define SUNXI_PWM_MUX SUN8I_V3S_GPB_PWM
#endif
@@ -110,7 +110,7 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN8I_V3S) || defined(CONFIG_MACH_SUN8I_S3))
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
@@ -87,7 +87,7 @@ int print_cpuinfo(void)
printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_H3
printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_V3S
#elif defined CONFIG_MACH_SUN8I_V3S || defined CONFIG_MACH_SUN8I_S3
printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN9I
puts("CPU: Allwinner A80 (SUN9I)\n");
@@ -22,9 +22,9 @@ struct dram_para {
u8 bus_width;
u8 dual_rank;
u8 row_bits;
#ifdef CONFIG_SUNXI_H3_DRAM_DDR2
//#ifdef CONFIG_SUNXI_H3_DRAM_DDR2
u8 bank_bits;
#endif
//#endif
};

static inline int ns_to_t(int nanoseconds)
@@ -139,6 +139,17 @@ config MACH_SUN8I_V3S
select SUNXI_DE2
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

config MACH_SUN8I_S3
bool "sun8i (Allwinner S3)"
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select SUNXI_H3_DW_DRAM
select SUNXI_DE2
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
@@ -155,7 +166,7 @@ endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T || MACH_SUN8I_V3S
default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T || MACH_SUN8I_V3S || MACH_SUN8I_S3

config DRAM_TYPE
int "sunxi dram type"
@@ -0,0 +1,27 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
# CONFIG_ARMV7_NONSEC is not set
CONFIG_MACH_SUN8I_S3=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=14779
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_BL_PWM="PB4"
# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
# CONFIG_CONSOLE_MUX is not set
CONFIG_SPL=y
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_FPGA is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_NETDEVICES is not set
CONFIG_DM_SPI=y
CONFIG_SUNXI_SPI=y
CONFIG_OF_LIBFDT_OVERLAY=y
@@ -525,7 +525,7 @@ static void sunxi_composer_init(void)
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

#ifndef CONFIG_MACH_SUN8I_V3S
#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
clock_set_pll10(432000000);

/* Set DE parent to pll10 */
@@ -905,7 +905,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
int bp, clk_delay, clk_div, clk_double, pin, total, val;

#ifndef CONFIG_MACH_SUN8I_V3S
#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
#else
@@ -21,7 +21,7 @@
#define CONFIG_SUNXI_USB_PHYS 4
#elif defined CONFIG_MACH_SUN8I_A83T
#define CONFIG_SUNXI_USB_PHYS 3
#elif defined CONFIG_MACH_SUN8I_V3S
#elif (defined CONFIG_MACH_SUN8I_V3S) || (defined CONFIG_MACH_SUN8I_S3)
#define CONFIG_SUNXI_USB_PHYS 1
#else
#define CONFIG_SUNXI_USB_PHYS 2
@@ -77,7 +77,7 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_LOAD_ADDR 0x41000000 /* default load address */
/* V3s do not have enough memory to place code at 0x4a000000 */
#ifndef CONFIG_MACH_SUN8I_V3S
#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
#define CONFIG_SYS_TEXT_BASE 0x4a000000
#else
#define CONFIG_SYS_TEXT_BASE 0x42e00000
@@ -153,7 +153,7 @@
#define CONFIG_SYS_MMC_MAX_DEVICE 4
#endif

#ifndef CONFIG_MACH_SUN8I_V3S
#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
/* 64MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20))
#else
@@ -303,7 +303,7 @@ extern int soft_i2c_gpio_scl;
* The amount of RAM to keep free at the top of RAM when relocating u-boot,
* to use as framebuffer. This must be a multiple of 4096.
*/
#ifndef CONFIG_MACH_SUN8I_V3S
#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
#else
#define CONFIG_SUNXI_MAX_FB_SIZE (2 << 20)
@@ -410,7 +410,7 @@ extern int soft_i2c_gpio_scl;
* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end.
*/
#ifndef CONFIG_MACH_SUN8I_V3S
#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
#define BOOTM_SIZE __stringify(0xa000000)
#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
@@ -440,7 +440,7 @@ extern int soft_i2c_gpio_scl;
"pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
"ramdisk_addr_r=" RAMDISK_ADDR_R "\0"

#ifndef CONFIG_MACH_SUN8I_V3S
#if !defined(CONFIG_MACH_SUN8I_V3S) && !defined(CONFIG_MACH_SUN8I_S3)
#define DFU_ALT_INFO_RAM \
"dfu_alt_info_ram=" \
"kernel ram " KERNEL_ADDR_R " 0x1000000;" \

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