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Branch: XiaoZhi_S3_Sim…
Commits on Apr 23, 2019
Commits on Apr 7, 2019
Commits on Aug 12, 2017
  1. Merge branch 'v3s-current' into v3s-spi-experimental

    Icenowy committed Aug 12, 2017
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
  2. sunxi: fix SMP bit for V3s SoC

    Icenowy committed Aug 12, 2017
    The cache of Cortex-A7 is only enabled if the SMP bit is set, but the
    SMP bit of V3s is wrongly left unset, because I thought that it's not
    SMP-capable.
    
    Fix this.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Commits on May 23, 2017
  1. spi: sunxi: fix tx buf

    Icenowy committed May 23, 2017
    After a fifo length of data is sent to tx fifo, the tx buffer should be
    offseted.
    
    Do this offset after the transfer.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Commits on May 21, 2017
  1. sunxi: enable env on spi flash when spi flash is available

    Icenowy committed May 21, 2017
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
  2. sunxi: update defconfigs for Lichee Pi Zero for SPI

    Icenowy committed May 21, 2017
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
  3. spl: sunxi: Fix build error with CONFIG_SPL_SPI_SUNXI

    plaes authored and Icenowy committed Jan 2, 2017
    Fix typo introduced in ebc4ef6
    
    Signed-off-by: Priit Laes <plaes@plaes.org>
    Reviewed-by: Jagan Teki <jagan@openedev.com>
  4. sunxi: enable SPL SPI for all sun8i SoCs

    Icenowy committed May 21, 2017
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
  5. sunxi: enable SPI for Lichee Pi Zero

    Icenowy committed May 21, 2017
    Lichee Pi Zero have a SPI NOR solder pad.
    
    Enable the SPI on Lichee Pi Zero.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
  6. sunxi: add SPI0 node for V3s DTSI

    Icenowy committed May 21, 2017
    Allwinner V3s SoC has a SPI controller which is the same as the
    controllers in H3 SoC.
    
    Add a device tree node for it, so that it can be usable.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
  7. sunxi: spi: set up GPIO pins using pinctrl

    S.J.R. van Schaik authored and Icenowy committed Feb 23, 2017
  8. sunxi: add SPI driver for Allwinner devices (sunxi)

    StephanvanSchaik authored and Icenowy committed Feb 10, 2017
    Implements a driver model SPI driver for Allwinner devices (sunxi).
    
    Signed-off-by: S.J.R. van Schaik <stephan@whiteboxsystems.nl>
  9. sunxi: add SPI register definitions for sun6i/sun8i/sun9i/sun50i

    StephanvanSchaik authored and Icenowy committed Feb 10, 2017
    Introduces SPI registers for sun6i/sun8i/sun9i/sun50i by adding struct
    sunxi_spi_regs and flags.
    
    Signed-off-by: S.J.R. van Schaik <stephan@whiteboxsystems.nl>
  10. sunxi: add SPI register definitions for sun4i/sun7i

    StephanvanSchaik authored and Icenowy committed Feb 10, 2017
    Introduces SPI registers for sun4i/sun7i by adding struct sunxi_spi_regs
    and flags.
    
    Signed-off-by: S.J.R. van Schaik <stephan@whiteboxsystems.nl>
  11. sunxi: add missing AHB_GATE_OFFSET_SPIx defines for sun6i/sun9i

    StephanvanSchaik authored and Icenowy committed Feb 10, 2017
    Added missing AHB_GATE_OFFSET_SPIx defines to enable/disable clock gating for
    SPI on the sun6i and sun9i platforms.
    
    Signed-off-by: S.J.R. van Schaik <stephan@whiteboxsystems.nl>
Commits on May 20, 2017
  1. sunxi: enable fdt overlay in lcd-less Lichee Pi Zero defconfig

    Icenowy committed May 20, 2017
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Commits on Apr 13, 2017
  1. add Lichee Pi Zero with LCD defconfig's

    Icenowy committed Apr 13, 2017
    Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Commits on Jan 19, 2017
  1. sunxi: display: change pipeline string for DE2

    Icenowy committed Jan 15, 2017
    DE2 do not have dedicated BE or FE.
    
    Remove the "_be" suffix in the pipeline string of DE2.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
  2. sunxi: display: add simplefb support for V3s SoC

    Icenowy committed Jan 19, 2017
    V3s SoC features a DE2 composer.
    
    Add support for it.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Commits on Jan 13, 2017
  1. sunxi: Add clocks for DE2/HDMI/TCON

    jernejsk authored and Icenowy committed Dec 9, 2016
    This is needed for HDMI support, which will be added later.
    
    Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
    [Icenowy: renamed back lcd0_ch0_clk_cfg, add PLL3 for DE2 on V3s,
    and add CONFIG_SUNXI_DE2]
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
  2. sunxi: do a CCM quirk on V3s for USB to work properly

    Icenowy committed Dec 30, 2016
    USB OTG on V3s SoC seems to need the USB OTG clock gate to be passed and
    the reset to be deasserted before boot, otherwise it won't work in
    Linux.
    
    Add this quirk.
    
    Also add a generic quirk framework in sunxi's clock initialization code.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
  3. sunxi: low memory footprint for V3s

    Icenowy committed Dec 28, 2016
    V3s devices won't have enough memory to load U-Boot binary at
    0x4a000000, and they do not have enough memory to reserve 64MiB for
    malloc() (it has only 64MiB at all!)
    
    Change the DRAM mapping for it.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
  4. sunxi: add support for Lichee Pi Zero

    Icenowy committed Jan 7, 2017
    Lichee Pi Zero is a development board with a V3s SoC.
    
    Add support for it.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
  5. sunxi: add DTSI file for V3s

    Icenowy committed Jan 7, 2017
    As we have now V3s support in board code, the V3s DTSI file should also
    be added.
    
    Add also some CCU include headers to satisfy the DTSI file.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Commits on Dec 28, 2016
  1. sunxi: add basic V3s support

    Icenowy committed Dec 28, 2016
    Currently a working SPL for V3s can be built now.
    
    The U-Boot main binary still cannot work.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
  2. sunxi: add DDR2 support to H3-like DRAM controller

    Icenowy committed Dec 28, 2016
    H3-like DRAM controller needs some special code to operate a DDR2 DRAM
    chip. Add the logic to probe such a chip.
    
    As there's no commercial boards available now with H3 and DDR2 DRAM, the
    patch is developed and tested on a V3s chip, which has in-package DDR2
    DRAM.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
  3. sunxi: H3/A64: fix non-ODT setting

    Andre-ARM authored and Icenowy committed Aug 4, 2016
    According to Jens disabling the on-die-termination should set bit 5,
    not bit 1 in the respective register. Fix this.
    
    Reported-by: Jens Kuske <jenskuske@gmail.com>
    Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  4. sunxi: makes an invisible option for H3-like DRAM controllers

    Icenowy committed Dec 28, 2016
    Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
    DesignWare DRAM controller, which do not have official free DRAM
    initialization code, but can use modified dram_sun8i_h3.c.
    
    Add a invisible option for easier DRAM initialization code reuse.
    
    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Commits on Dec 23, 2016
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