For pinctrl

Makefile

@@ -5,6 +5,7 @@ SUBLEVEL = 0
 EXTRAVERSION = -rc1
 NAME = Baby Opossum Posse
 
+# This is a dummy change
 # *DOCUMENTATION*
 # To see a list of typical targets execute "make help"
 # More info can be located in ./README

drivers/pinctrl/qcom/Kconfig

@@ -59,6 +59,16 @@ config PINCTRL_LPASS_LPI
 	  Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
 	  (Low Power Island) found on the Qualcomm Technologies Inc SoCs.
 
+config PINCTRL_QCS8300_LPASS_LPI
+	tristate "Qualcomm Technologies Inc QCS8300 LPASS LPI pin controller driver"
+	depends on ARM64 || COMPILE_TEST
+	depends on PINCTRL_LPASS_LPI
+	help
+	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+	  Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+	  (Low Power Island) found on the Qualcomm Technologies Inc QCS8300
+	  platform.
+
 config PINCTRL_SC7280_LPASS_LPI
 	tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
 	depends on ARM64 || COMPILE_TEST
@@ -143,4 +153,14 @@ config PINCTRL_SM8650_LPASS_LPI
 	  (Low Power Island) found on the Qualcomm Technologies Inc SM8650
 	  platform.
 
+config PINCTRL_SA8775P_LPASS_LPI
+	tristate "Qualcomm Technologies Inc SA8775P LPASS LPI pin controller driver"
+	depends on ARM64 || COMPILE_TEST
+	depends on PINCTRL_LPASS_LPI
+	help
+	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+	  Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+	  (Low Power Island) found on the Qualcomm Technologies Inc SA8775P
+	  platform.
+
 endif

drivers/pinctrl/qcom/Kconfig.msm

@@ -226,6 +226,14 @@ config PINCTRL_QDU1000
 	  Qualcomm Technologies Inc TLMM block found on the Qualcomm
 	  Technologies Inc QDU1000 and QRU1000 platforms.
 
+config PINCTRL_SA7255P
+	tristate "Qualcomm Technologies Inc SA7255P pin controller driver"
+	depends on ARM64 || COMPILE_TEST
+	help
+	  This is the pinctrl, pinmux and pinconf driver for the Qualcomm
+	  Technologies Inc TLMM block found on the Qualcom TLMM block
+	  found on the Qualcomm SA7255P platforms.
+
 config PINCTRL_SA8775P
 	tristate "Qualcomm Technologies Inc SA8775P pin controller driver"
 	depends on ARM64 || COMPILE_TEST

drivers/pinctrl/qcom/Makefile

@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_QCM2290)	+= pinctrl-qcm2290.o
 obj-$(CONFIG_PINCTRL_QCS404)	+= pinctrl-qcs404.o
 obj-$(CONFIG_PINCTRL_QCS615)    += pinctrl-qcs615.o
 obj-$(CONFIG_PINCTRL_QCS8300)	+= pinctrl-qcs8300.o
+obj-$(CONFIG_PINCTRL_QCS8300_LPASS_LPI) += pinctrl-qcs8300-lpass-lpi.o
 obj-$(CONFIG_PINCTRL_QDF2XXX)	+= pinctrl-qdf2xxx.o
 obj-$(CONFIG_PINCTRL_MDM9607)	+= pinctrl-mdm9607.o
 obj-$(CONFIG_PINCTRL_MDM9615)	+= pinctrl-mdm9615.o
@@ -35,8 +36,10 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
 obj-$(CONFIG_PINCTRL_QDU1000)	+= pinctrl-qdu1000.o
+obj-$(CONFIG_PINCTRL_SA7255P)	+= pinctrl-sa7255p.o
 obj-$(CONFIG_PINCTRL_SA8775P)	+= pinctrl-sa8775p.o
 obj-$(CONFIG_PINCTRL_SAR2130P)	+= pinctrl-sar2130p.o
+obj-$(CONFIG_PINCTRL_SA8775P_LPASS_LPI) += pinctrl-sa8775p-lpass-lpi.o
 obj-$(CONFIG_PINCTRL_SC7180)	+= pinctrl-sc7180.o
 obj-$(CONFIG_PINCTRL_SC7280)	+= pinctrl-sc7280.o
 obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o

drivers/pinctrl/qcom/pinctrl-lpass-lpi.c

@@ -2,6 +2,7 @@
 /*
  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  * Copyright (c) 2020 Linaro Ltd.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/bitfield.h>
@@ -10,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/seq_file.h>
 
 #include <linux/pinctrl/pinconf-generic.h>
@@ -24,6 +26,8 @@
 #define GPIO_FUNC		0
 #define MAX_LPI_NUM_CLKS	2
 
+static struct device *lpi_dev;
+
 struct lpi_pinctrl {
 	struct device *dev;
 	struct pinctrl_dev *ctrl;
@@ -34,21 +38,35 @@ struct lpi_pinctrl {
 	struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
 	/* Protects from concurrent register updates */
 	struct mutex lock;
+	/* Protects from concurrent clock updates */
+	struct mutex lpi_lock;
 	DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO);
 	const struct lpi_pinctrl_variant_data *data;
 };
 
 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
 			 unsigned int addr)
 {
-	return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
+	int ret = 0;
+
+	pm_runtime_get_sync(lpi_dev);
+
+	ret = ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
+
+	pm_runtime_mark_last_busy(lpi_dev);
+	pm_runtime_put_autosuspend(lpi_dev);
+	return ret;
 }
 
 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
 			  unsigned int addr, unsigned int val)
 {
+	pm_runtime_get_sync(lpi_dev);
+
 	iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
 
+	pm_runtime_mark_last_busy(lpi_dev);
+	pm_runtime_put_autosuspend(lpi_dev);
 	return 0;
 }
 
@@ -448,6 +466,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
 
 	pctrl->data = data;
 	pctrl->dev = &pdev->dev;
+	lpi_dev = &pdev->dev;
 
 	pctrl->clks[0].id = "core";
 	pctrl->clks[1].id = "audio";
@@ -487,6 +506,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
 	pctrl->chip.can_sleep = false;
 
 	mutex_init(&pctrl->lock);
+	mutex_init(&pctrl->lpi_lock);
 
 	pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
 	if (IS_ERR(pctrl->ctrl)) {
@@ -505,10 +525,16 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
 		goto err_pinctrl;
 	}
 
+	pm_runtime_set_autosuspend_delay(dev, 100);
+	pm_runtime_use_autosuspend(dev);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+
 	return 0;
 
 err_pinctrl:
 	mutex_destroy(&pctrl->lock);
+	mutex_destroy(&pctrl->lpi_lock);
 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
 
 	return ret;
@@ -521,12 +547,38 @@ void lpi_pinctrl_remove(struct platform_device *pdev)
 	int i;
 
 	mutex_destroy(&pctrl->lock);
+	mutex_destroy(&pctrl->lpi_lock);
 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
 
 	for (i = 0; i < pctrl->data->npins; i++)
 		pinctrl_generic_remove_group(pctrl->ctrl, i);
 }
 EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
 
+int lpi_pinctrl_runtime_suspend(struct device *dev)
+{
+	struct lpi_pinctrl *pctrl = dev_get_drvdata(dev);
+
+	mutex_lock(&pctrl->lpi_lock);
+	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
+	mutex_unlock(&pctrl->lpi_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(lpi_pinctrl_runtime_suspend);
+
+int lpi_pinctrl_runtime_resume(struct device *dev)
+{
+	int ret;
+	struct lpi_pinctrl *pctrl = dev_get_drvdata(dev);
+
+	mutex_lock(&pctrl->lpi_lock);
+	ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
+	mutex_unlock(&pctrl->lpi_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(lpi_pinctrl_runtime_resume);
+
 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
 MODULE_LICENSE("GPL");

drivers/pinctrl/qcom/pinctrl-lpass-lpi.h

@@ -2,6 +2,7 @@
 /*
  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  * Copyright (c) 2020 Linaro Ltd.
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 #ifndef __PINCTRL_LPASS_LPI_H__
 #define __PINCTRL_LPASS_LPI_H__
@@ -89,5 +90,7 @@ struct lpi_pinctrl_variant_data {
 
 int lpi_pinctrl_probe(struct platform_device *pdev);
 void lpi_pinctrl_remove(struct platform_device *pdev);
+int lpi_pinctrl_runtime_suspend(struct device *dev);
+int lpi_pinctrl_runtime_resume(struct device *dev);
 
 #endif /*__PINCTRL_LPASS_LPI_H__*/

drivers/pinctrl/qcom/pinctrl-qcs615.c

@@ -1062,7 +1062,7 @@ static const struct msm_pinctrl_soc_data qcs615_tlmm = {
 	.nfunctions = ARRAY_SIZE(qcs615_functions),
 	.groups = qcs615_groups,
 	.ngroups = ARRAY_SIZE(qcs615_groups),
-	.ngpios = 123,
+	.ngpios = 124,
 	.tiles = qcs615_tiles,
 	.ntiles = ARRAY_SIZE(qcs615_tiles),
 	.wakeirq_map = qcs615_pdc_map,