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cirq.optimize_for_target_gateset(circuit, gateset=cirq_ionq.IonQTargetGateset()) doesn't take advantage of ion trap's all-to-all connectivity #6068

@vtomole

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@vtomole

The text book compilation of the Toffoli gate consists of 6 CX gates with a depth of 12. This is because textbook compilations don't take into account the connectivity of the device it compiles to. A pro of the Ion trap architecture is it's all-to-all connectivity. It seems like Cirq is not using that to compile to the best circuit suited for the ion trap.

import cirq
import cirq_ionq

circuit = cirq.optimize_for_target_gateset(
    cirq.Circuit(cirq.TOFFOLI(cirq.q(0), cirq.q(1), cirq.q(2))),
    gateset=cirq_ionq.IonQTargetGateset(),
)


print(circuit)
# prints
# 0: ───T───@──────────────@───────@──────────@──────────────
#           │              │       │          │
# 1: ───T───X───@───T^-1───X───@───X──────@───X──────@───────
#               │              │          │          │
# 2: ───H───T───X───T──────────X───T^-1───X───T^-1───X───H───


print(f"Depth: {len(circuit)}")
print(
    f"Number of CX gates: {len([op for op in circuit.all_operations() if isinstance(op.gate, cirq.CXPowGate)])}"
)
# prints
# Depth: 11
# Number CX gates: 8

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    architecture/ion-trapIon trap quantum computer related issuesarea/decompositionarea/gate-compilationgood first issueThis issue can be resolved by someone who is not familiar with the codebase. A good starting issue.kind/design-issueA conversation around designpriority/p3Should be done in the next 6 monthstriage/acceptedA consensus emerged that this bug report, feature request, or other action should be worked on

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